CN106068505A - 共享总线上的比特分配以促成检错优化 - Google Patents

共享总线上的比特分配以促成检错优化 Download PDF

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Publication number
CN106068505A
CN106068505A CN201580010556.1A CN201580010556A CN106068505A CN 106068505 A CN106068505 A CN 106068505A CN 201580010556 A CN201580010556 A CN 201580010556A CN 106068505 A CN106068505 A CN 106068505A
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CN
China
Prior art keywords
bit
word
minimum effective
data
agreement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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CN201580010556.1A
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English (en)
Chinese (zh)
Inventor
S·森戈库
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Qualcomm Inc
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Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106068505A publication Critical patent/CN106068505A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095—Error detection codes other than CRC and single parity bit codes
    • H03M13/096—Checksums
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Information Transfer Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
CN201580010556.1A 2014-02-28 2015-02-28 共享总线上的比特分配以促成检错优化 Pending CN106068505A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461946647P 2014-02-28 2014-02-28
US61/946,647 2014-02-28
US14/634,106 2015-02-27
US14/634,106 US20150248373A1 (en) 2014-02-28 2015-02-27 Bit allocation over a shared bus to facilitate an error detection optimization
PCT/US2015/018202 WO2015131164A1 (en) 2014-02-28 2015-02-28 Bit allocation over a shared bus to facilitate an error detection optimization

Publications (1)

Publication Number Publication Date
CN106068505A true CN106068505A (zh) 2016-11-02

Family

ID=54006839

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580010556.1A Pending CN106068505A (zh) 2014-02-28 2015-02-28 共享总线上的比特分配以促成检错优化

Country Status (6)

Country Link
US (1) US20150248373A1 (https=)
EP (1) EP3111561A1 (https=)
JP (1) JP2017511044A (https=)
KR (1) KR20160125411A (https=)
CN (1) CN106068505A (https=)
WO (1) WO2015131164A1 (https=)

Families Citing this family (16)

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WO2013046734A1 (ja) * 2011-09-27 2013-04-04 三菱電機株式会社 スレーブ装置、マスター装置及び通信方法
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US9519603B2 (en) 2013-09-09 2016-12-13 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9678828B2 (en) 2013-10-09 2017-06-13 QUAULCOMM Incorporated Error detection capability over CCIe protocol
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9684624B2 (en) 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
WO2015126983A1 (en) * 2014-02-18 2015-08-27 Qualcomm Incorporated Technique to avoid metastability condition and avoid unintentional state changes of legacy i2c devices on a multi-mode bus
US10019306B2 (en) * 2016-04-27 2018-07-10 Western Digital Technologies, Inc. Collision detection for slave storage devices
WO2017189206A1 (en) * 2016-04-27 2017-11-02 Qualcomm Incorporated I3c high data rate (hdr) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
JP6786871B2 (ja) 2016-05-18 2020-11-18 ソニー株式会社 通信装置、通信方法、プログラム、および、通信システム
US20180054216A1 (en) * 2016-08-22 2018-02-22 Qualcomm Incorporated Flipped bits for error detection and correction for symbol transition clocking transcoding
JP6953226B2 (ja) * 2017-08-04 2021-10-27 ソニーセミコンダクタソリューションズ株式会社 通信装置、通信方法、プログラム、および、通信システム
JP7031961B2 (ja) * 2017-08-04 2022-03-08 ソニーセミコンダクタソリューションズ株式会社 通信装置、通信方法、プログラム、および、通信システム
JP2023089317A (ja) * 2020-05-11 2023-06-28 ソニーセミコンダクタソリューションズ株式会社 通信装置及び通信システム
TWI837031B (zh) * 2023-06-28 2024-03-21 明泰科技股份有限公司 I2c匯流排監控裝置

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US5872519A (en) * 1992-05-22 1999-02-16 Directed Electronics, Inc. Advanced embedded code hopping system
US6370668B1 (en) * 1999-07-23 2002-04-09 Rambus Inc High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
US20070016694A1 (en) * 2001-12-17 2007-01-18 Isaac Achler Integrated circuits for high speed adaptive compression and methods therefor
US20070234136A1 (en) * 2006-03-31 2007-10-04 Emc Corporation Method and apparatus for detecting the presence of errors in data transmitted between components in a data storage system using an I2C protocol
US20080244370A1 (en) * 2007-03-30 2008-10-02 Chung Hon Lam Multi-bit memory error detection and correction system and method
US20090316724A1 (en) * 2008-06-19 2009-12-24 Nokia Corporation Electronically configurable interface
US20120117287A1 (en) * 2010-11-08 2012-05-10 Denso Corporation Communication system, master node, and slave node
CN102567250A (zh) * 2010-11-29 2012-07-11 意法半导体股份有限公司 具有可通过降低数量的端子编程的地址的电子设备

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FR2542531B1 (fr) * 1983-03-09 1988-05-20 Telephonie Ind Commerciale Procede et dispositifs de transcodage d'informations binaires pour transmission multiplexe temporelle
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US9678828B2 (en) * 2013-10-09 2017-06-13 QUAULCOMM Incorporated Error detection capability over CCIe protocol

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Publication number Priority date Publication date Assignee Title
US5872519A (en) * 1992-05-22 1999-02-16 Directed Electronics, Inc. Advanced embedded code hopping system
CN1082288A (zh) * 1992-06-22 1994-02-16 国际商业机器公司 等时权标环用的枢纽和接口
US6370668B1 (en) * 1999-07-23 2002-04-09 Rambus Inc High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
US20070016694A1 (en) * 2001-12-17 2007-01-18 Isaac Achler Integrated circuits for high speed adaptive compression and methods therefor
US20070234136A1 (en) * 2006-03-31 2007-10-04 Emc Corporation Method and apparatus for detecting the presence of errors in data transmitted between components in a data storage system using an I2C protocol
US20080244370A1 (en) * 2007-03-30 2008-10-02 Chung Hon Lam Multi-bit memory error detection and correction system and method
US20090316724A1 (en) * 2008-06-19 2009-12-24 Nokia Corporation Electronically configurable interface
US20120117287A1 (en) * 2010-11-08 2012-05-10 Denso Corporation Communication system, master node, and slave node
CN102567250A (zh) * 2010-11-29 2012-07-11 意法半导体股份有限公司 具有可通过降低数量的端子编程的地址的电子设备

Also Published As

Publication number Publication date
EP3111561A1 (en) 2017-01-04
KR20160125411A (ko) 2016-10-31
WO2015131164A1 (en) 2015-09-03
US20150248373A1 (en) 2015-09-03
JP2017511044A (ja) 2017-04-13

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