CN106055001A - Improved reference current source circuit - Google Patents

Abstract

The invention relates to an improved reference current source circuit. The reference current source includes a mirror current source consisting of MOS transistors; and a negative feedback loop is introduced through a third PMOS transistor MP3 and a third NMOS transistor MN3. The problem that the precision of the reference current source is low due to a second-order effect of a circuit, in particular to current mismatch caused by MOS channel length modulation effect, in reference current source circuits of automatic biasing structures and current source circuits of peak structures can be solved; an improved circuit structure for suppressing the channel length modulation effect is provided; and the negative feedback loop is introduced to eliminate the MOS channel length modulation effect of the reference current source, and the high precision reference current source can be achieved.

Description

A kind of reference current source circuit of improvement

Technical field

The invention belongs to integrated circuit fields, the reference current source circuit of a kind of improvement.

Background technology

In the design of integrated circuit, reference current source be decision-making circuit performance and reliability work key factor it One.It is the current offset needed for other circuit provide that reference current source generally passes through current mirror mirror image, therefore refers to current source Precision determines the precision of other bias circuit current, or even the performance of whole Circuits System.

Fig. 1 is the reference current source circuit unrelated with supply voltage, temperature of automatic biasing structure.By MP1, MP2, MN1, The auto bias circuit structure of MN2 composition, introduces audion Q1, Q2 and resistance R1, R2 restriction relation, thus obtains one with electric The reference current source that source voltage, temperature are unrelated.Wherein MP1 Yu MP2, MN1 Yu MN2 are respectively one group of current mirror.

$I_D\≈\frac{1}{2}{\mathrm{\μC}}_{OX}\frac{W}{L}{(V_{GS}-V_{TH})}^2(1+{\mathrm{\λV}}_{DS})---\left(1\right)$

Wherein μ is electron mobility parameter；C_oxGate oxide capacitance for unit area；V_THFor NMOS tube threshold voltage, λ is channel length modulation coefficient.

Formula (1) is to consider metal-oxide-semiconductor " square-law " formula of channel-length modulation, for MP1 and MP2, V_DS,MP2= V_GS,MP2>V_DS,MP1, for MN1 and MN2, V_DS,MN1=V_GS,MN1>V_DS,MN2；Due to mirror image pipe and the source-drain voltage V being mirrored pipe_DS Difference, cause electric current can not accurately mirror image, thus affect the precision of reference current source.

Fig. 2 is the reference current source circuit unrelated with supply voltage of peak value structure.Also due to the source and drain of MP1 Yu MP2 Voltage V_DSDifference, cause electric current can not accurately mirror image, thus affect the precision of reference current source.

Summary of the invention

The technical problem to be solved in the present invention is existing automatic biasing structural reference current source circuit, peak value structural reference electric current Source circuit, due to MOS channel-length modulation cause electric current can not accurately mirror image, thus affect the essence of reference current source The problem of degree, it is provided that the reference current source circuit of a kind of improvement, by the basis of original circuit structure, introduces one and bears anti- Feedback loop, eliminates the MOS channel-length modulation of reference current source, to realize high-precision reference current source.

In order to solve above-mentioned technical problem, the invention provides following technical scheme:

The reference current source circuit of a kind of improvement of the present invention, reference current source circuit includes the mirror image electricity being made up of metal-oxide-semiconductor Stream source, introduces one article of feedback loop by the 3rd PMOS MP3, the 3rd NMOS tube MN3.

Further, by the first PMOS MP1 and the second PMOS MP2, the first NMOS tube MN1 in reference current source circuit The 3rd PMOS MP3 that is connected with two groups of mirror current sources of the second NMOS tube MN2 and two groups of mirror current sources, the 3rd NMOS tube The feedback loop composition automatic biasing structure that MN3 is constituted.

Further, the reference current source circuit of automatic biasing structure include the first PMOS MP1, the second PMOS MP2, Three PMOS MP3, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, a NPN audion Q1, the 2nd NPN Audion Q2, the 3rd NPN audion Q3, the first resistance R1 and the second resistance R2, the first PMOS MP1, the second PMOS MP2, The source electrode of the 3rd PMOS MP3 is connected with power end VDD；The grid of the first PMOS MP1 and the grid of the second PMOS MP2 and Drain electrode, the drain electrode of the second NMOS tube MN2 connect；First PMOS MP1 drain electrode with the grid of the 3rd PMOS MP3, first The drain electrode of NMOS tube MN1 connects；Drain electrode and the drain and gate of the 3rd NMOS tube MN3, first NMOS tube of the 3rd PMOS MP3 The grid of MN1, the grid of the second NMOS tube MN2 connect；The source electrode of the 3rd NMOS tube MN3 and the current collection of the 3rd NPN audion Q3 Pole and base stage connect；The source electrode of the first NMOS tube MN1 and the colelctor electrode of the 2nd NPN audion Q2, second resistance R2 one end connect； The base stage of the second NMOS tube MN2 and the colelctor electrode of a NPN audion Q1 and base stage, the 2nd NPN audion Q2 connects；Second The emitter stage of NPN audion Q2 and one end of the first resistance R1 connect；The emitter stage of the oneth NPN audion Q1, the 3rd NPN tri-pole The emitter stage of pipe Q3, the other end of the first resistance R1, the other end of the second resistance R2 are connected to ground.

Further, by the first PMOS MP1 and mono-group of image current of the second PMOS MP2 in reference current source circuit The 3rd PMOS MP3, the feedback loop of the 3rd NMOS tube MN3 composition that source is connected with one group of mirror current source form peak value Structure.

Further, the reference current source circuit of peak value structure include the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the first resistance R1 and the second resistance R2, the One PMOS MP1, the second PMOS MP2, the source electrode of the 3rd PMOS MP3 are connected with power end VDD；First PMOS MP1 Grid and the grid of the second PMOS MP2, the grid of the 3rd PMOS MP3 and drain electrode, the drain electrode of the 3rd NMOS tube MN3, second One end of resistance R2 connects；The drain electrode of the first PMOS MP1 connects with one end of the drain electrode of the second NMOS tube MN2, the first resistance R1 Connect；The other end of the first resistance R1 and the grid of the first NMOS tube MN1 and drain electrode connect；The drain electrode of the second PMOS MP2 and the The drain electrode of two NMOS tube MN2, the grid of the 3rd NMOS tube MN3 connect；First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the other end of the second resistance R2 are connected to ground.

Beneficial effects of the present invention: in order to solve the reference electricity of the reference current source circuit of automatic biasing structure, peak value structure Due to the second-order effects of circuit in current source circuit, the current mismatch that particularly MOS channel-length modulation causes causes reference Current source precision ratio is relatively low, it is proposed that the circuit structure of the suppression channel-length modulation of improvement, negative anti-by introducing one Feedback loop, eliminates the MOS channel-length modulation of reference current source, to realize high-precision reference current source.

Accompanying drawing explanation

The present invention is further described with embodiment below in conjunction with the accompanying drawings.

Fig. 1 is the reference current source circuit schematic diagram unrelated with supply voltage, temperature of existing automatic biasing structure；

Fig. 2 is the reference current source circuit schematic diagram unrelated with supply voltage of existing peak value structure；

Fig. 3 is the reference current source circuit schematic diagram of the automatic biasing structure improved；

Fig. 4 is the reference current source circuit schematic diagram of the peak value structure improved.

Detailed description of the invention

The reference current source circuit of a kind of improvement of the present invention, including the mirror current source being made up of metal-oxide-semiconductor, by the 3rd PMOS MP3, the 3rd NMOS tube MN3 introduce one article of feedback loop.

Embodiment one: the reference current source circuit of the automatic biasing structure of improvement.

As it is shown on figure 3, the source electrode of the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3 and power end VDD Connect；The drain electrode of the grid of the first PMOS MP1 and the grid of the second PMOS MP2 and drain electrode, the second NMOS tube MN2 connects； The drain electrode of the first PMOS MP1 is connected with grid, the drain electrode of the first NMOS tube MN1 of the 3rd PMOS MP3；3rd PMOS Drain electrode and the drain and gate of the 3rd NMOS tube MN3, the grid of the first NMOS tube MN1, the grid of the second NMOS tube MN2 of MP3 Connect；The source electrode of the 3rd NMOS tube MN3 and the colelctor electrode of the 3rd NPN audion Q3 and base stage connect；The source of the first NMOS tube MN1 Pole is connected with colelctor electrode, second resistance R2 one end of the 2nd NPN audion Q2；Second NMOS tube MN2 and a NPN audion Q1 Colelctor electrode and base stage, the 2nd NPN audion Q2 base stage connect；The emitter stage of the 2nd NPN audion Q2 and the first resistance R1 One end connect；The emitter stage of the oneth NPN audion Q1, the emitter stage of the 3rd NPN audion Q3, the first resistance R1, the second electricity Resistance R2 is connected to ground.

Embodiment two: the reference current source circuit of the peak value structure of improvement.

As shown in Figure 4, source electrode and the power end VDD of the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3 Connect；The grid of the first PMOS MP1 and the grid of the second PMOS MP2, the grid of the 3rd PMOS and drain electrode, the 3rd NMOS tube Drain electrode, the second resistance R2 one end connect；Drain electrode and the drain electrode of the second NMOS tube MN2, first resistance of the first PMOS MP1 One end of R1 connects；The other end of the first resistance R1 and the grid of the first NMOS tube MN1 and drain electrode connect；Second PMOS MP2 Drain electrode be connected with drain electrode, the grid of the 3rd NMOS tube MN3 of the second NMOS tube MN2；First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the other end of the second resistance R2 are connected to ground.

The circuit of scheme one and scheme two introduces one article of negative feedback loop by the 3rd PMOS MP3, the 3rd NMOS tube MN3 Road, forces the source and drain of PMOS MP1 is pressed V_DS,MP1Fall clamp is V_GS, the source and drain equal to MP2 presses V_GS,MP2.According to formula (1), suppression First PMOS MP1, the leakage current mismatch of the second PMOS MP2, improve the precision of reference current source.

In the present invention, the word that the expression such as " connection ", " being connected ", " company ", " connecing " is electrical connected, if no special instructions, Then represent direct or indirect electric connection.First end of above-mentioned all resistance and the second end are all the sides of flowing through according to electric current To definition, the one end of the resistance that electric current first passes around is the first end, and the other end is just the second end.

With the above-mentioned desirable embodiment according to the present invention for enlightenment, by above-mentioned description, the art general Logical technical staff can carry out various change and amendment completely in the range of without departing from this invention technological thought.This The content that the technical scope of item invention is not limited in description, it is necessary to determine its technology according to right Property scope.

Claims (5)

1. the reference current source circuit improved, reference current source circuit includes the mirror current source being made up of metal-oxide-semiconductor, and it is special Levy and be: introduce one article of feedback loop by the 3rd PMOS MP3, the 3rd NMOS tube MN3.

The reference current source circuit of improvement the most according to claim 1, it is characterised in that: in described reference current source circuit By the first PMOS MP1 and the second PMOS MP2, the first NMOS tube MN1 and two groups of mirror current sources of the second NMOS tube MN2 and The feedback loop composition automatic biasing knot that 3rd PMOS MP3 of two groups of mirror current source connections, the 3rd NMOS tube MN3 are constituted Structure.

The reference current source circuit of improvement the most according to claim 2, it is characterised in that: the reference of described automatic biasing structure Current source circuit include the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1, second NMOS tube MN2, the 3rd NMOS tube MN3, a NPN audion Q1, the 2nd NPN audion Q2, the 3rd NPN audion Q3, first Resistance R1 and the second resistance R2, the first PMOS MP1, the second PMOS MP2, source electrode and the power end VDD of the 3rd PMOS MP3 Connect；The drain electrode of the grid of the first PMOS MP1 and the grid of the second PMOS MP2 and drain electrode, the second NMOS tube MN2 connects； The drain electrode of the first PMOS MP1 is connected with grid, the drain electrode of the first NMOS tube MN1 of the 3rd PMOS MP3；3rd PMOS Drain electrode and the drain and gate of the 3rd NMOS tube MN3, the grid of the first NMOS tube MN1, the grid of the second NMOS tube MN2 of MP3 Connect；The source electrode of the 3rd NMOS tube MN3 and the colelctor electrode of the 3rd NPN audion Q3 and base stage connect；The source of the first NMOS tube MN1 Pole is connected with colelctor electrode, second resistance R2 one end of the 2nd NPN audion Q2；Second NMOS tube MN2 and a NPN audion Q1 Colelctor electrode and base stage, the 2nd NPN audion Q2 base stage connect；The emitter stage of the 2nd NPN audion Q2 and the first resistance R1 One end connect；The emitter stage of the oneth NPN audion Q1, the emitter stage of the 3rd NPN audion Q3, the first resistance R1 another End, the other end of the second resistance R2 are connected to ground.

The reference current source circuit of improvement the most according to claim 1, it is characterised in that: in described reference current source circuit The 3rd PMOS connected by the first PMOS MP1 and mono-group of mirror current source of the second PMOS MP2 and one group of mirror current source The feedback loop composition peak value structure that MP3, the 3rd NMOS tube MN3 are constituted.

The reference current source circuit of improvement the most according to claim 4, it is characterised in that: the reference electricity of described peak value structure Current source circuit includes the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1, the 2nd NMOS Pipe MN2, the 3rd NMOS tube MN3, the first resistance R1 and the second resistance R2, the first PMOS MP1, the second PMOS MP2, the 3rd The source electrode of PMOS MP3 is connected with power end VDD；The grid of the first PMOS MP1 and the grid of the second PMOS MP2, the 3rd The grid of PMOS MP3 and drain electrode, the drain electrode of the 3rd NMOS tube MN3, one end of the second resistance R2 connect；First PMOS MP1 Drain electrode be connected with drain electrode, one end of the first resistance R1 of the second NMOS tube MN2；The other end of the first resistance R1 and a NMOS The grid of pipe MN1 and drain electrode connect；Drain electrode and the drain electrode of the second NMOS tube MN2, the 3rd NMOS tube MN3 of the second PMOS MP2 Grid connect；First NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the other end of the second resistance R2 connect with ground Connect.