CN111522391A - Bias circuit irrelevant to power supply voltage - Google Patents
Bias circuit irrelevant to power supply voltage Download PDFInfo
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- CN111522391A CN111522391A CN202010382071.8A CN202010382071A CN111522391A CN 111522391 A CN111522391 A CN 111522391A CN 202010382071 A CN202010382071 A CN 202010382071A CN 111522391 A CN111522391 A CN 111522391A
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- nmos transistor
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- power supply
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
The invention discloses a bias circuit irrelevant to power supply voltage, which comprises three PMOS (P-channel metal oxide semiconductor) tubes, three NMOS (N-channel metal oxide semiconductor) tubes and a resistor R0, wherein a first PMOS tube P0 is connected into a diode structure and forms a current mirror with a second PMOS tube P1; the third NMOS transistor N2 is connected as a diode structure and forms a current mirror with the first NMOS transistor N0; the source of the third PMOS transistor P2 is connected to the power supply VDD, and forms a current branch with the third NMOS transistor N2. The invention can reduce the influence of the power supply voltage change on the magnitude of the bias current to the maximum extent, thereby effectively reducing the change of the system quiescent current along with the power supply voltage.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a bias circuit irrelevant to power supply voltage.
Background
With the progress of the CMOS process, the development trend of integrated circuits is that the integration level is higher and higher, the power supply voltage is lower and lower, and the power consumption is lower and lower; low voltage and low power design is the mainstream direction of integrated circuit development. The rapid development of integrated circuits and the continuous expansion of their application fields require that the chip not only has low power consumption, but also can meet the requirement of wide power supply voltage.
The bias circuit provides a static operating point and bias current for other devices in the circuit to complete specific functions; to some extent, the magnitude of the bias current determines the magnitude of the quiescent current of the entire circuit, and even the total current. The change of the bias current along with the power supply voltage is effectively reduced, and the method is an effective way for improving the power supply stability of the whole circuit quiescent current and even the total current. The conventional bias circuit independent of the power supply still has certain power supply dependence.
As shown in fig. 1, which is a conventional bias circuit independent of power supply, PMOS transistors P00 and P10 form a current mirror structure, and the current ratio is set to 1: 1; the ratio of the sizes (W/L) of the NMOS tubes N00 and N10 is 1: m; under the condition of not considering the channel length modulation effect, the currents of the two branches are equal, namely the two branches are
For the conventional bias circuit, under the condition that the variation range of the power supply voltage is relatively large, the potentials of the nodes A0 and B0 have a large difference, and due to the channel length modulation effect, the currents of the PMOS transistors P0 and P1 are not equal, which causes the deviation of the output bias current; therefore, the current change caused by the channel length modulation effect is not negligible, as shown in equation (2):
disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a bias circuit irrelevant to power supply voltage, so that the influence of the change of the power supply voltage on the magnitude of bias current can be reduced to the greatest extent, and the change of the static current of a system along with the change of the power supply voltage can be effectively reduced.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention relates to a bias circuit irrelevant to power supply voltage, which is characterized by comprising the following components:
three PMOS tubes: a first PMOS transistor P0, a second PMOS transistor P1 and a third PMOS transistor P2; three NMOS tubes: a first NMOS transistor N0, a second NMOS transistor N1, a third NMOS transistor N2 and a resistor R0;
the source electrode of the first NMOS transistor N0 is grounded; the drain electrode of the first NMOS transistor N0, the grid electrode and the drain electrode of the first PMOS transistor P0, and the grid electrode of the second PMOS transistor P1 are connected to the point A;
the source electrode of the first PMOS transistor P0 and the source electrode of the second PMOS transistor P1 are both connected to a power supply VDD; the first PMOS tube P0 is connected into a diode structure and forms a current mirror with the second PMOS tube P1;
the source electrode of the third NMOS transistor N2 is grounded, the grid electrode and the drain electrode of the third NMOS transistor N2, the grid electrode of the first NMOS transistor N0, the grid electrode of the second NMOS transistor N1 and the drain electrode of the third PMOS transistor P2 are connected to a node C; the third NMOS transistor N2 is connected to form a diode structure, and forms a current mirror with the first NMOS transistor N0;
the source electrode of the second NMOS transistor N1 is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the ground potential; the drain electrode of the second NMOS transistor N1, the drain electrode of the second PMOS transistor P1 and the gate electrode of the third PMOS transistor P2 are all connected to a node B; the source of the third PMOS transistor P2 is connected to the power supply VDD, and forms a current branch with the third NMOS transistor N2.
The bias circuit is also characterized in that the ratio of the width to length ratios of the first PMOS tube P0, the second PMOS tube P1 and the third PMOS tube P2 is 1:1: 1; the ratio of the width to length ratios of the first NMOS transistor N0, the second NMOS transistor N1 and the third NMOS transistor N2 is 1: m: 1.
The third PMOS transistor P2 and the third NMOS transistor N2 form a clamp circuit, so that the potentials of the node a and the node B are equal, and the current of the first PMOS transistor P0 is equal to the current of the second PMOS transistor P1, thereby realizing a bias current independent of the supply voltage.
The substrate of the second NMOS transistor N1 is connected to the source electrode to eliminate the body effect.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is based on the traditional bias circuit, introduces the clamping circuit, enables the drain electrode-source electrode voltage of the current mirror generating the bias current branch circuit to be equal, and greatly reduces the influence of the power supply voltage change on the magnitude of the bias current, thereby overcoming the problem of power supply dependency of the bias current caused by the channel length modulation effect under the condition that the power supply voltage change range of the traditional bias circuit is larger,
2. the bias circuit has a large working power supply voltage range and a low lowest working power supply voltage; the method is suitable for an analog or mixed signal integrated circuit with low minimum power supply voltage and wide variation range, effectively solves the problem that the bias current in the bias circuit varies with the power supply voltage, and reduces the variation of the system quiescent current with the power supply voltage.
Drawings
FIG. 1 is a schematic diagram of a conventional bias circuit;
FIG. 2 is a schematic diagram of a bias circuit proposed by the present invention;
fig. 3 is a simplified circuit diagram of fig. 2.
Detailed Description
In this embodiment, as shown in fig. 2, a bias circuit independent of a power supply voltage includes:
three PMOS tubes: a first PMOS transistor P0, a second PMOS transistor P1 and a third PMOS transistor P2; three NMOS tubes: a first NMOS transistor N0, a second NMOS transistor N1, a third NMOS transistor N2 and a resistor R0;
the source electrode of the first NMOS transistor N0 is grounded; the drain electrode of the first NMOS transistor N0, the grid electrode and the drain electrode of the first PMOS transistor P0, and the grid electrode of the second PMOS transistor P1 are connected to the point A;
the source electrode of the first PMOS transistor P0 and the source electrode of the second PMOS transistor P1 are both connected to a power supply VDD; the first PMOS tube P0 is connected into a diode structure and forms a current mirror with the second PMOS tube P1;
the source electrode of the third NMOS transistor N2 is grounded, the grid electrode and the drain electrode of the third NMOS transistor N2, the grid electrode of the first NMOS transistor N0, the grid electrode of the second NMOS transistor N1 and the drain electrode of the third PMOS transistor P2 are connected to a node C; and the substrate of the second NMOS transistor N1 is connected to the source to eliminate the body effect. The third NMOS transistor N2 is connected as a diode structure and forms a current mirror with the first NMOS transistor N0;
the source electrode of the second NMOS transistor N1 is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the ground potential; the drain electrode of the second NMOS transistor N1, the drain electrode of the second PMOS transistor P1 and the gate electrode of the third PMOS transistor P2 are all connected to the node B; the source of the third PMOS transistor P2 is connected to the power supply VDD, and forms a current branch with the third NMOS transistor N2.
In specific implementation, the ratio of the width to length ratios of the first PMOS transistor P0, the second PMOS transistor P1 and the third PMOS transistor P2 is 1:1: 1; the ratio of the width to length ratios of the first NMOS transistor N0, the second NMOS transistor N1 and the third NMOS transistor N2 is 1: m: 1. The NMOS current mirror N0 has the same size as N2, the current of the branch of the NMOS transistor N0 is equal to that of the branch of the NMOS transistor N2, and the sizes of the PMOS transistors P0 and P2 are equal, so that the grid potentials of the PMOS transistors P0 and P2 are equal; the third PMOS tube P2 and the third NMOS tube N2 form a clamping circuit, so that the potentials of a node A and a node B are equal, the current flowing through the first PMOS tube P0 is equal to the current flowing through the second PMOS tube P1, the channel length modulation effect of the PMOS tubes P0 and P1 is eliminated, the dependence of the bias current Iout on the power supply voltage is reduced to a great extent, and the bias circuit generates the bias current irrelevant to the power supply voltage.
Quantitatively, a slight change Δ V in the supply voltage is obtained from the simplified circuit diagram of the bias circuit shown in FIG. 3, taking into account the channel length modulation effectDDThe resulting change in output current is:
as can be seen from expressions (2) and (3), under the condition that the power supply variation is the same, the variation of the bias current output by the bias circuit is much smaller than that of the conventional bias circuit.
The minimum operating voltage of the biasing circuit is VGS + VDS.
The bias circuit eliminates the influence of channel length modulation effect on the output bias current to a great extent, the output bias current is basically unchanged when the power supply voltage range is large, and the bias circuit is suitable for analog or mixed signal integrated circuits with low lowest power supply voltage and large variation range.
Claims (4)
1. A supply voltage independent bias circuit, comprising:
three PMOS tubes: a first PMOS transistor P0, a second PMOS transistor P1 and a third PMOS transistor P2; three NMOS tubes: a first NMOS transistor N0, a second NMOS transistor N1, a third NMOS transistor N2 and a resistor R0;
the source electrode of the first NMOS transistor N0 is grounded; the drain electrode of the first NMOS transistor N0, the grid electrode and the drain electrode of the first PMOS transistor P0, and the grid electrode of the second PMOS transistor P1 are connected to the point A;
the source electrode of the first PMOS transistor P0 and the source electrode of the second PMOS transistor P1 are both connected to a power supply VDD; the first PMOS tube P0 is connected into a diode structure and forms a current mirror with the second PMOS tube P1;
the source electrode of the third NMOS transistor N2 is grounded, the grid electrode and the drain electrode of the third NMOS transistor N2, the grid electrode of the first NMOS transistor N0, the grid electrode of the second NMOS transistor N1 and the drain electrode of the third PMOS transistor P2 are connected to a node C; the third NMOS transistor N2 is connected to form a diode structure, and forms a current mirror with the first NMOS transistor N0;
the source electrode of the second NMOS transistor N1 is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the ground potential; the drain electrode of the second NMOS transistor N1, the drain electrode of the second PMOS transistor P1 and the gate electrode of the third PMOS transistor P2 are all connected to a node B; the source of the third PMOS transistor P2 is connected to the power supply VDD, and forms a current branch with the third NMOS transistor N2.
2. The bias circuit of claim 1, wherein the ratio of the width-to-length ratios of the first PMOS transistor P0, the second PMOS transistor P1, and the third PMOS transistor P2 is 1:1: 1; the ratio of the width to length ratios of the first NMOS transistor N0, the second NMOS transistor N1 and the third NMOS transistor N2 is 1: m: 1.
3. The bias circuit as claimed in claim 1, wherein the third PMOS transistor P2 and the third NMOS transistor N2 constitute a clamp circuit, so that the potentials of the node A and the node B are equal, and the current of the first PMOS transistor P0 and the current of the second PMOS transistor P1 are equal, thereby realizing a bias current independent of the supply voltage.
4. The bias circuit as claimed in claim 1, wherein the substrate of the second NMOS transistor N1 is connected to the source to eliminate the body effect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010382071.8A CN111522391A (en) | 2020-05-08 | 2020-05-08 | Bias circuit irrelevant to power supply voltage |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010382071.8A CN111522391A (en) | 2020-05-08 | 2020-05-08 | Bias circuit irrelevant to power supply voltage |
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| CN111522391A true CN111522391A (en) | 2020-08-11 |
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| CN202010382071.8A Pending CN111522391A (en) | 2020-05-08 | 2020-05-08 | Bias circuit irrelevant to power supply voltage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115882827A (en) * | 2022-12-29 | 2023-03-31 | 无锡迈尔斯通集成电路有限公司 | Low-temperature coefficient constant delay circuit less influenced by process |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001659A1 (en) * | 2001-06-08 | 2003-01-02 | Stmicroelectronics S.A. | Bias circuit with voltage and temperature stable operating point |
| CN101609344A (en) * | 2009-07-07 | 2009-12-23 | 东南大学 | The CMOS subthreshold high-order temperature compensation bandgap reference circuit |
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| CN106055001A (en) * | 2016-06-08 | 2016-10-26 | 中国电子科技集团公司第五十八研究所 | Improved reference current source circuit |
| CN109240407A (en) * | 2018-09-29 | 2019-01-18 | 北京兆易创新科技股份有限公司 | A kind of a reference source |
-
2020
- 2020-05-08 CN CN202010382071.8A patent/CN111522391A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001659A1 (en) * | 2001-06-08 | 2003-01-02 | Stmicroelectronics S.A. | Bias circuit with voltage and temperature stable operating point |
| CN101609344A (en) * | 2009-07-07 | 2009-12-23 | 东南大学 | The CMOS subthreshold high-order temperature compensation bandgap reference circuit |
| CN104503530A (en) * | 2015-01-09 | 2015-04-08 | 中国科学技术大学 | High-performance high-reliability reference voltage source of low-voltage complementary metal oxide semiconductor (CMOS) |
| CN106055001A (en) * | 2016-06-08 | 2016-10-26 | 中国电子科技集团公司第五十八研究所 | Improved reference current source circuit |
| CN109240407A (en) * | 2018-09-29 | 2019-01-18 | 北京兆易创新科技股份有限公司 | A kind of a reference source |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115882827A (en) * | 2022-12-29 | 2023-03-31 | 无锡迈尔斯通集成电路有限公司 | Low-temperature coefficient constant delay circuit less influenced by process |
| CN115882827B (en) * | 2022-12-29 | 2024-02-13 | 无锡迈尔斯通集成电路有限公司 | Low-temperature coefficient constant delay circuit with small process influence |
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Application publication date: 20200811 |
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