CN115857606A - Low-power-consumption reference voltage source - Google Patents

Abstract

The invention discloses a low-power consumption reference voltage source, which comprises: the bias compensation circuit comprises an N-stage PMOS tube and is used for providing bias current for a reference voltage source; the reference voltage output circuit comprises an N-stage self-cascode structure and is used for generating and outputting a reference voltage; the N output ends of the bias compensation circuit are correspondingly connected with the N input ends of the reference voltage output circuit; n is an integer greater than or equal to 2. The reference voltage source with the full CMOS structure is adopted, only lower power supply voltage and smaller bias current are needed, meanwhile, no resistor device is needed, the occupied chip area is greatly reduced, the chip utilization rate is improved, the same type of MOS transistors are adopted in the reference voltage output circuit, the N-stage self-cascode structure stacking is utilized, the power consumption of the reference voltage source is reduced, and meanwhile the output reference voltage is adjustable.

Description

Low-power-consumption reference voltage source

Technical Field

The invention relates to the field of reference voltage source design, in particular to a low-power-consumption reference voltage source.

Background

With the rapid development of the internet of things and portable devices, the miniaturization, portability and low power consumption of the devices have become the current development direction. The reference source circuit is used as an important basic module of an analog integrated circuit, can provide reference voltage insensitive to power supply voltage, temperature and process variation, and is widely applied to circuits such as an analog-to-digital converter, a digital-to-analog converter, a phase-locked loop, a dynamic memory and the like. These circuits are the basis of various chips and electronic devices, and therefore, in order to meet the requirements of various electronic products on power consumption and size, the development of a voltage reference source with ultra-low power consumption and small size is urgently needed.

The conventional bandgap reference source can output a reference voltage which has small variation with a power supply voltage and temperature, but a bipolar transistor device is required, so that the minimum power supply voltage and bias current for voltage reference operation are limited, and power consumption is difficult to reduce. Meanwhile, the bandgap reference requires a resistor device to adjust the temperature characteristic of the reference voltage, and the required resistance is large under the condition of low current, which results in large chip area occupation.

The research on the full CMOS reference voltage source at present mainly focuses on two directions of proposing different generation modes of the reference voltage and improving the performance. The common generation mode of the reference voltage is a self-cascode structure composed of two NMOS transistors, which uses the threshold difference of the two NMOS transistors to form a negative temperature coefficient voltage, V _T A positive temperature coefficient voltage is generated. But there are two problems with the current two transistor threshold difference configuration of the self-cascode structure.

One is that if two different types of transistors are used to construct the threshold difference (one is a high threshold transistor and the other is a low threshold transistor), the two types of transistors may be located at different process corners due to different doping processes, which may make them more sensitive to process variations. At the same time, this structure can theoretically only produce a fixed output voltage.

If the same type of transistor is used to form the threshold difference by using the short channel length effect, although the process deviation generated by using different types of transistors can be eliminated, the reference voltage value generated by the scheme is very small (lower than 100 mV), which greatly limits the application scene of the reference voltage source.

Disclosure of Invention

In order to solve the problems, the invention provides a low-power-consumption reference voltage source which is adjustable in output reference voltage and is realized by adopting the same type of MOS transistor and utilizing the body effect, the short channel length effect and the stacking of a self-cascode structure. The specific technical scheme of the invention is as follows:

a low power consumption reference voltage source, the reference voltage source comprising: the bias compensation circuit comprises an N-stage PMOS tube and is used for providing bias current for a reference voltage source; the reference voltage output circuit comprises an N-stage self-cascode structure and is used for generating and outputting a reference voltage; the N output ends of the bias compensation circuit are correspondingly connected with the N input ends of the reference voltage output circuit; n is an integer greater than or equal to 2.

Compared with the traditional band-gap reference source, adopt the reference voltage source of full CMOS structure among this technical scheme, utilize the MOS pipe of work in sub-threshold region to produce reference voltage, the reference voltage source of this kind of structure only needs lower mains voltage and less bias current, simultaneously, this kind of reference voltage source who adopts full CMOS structure need not to set up resistance device, reduce by a wide margin and occupy the chip area, improve the chip utilization ratio, adopt the MOS transistor of same type among the reference voltage output circuit, utilize piling up of N level self-cascode structure, realize output reference voltage adjustable when reducing the reference voltage source consumption.

Furthermore, the drain electrode of each of the N-stage PMOS transistors of the bias compensation circuit is used as an output end of the bias compensation circuit and is connected with a corresponding input end of the reference voltage output circuit. According to the technical scheme, the drain electrode of each PMOS tube in the N-stage PMOS tubes is used as the output end of the bias compensation circuit and is connected with one corresponding input end of the reference voltage output circuit, so that the bias compensation circuit can provide bias compensation current.

Furthermore, the source electrode of each stage of PMOS tube in the bias compensation circuit is connected with the grid electrode of the same stage of PMOS tube. Compared with the prior art, in the technical scheme, the source electrode of each level of PMOS tube in the bias compensation circuit is connected with the grid electrode of the same level of PMOS tube, so that the grid-source voltage V of the PMOS tube _GS And the output voltage is not less than 0, so that the bias current is provided for the reference voltage source, the power consumption of the voltage reference is reduced, and the low-power-consumption output of the whole reference voltage source is realized.

Furthermore, the reference voltage source further comprises a power supply, the substrate of each stage of PMOS tube in the bias compensation circuit is connected with the power supply, and the connection point of the source electrode of each stage of PMOS tube and the grid electrode of the same stage of PMOS tube is connected with the power supply. Compared with the prior art, the N-level PMOS tubes in the bias compensation circuit are respectively connected with the power supply in the technical scheme, so that no zero current branch circuit exists in the bias compensation circuit when the power supply is powered on, a starting circuit is not required to be designed for the reference voltage source, the circuit structure of the whole reference voltage source is simpler, and the occupied chip area can be effectively reduced.

Furthermore, each stage of the self-cascode structure comprises a No. 1 NMOS transistor and a No. 2 NMOS transistor; and the drain electrode of the NMOS transistor No. 2 of each stage of the self-cascode structure is used as one input end of the reference voltage output circuit and is connected with one corresponding output end of the bias compensation circuit. According to the technical scheme, the two MOS tubes of the same type are adopted to form a primary self-cascode structure, the self-cascode structure provides a positive temperature coefficient and a negative temperature coefficient, so that the reference voltage source is less influenced by temperature, a threshold difference is formed by utilizing the short channel length effect of the two MOS tubes, and the problem that the reference voltage output by the MOS tubes of the same type is limited at present is solved by superposing the N-stage self-cascode structures.

Furthermore, the grid electrode of the No. 1 NMOS tube in each stage of self-cascode structure is connected with the grid electrode of the No. 2 NMOS tube; the drain electrode of the No. 1 NMOS tube in each stage of self-cascode structure is connected with the source electrode of the No. 2 NMOS tube; and the substrate of the No. 1 NMOS tube in each stage of the self-cascode structure is connected with the ground wire. In the technical scheme, the grid electrodes of two NMOS tubes in each stage of self-cascode structure are connected to realize a common-gate structure.

Further, the grid electrode of the NMOS tube No. 2 in each stage of self-cascode structure is connected with the drain electrode of the NMOS tube No. 2 in the same stage of self-cascode structure.

Furthermore, a connection point of the drain of the NMOS transistor No. 1 of the nth stage self-cascode structure and the source of the NMOS transistor No. 2 of the nth stage self-cascode structure serves as an output end of the reference voltage output circuit, and is used for outputting a reference voltage. In the technical scheme, the connection point of the drain electrode of the NMOS tube No. 1 of the last stage and the source electrode of the NMOS tube No. 2 is used as the output end of the reference voltage output circuit to output the reference voltage regulated by the N-stage self-cascode structure, the structure regulates the reference voltage output by the reference voltage source by regulating the stage number of the N-stage self-cascode structure, and meanwhile, the structure eliminates the influence of the body effect by stacking the N-stage self-cascode structure.

Furthermore, the connecting point of the drain electrode of the No. 1 NMOS tube of the k-1 level self-cascode structure and the source electrode of the No. 2 NMOS tube of the k-1 level self-cascode structure is connected with the source electrode of the No. 1 NMOS tube of the k level self-cascode structure; wherein k is an integer greater than or equal to 2 and less than or equal to N. According to the technical scheme, the connection point of the drain electrode of the NMOS tube No. 1 of the (k-1) -th self-cascode structure and the source electrode of the NMOS tube No. 2 of the (k-1) -th self-cascode structure is connected with the source electrode of the NMOS tube No. 1 of the (k-1) -th self-cascode structure, so that the N-level self-cascode structures are communicated.

Further, the source electrode of the No. 1 NMOS tube of the 1 st stage self-cascode structure is connected with the ground wire.

Furthermore, the substrate of the No. 2 NMOS tube of each stage of the self-cascode structure is connected with the output end of the reference voltage output circuit. Compared with the prior art, the reference voltage source in the technical scheme adopts a feedback connection mode, the output feedback of the reference voltage output circuit is connected to the body potential of the NMOS transistor No. 2 of each stage of the self-cascode structure, and the output reference voltage value is convenient to calculate.

Drawings

Fig. 1 is a schematic circuit diagram of a low-power reference voltage source according to an embodiment of the invention.

Fig. 2 is a schematic circuit diagram of a reference voltage source with N equal to 2 according to an embodiment of the invention.

Fig. 3 is a schematic circuit diagram of a reference voltage source with N equal to 3 according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described and illustrated with reference to the accompanying drawings and embodiments. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention. It should be understood that various changes in design, manufacture, or manufacture to the disclosed embodiments will be apparent to those skilled in the art, and that such changes in the disclosed embodiments are merely routine and should not be construed as providing the required level of technical equivalents.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "including," "comprising," "having," and any variations thereof herein, is intended to cover non-exclusive inclusions, such as: a process, method, system product or apparatus that comprises a list of steps or modules is not limited to the listed steps or elements but may include additional steps or elements not listed or inherent to such process, method, product or apparatus. Reference throughout this application to the terms "first," "second," "third," and the like are only used for distinguishing between similar references and not intended to imply a particular ordering for the objects.

In one embodiment of the present invention, a low power consumption reference voltage source is provided, which includes: an offset compensation circuit and a reference voltage output circuit. Wherein, as shown in fig. 1, the bias compensation circuit comprises N-stage PMOS transistors (M in fig. 1) _P1 To M _PN ) And the reference voltage output circuit is used for providing bias current for the low-power-consumption reference voltage output circuit, and comprises an N-stage self-cascode structure and is used for generating and outputting reference voltage based on the bias current provided by the bias compensation circuit. Specifically, the N-stage PMOS transistors of the bias compensation circuit are respectively connected with the N-stage self-cascode structures of the reference voltage output circuit in a one-to-one correspondence manner, so that the bias compensation circuit provides a bias current for the reference voltage output circuit. The one-to-one corresponding connection means that a first-stage PMOS tube is connected with a first-stage self-cascode structure, a second-stage PMOS tube is connected with a second-stage self-cascode structure, and the rest can be done in the same way, and the Nth stageThe PMOS tube is connected with the Nth-stage self-cascode structure; wherein N is an integer greater than or equal to 2.

And the drain electrode of each PMOS tube in the N-stage PMOS tubes of the bias compensation circuit is used as an output end of the bias compensation circuit and is connected with a corresponding input end of the reference voltage output circuit.

The source electrode of each stage of PMOS tube in the bias compensation circuit is connected with the grid electrode of the same stage of PMOS tube, and understandably, the source electrode on the same PMOS tube is connected with the grid electrode. In this embodiment, the source and the gate of each level of PMOS transistor in the bias compensation circuit are connected, so that the gate-source voltage V of each level of PMOS transistor _GS And the offset compensation circuit is equal to 0, so that the offset compensation circuit provides offset current for the reference voltage output circuit, the power consumption of the voltage reference is reduced, and the low-power-consumption output of the whole reference voltage source is realized.

The low-power reference voltage source further comprises a power supply V _DD The substrate of each stage of PMOS tube in the bias compensation circuit is connected with the power supply V _DD The PMOS transistors are connected, and meanwhile, the connection point of the source electrode of each level of PMOS transistor and the grid electrode of the same level of PMOS transistor is connected with the power supply V _DD Are connected. Through connecting each level of PMOS pipe with the power, make zero current branch road does not exist in the offset compensation circuit, thereby compare in prior art based on the reference voltage source of this kind of structure, need not to design starting circuit and power up with auxiliary power, realize simplifying reference voltage source overall circuit structure, can effectively reduce reference voltage source and occupy the chip area, reduce chip cost.

In the N-stage self-cascode structure in the reference voltage output circuit, each stage of self-cascode structure includes a No. 1 NMOS transistor and a No. 2 NMOS transistor (for example, M in fig. 1) ₁₁ To M _N1 For each stage of NMOS transistor No. 1 of self-cascode structure, M ₁₂ To M _N2 For each grade of NMOS tube No. 2 of the self-cascode structure), the drain electrode of the NMOS tube No. 2 of the self-cascode structure at each grade is taken as an input end of the reference voltage output circuit, so that N drain electrodes of the PMOS tube No. N grades of the bias compensation circuit and the NMOS tube No. 2 of the self-cascode structure at N grades are enabled to be respectively connected with the output end of the reference voltage output circuitThe N drain electrodes of the offset compensation circuit are connected in a one-to-one correspondence to realize that the output end of the offset compensation circuit is correspondingly connected with the input end of the reference voltage output circuit. It should be noted that the first stage PMOS transistor M _P1 Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M of a first-stage self-cascode structure ₁₂ Is connected with the drain electrode of the second-stage PMOS tube M _P2 Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M with a second-stage self-cascode structure ₂₂ The drain electrodes of the PMOS tubes are connected in the same way, and the Nth-stage PMOS tube M is obtained by analogy _PN Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M with an Nth stage self-cascode structure _N2 Is connected to the drain of (c). In the embodiment, two MOS tubes of the same type form a primary self-cascode structure, a positive temperature coefficient and a negative temperature coefficient are provided for a reference voltage source through the self-cascode structure, so that the reference voltage source is less influenced by the environmental temperature, a threshold difference is formed by utilizing the short channel length effect of the two NMOS tubes, and the problem that the reference voltage output by the MOS tubes of the same type is limited at present is solved through the superposition of the N-stage self-cascode structure.

It should be noted that the reference voltage output circuit part in FIG. 1 has a specific value of, for example, M _N1 Wherein "M" represents MOS transistor, "N" represents the stage number of the self-cascode structure, "1" represents that the MOS transistor is the NMOS transistor No. 1 of the self-cascode structure of the first stage, and according to the analysis, M is understandable _N2 The NMOS transistor is a No. 2 NMOS transistor with an Nth-stage self-cascode structure; such as: m is a group of _PN Wherein, M represents MOS tube, P represents PMOS tube, N represents the series of PMOS tube; such as: "I" represents the bias current of each branch, and "V _DD "represents the supply voltage" V _REFN "represents the reference voltage output by the reference voltage source, and" GND "represents the ground.

In the reference voltage output circuit, each level of grid electrode of the NMOS tube No. 1 from the cascode structure is connected with the grid electrode of the NMOS tube No. 2 from the cascode structure at the same level, each level of drain electrode of the NMOS tube No. 1 from the cascode structure is connected with the source electrode of the NMOS tube No. 2 from the cascode structure at the same level, and each level of substrate of the NMOS tube No. 1 from the cascode structure is connected with the ground wire GND. In this embodiment, the gates and gates of the NMOS transistor No. 1 and the NMOS transistor No. 2 of the same-stage self-cascode structure are connected to form a cascode structure.

The grid electrode of the NMOS tube No. 2 in each stage of the self-cascode structure in the reference voltage output circuit is connected with the drain electrode of the NMOS tube No. 2 in the same stage of the self-cascode structure, understandably, the grid electrode and the drain electrode of the NMOS tube No. 2 in each stage of the self-cascode structure are connected, and the drain electrode of the NMOS tube No. 2 in each stage of the self-cascode structure is used as the input end of the self-cascode structure and is connected with the drain electrode of the PMOS tube of the bias compensation circuit.

As shown in fig. 1, the N-th stage of NMOS transistor 1 with self-cascode structure in the reference voltage output circuit is connected to a power supply _N1 Drain and N-th stage self-cascode structure NMOS transistor M No. 2 _N2 The source of the reference voltage source is used as the output end of the reference voltage output circuit and is used for outputting the reference voltage of the reference voltage source with low power consumption. In this embodiment, the N-th self-cascode NMOS transistor No. 1M _N1 Drain electrode of (1) and N-th stage self-cascode structure No. 2 NMOS tube M _N2 The connection point of the source electrode is used as the output end of the reference voltage output circuit to output the reference voltage regulated by the N-stage self-cascode structure, meanwhile, the reference voltage source with the structure can regulate the reference voltage output by the reference voltage source by regulating the stage number N of the self-cascode structure, and the influence of the body effect can be eliminated by stacking the N-stage self-cascode structure.

Specifically, a connection point of a drain of a No. 1 NMOS tube of the k-1 stage self-cascode structure and a source of a No. 2 NMOS tube of the k-1 stage self-cascode structure in the reference voltage output circuit is connected with a source of the No. 1 NMOS tube of the k stage self-cascode structure, where k is an integer greater than or equal to 2 and less than or equal to N. The connection point of the drain electrode of the NMOS tube No. 1 of the current-stage self-cascode structure and the source electrode of the NMOS tube No. 2 of the current-stage self-cascode structure is connected with the source electrode of the NMOS tube No. 1 of the next-stage self-cascode structure, and the k-stage self-cascode structures are communicated. It should be noted that the source of the NMOS transistor No. 1 of the 1 st-stage self-cascode structure in the reference voltage output circuit is connected to the ground GND.

Specifically, the substrate of the NMOS transistor No. 2 of each stage of the reference voltage output circuit is connected to the output terminal of the reference voltage output circuit, and it can be understood that the substrate of the NMOS transistor No. 2 of each stage of the reference voltage output circuit is connected to the connection point of the drain electrode of the NMOS transistor No. 1 of the self-cascode structure and the source electrode of the NMOS transistor No. 2 of the self-cascode structure, which becomes a feedback connection mode, and the output voltage output by the reference voltage output circuit is fed back and transmitted to the bulk potential of the NMOS transistor No. 2 of each stage of the self-cascode structure, so as to calculate the reference voltage value output after the bulk effect is eliminated.

When the number of N stages is smaller, the power consumption of the reference voltage source is smaller, and when the number of N stages is larger, the power consumption of the reference voltage source is larger, but the output reference voltage is also larger. Therefore, the stacking order number N of the self-cascode structure of the reference voltage source can be adaptively adjusted according to actual requirements, so as to achieve the effect of being most suitable for the current requirements.

Based on the above embodiments, as a preferred embodiment of the present invention, a low power consumption reference voltage source with N equal to 2 is provided, as shown in fig. 2, the low power consumption reference voltage source includes a bias compensation circuit and a reference voltage output circuit, the bias compensation circuit includes a 2-stage PMOS transistor (M in fig. 2) _P1 And M _P2 ) For providing 2 branches of bias current (I in fig. 3) to the reference voltage output circuit _a ) (ii) a The reference voltage compensation circuit comprises a 2-stage self-cascode structure and is used for generating and outputting a reference voltage based on the bias current provided by the bias compensation circuit.

Specifically, the source electrode of each stage of PMOS transistor in the bias compensation circuit is connected to the gate electrode of the same stage of PMOS transistor, the substrate of each stage of PMOS transistor is connected to the power supply, and 2 drain electrodes of 2 stages of PMOS transistors serve as 2 output terminals of the bias compensation circuit, and are configured to provide bias currents of 2 branches for the reference voltage output circuit.

In the 2-stage self-cascode structure of the reference voltage output circuit, each stage of self-cascode structure comprises a No. 1 NMOS tube and a No. 2 NMOS tube, as shown in FIG. 2, the first stage of self-cascode structure comprises a No. 1 NMOS tube M ₁₁ And NMOS tube No. 2M ₁₂ The second stage self-cascode structure comprises a No. 1 NMOS tube M ₂₁ And NMOS tube No. 2M ₂₂ 。

It should be noted that the reference voltage output circuit part in FIG. 2 has a specific value of, for example, M ₂₁ Wherein "M" represents a MOS transistor, "2" represents the number of stages of the self-cascode structure, and "1" represents that the MOS transistor is the NMOS transistor No. 1 of the self-cascode structure, and according to the analysis, M is understandable ₁₂ The NMOS transistor is a No. 2 NMOS transistor with a 1 st-stage self-cascode structure; such as: m is a group of _P1 Wherein, M represents MOS tube, P represents PMOS tube, 1 represents the series of PMOS tube; such as: "I _a "represents the bias current of each branch," V _DD "represents the supply voltage" V _REF2 "represents the reference voltage outputted from the reference voltage source," GND "represents the ground.

Specifically, the first-stage self-cascode NMOS transistor No. 1M ₁₁ The grid of the NMOS transistor M is connected with a No. 2 NMOS transistor M of a first-stage self-cascode structure ₁₂ The grid electrode of the NMOS tube No. 1 of the first-stage self-cascode structure is connected with the ground wire GND, the grid electrode of the NMOS tube No. 2 of the first-stage self-cascode structure is connected with the drain electrode thereof, and the NMOS tube No. 1 of the first-stage self-cascode structure is connected with the drain electrode thereof ₁₁ Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M of a first-stage self-cascode structure ₁₂ The first stage is from the NMOS tube M of the cascode structure No. 1 ₁₁ Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M of a first-stage self-cascode structure ₁₂ The connecting point of the source electrode of the NMOS transistor (1N-channel metal oxide semiconductor) is connected with the NMOS transistor M of the second-stage self-cascode structure ₂₁ The source electrodes of the NMOS transistors M are connected, and the second stage is a No. 1 NMOS transistor M with a cascode structure ₂₁ Gate of (2) is self-cascode with the second stageNMOS transistor M No. 2 with grid structure ₂₂ The grid electrodes of the NMOS transistors are connected, and the second stage is from the NMOS transistor M of No. 1 of the cascode structure ₂₁ The substrate of the transistor is connected with a ground wire GND, and a second-stage self-cascode structure No. 2 NMOS transistor M ₂₂ The grid of the NMOS transistor is connected with the drain of the NMOS transistor, and the second stage is a No. 1 NMOS transistor M with a self-cascode structure ₂₁ Drain of the NMOS transistor M and a No. 2 NMOS transistor M of a second-stage self-cascode structure ₂₂ The source electrodes of the NMOS transistors are connected, and a No. 1 NMOS transistor M with a second-stage self-cascode structure is connected ₂₁ Drain of the NMOS transistor M and a No. 2 NMOS transistor M of a second-stage self-cascode structure ₂₂ As an output terminal of the reference voltage output circuit, for outputting a reference voltage V _REF2 。

And the drain electrodes of 2 NMOS transistors No. 2 in the 2-stage self-cascode structure are used as 2 input ends of the reference voltage output circuit and are used for being respectively connected with 2 output ends of the bias compensation circuit in a one-to-one correspondence manner so as to receive the compensation circuit provided by the bias compensation circuit. Specifically, the NMOS transistor M No. 2 of the first-stage self-cascode structure ₁₂ Drain electrode of and first-stage PMOS transistor M _P1 Drain electrode of the NMOS transistor is connected, and a second stage is from a No. 2 NMOS tube M of a cascode structure ₂₂ Drain electrode of and second-stage PMOS transistor M _P2 Is connected to the drain of (c).

It should be noted that, the substrates of 2 NMOS transistors in the 2-stage self-cascode structure and the 1 NMOS transistor M in the second-stage self-cascode structure ₂₁ Drain of (1) and second stage self-cascode structure of NMOS transistor M No. 2 ₂₂ The reference voltage output circuit feeds back the reference voltage output by the reference voltage output circuit to the body potential of the NMOS transistor No. 2 of each stage of the self-cascode structure, so that the reference voltage value output by the reference voltage source after the body effect is eliminated can be calculated.

Based on the above embodiments, as a preferred embodiment of the present invention, a low power consumption reference voltage source with N equal to 3 is provided, as shown in fig. 3, the low power consumption reference voltage source includes a bias compensation circuit and a reference voltage output circuit, the bias compensation circuit includes 3 stages of PMOS transistors (M in fig. 3) _P1 、M _P2 And M _P3 ) For being the referenceThe voltage output circuit provides bias current of 3 branches (I in FIG. 3) _b 、2I _b And 3I _b ) (ii) a The reference voltage compensation circuit comprises a 3-stage self-cascode structure and is used for generating and outputting a reference voltage based on a bias current provided by the bias compensation circuit.

Specifically, the source of each PMOS transistor in the bias compensation circuit is connected to the gate of the same PMOS transistor, the substrate of each PMOS transistor is connected to the power supply, and 3 drains of 3 PMOS transistors serve as 3 outputs of the bias compensation circuit, so as to provide bias currents of 3 branches for the reference voltage output circuit.

In the 3-stage self-cascode structure of the reference voltage output circuit, each stage of the self-cascode structure comprises a No. 1 NMOS tube and a No. 2 NMOS tube, as shown in FIG. 3, the first stage of the self-cascode structure comprises a No. 1 NMOS tube M ₁₁ And NMOS transistor No. 2M ₁₂ The second stage self-cascode structure comprises a No. 1 NMOS tube M ₂₁ And NMOS tube No. 2M ₂₂ The third-stage self-cascode structure comprises a No. 1 NMOS tube M ₃₁ And NMOS transistor No. 2M ₃₂ 。

Specifically, the first-stage self-cascode NMOS transistor M No. 1 ₁₁ The grid of the NMOS transistor M and the NMOS transistor M of the first stage self-cascode structure No. 2 ₁₂ The grid electrode of the NMOS tube No. 1 of the first-stage self-cascode structure is connected with the ground wire GND, the grid electrode of the NMOS tube No. 2 of the first-stage self-cascode structure is connected with the drain electrode of the NMOS tube No. 1 of the first-stage self-cascode structure, and the NMOS tube No. 1 of the first-stage self-cascode structure is connected with the ground wire GND ₁₁ Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M of a first-stage self-cascode structure ₁₂ The source electrodes of the NMOS transistors are connected, and a first-stage self-cascode structure NMOS transistor M No. 1 ₁₁ Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M of a first-stage self-cascode structure ₁₂ The connecting point of the source electrode of the NMOS transistor (1N-channel metal oxide semiconductor) is connected with the NMOS transistor M of the second-stage self-cascode structure ₂₁ The source electrodes of the NMOS transistors M are connected, and the second stage is a No. 1 NMOS transistor M with a cascode structure ₂₁ The grid of the NMOS transistor M and the NMOS transistor M of the second stage self-cascode structure No. 2 ₂₂ The grid electrodes of the NMOS transistors are connected, and a No. 1 NMOS transistor M with a second-stage self-cascode structure ₂₁ Is connected with the ground line GNDAnd a No. 2 NMOS transistor M with a second-stage self-cascode structure ₂₂ The grid of the NMOS transistor is connected with the drain of the NMOS transistor, and the second stage is a No. 1 NMOS transistor M with a self-cascode structure ₂₁ Drain electrode of the NMOS transistor M and a No. 2 NMOS transistor M with a second-stage self-cascode structure ₂₂ The source electrodes of the NMOS transistors are connected, and a second stage is an NMOS transistor M with a No. 1 self-cascode structure ₂₁ Drain of the NMOS transistor M and a No. 2 NMOS transistor M of a second-stage self-cascode structure ₂₂ The connecting point of the source electrode of the NMOS transistor is connected with the No. 2 NMOS transistor M of the third-stage self-cascode structure ₃₂ The source electrodes of the NMOS transistors are connected, and a No. 1 NMOS transistor M with a third-stage self-cascode structure ₃₁ The grid of the NMOS transistor M and the NMOS transistor M of the third-stage self-cascode structure No. 2 ₃₂ The grid electrodes of the NMOS transistors are connected, and the third stage is a No. 1 NMOS transistor M with a cascode structure ₃₁ The substrate of the transistor is connected with a ground wire GND, and the third-stage NMOS transistor M with a cascode structure is No. 2 ₃₂ The grid of the NMOS transistor is connected with the drain of the NMOS transistor, and the third stage is a No. 1 NMOS transistor M with a cascode structure ₃₁ Drain electrode of NMOS transistor M and NMOS transistor M of third-stage self-cascode structure No. 2 ₃₂ Is connected to the source of the transistor.

And the drain electrodes of 3 No. 2 NMOS tubes in the 3-stage self-cascode structure are used as 3 input ends of the reference voltage output circuit and are used for being respectively connected with 3 output ends of the bias compensation circuit in a one-to-one correspondence manner so as to receive the compensation circuit provided by the bias compensation circuit. Specifically, the first stage is from NMOS pipe M of No. 2 of cascode structure ₁₂ Drain electrode of and first-stage PMOS transistor M _P1 The drain electrodes of the NMOS transistors are connected, and the second stage is a No. 2 NMOS transistor M with a cascode structure ₂₂ Drain electrode of and second-stage PMOS transistor M _P2 Drain electrodes of the NMOS transistors are connected, and a No. 2 NMOS transistor M with a third-stage self-cascode structure ₃₂ Drain electrode of and third stage PMOS transistor M _P3 Is connected to the drain of the transistor.

No. 1 NMOS transistor M of third-stage self-cascode structure ₃₁ Drain electrode of NMOS transistor M and NMOS transistor M of third-stage self-cascode structure No. 2 ₃₂ As an output terminal of the reference voltage output circuit to output a reference voltage V _REF3 。

It should be noted that, the substrates of 3 NMOS transistors No. 2 in the 3-stage self-cascode structure and the third-stage self-cascode structureNo. 1 NMOS tube M ₃₁ Drain electrode of (1) and NMOS transistor M of No. 2 with third-stage self-cascode structure ₃₂ The reference voltage output by the reference voltage output circuit is fed back to the body potential of the NMOS tube No. 2 of each stage of the self-cascode structure, so that the reference voltage value output by the reference voltage source after the body effect is eliminated can be calculated.

Based on the above embodiment, the reference voltage source provided by the invention is based on the stacking of the N-stage self-cascode structure, and the structure that the output reference voltage feeds back the potential of the connecting body is adopted, so that the reference voltage source with adjustable output reference voltage, little change due to temperature influence and ultra-low power consumption is realized by utilizing the body effect and the short channel effect.

Obviously, the above-mentioned embodiments are only a part of embodiments of the present invention, not all embodiments, and the technical solutions of the embodiments may be combined with each other. In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In the embodiments provided in the present invention, it should be understood that the disclosed technical contents can be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the circuit may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (11)

1. A low power consumption reference voltage source, comprising:

the bias compensation circuit comprises an N-stage PMOS tube and is used for providing bias current for the reference voltage output circuit;

the reference voltage output circuit comprises an N-stage self-cascode structure and is used for generating and outputting a reference voltage;

the N-stage PMOS tubes of the bias compensation circuit are connected with the N-stage self-cascode structures of the reference voltage output circuit in a one-to-one correspondence manner; n is an integer greater than or equal to 2.

2. The low power consumption reference voltage source according to claim 1, wherein the drain of each of the N stages of PMOS transistors of the bias compensation circuit is connected as an output terminal of the bias compensation circuit to a corresponding input terminal of the reference voltage output circuit.

3. The low power consumption reference voltage source according to claim 2, wherein the source of each stage of PMOS transistor in the bias compensation circuit is connected to the gate of the same stage of PMOS transistor.

4. The low power consumption reference voltage source according to claim 3, wherein the reference voltage source further comprises a power supply, the substrate of each stage of PMOS transistor in the bias compensation circuit is connected to the power supply, and the connection point of the source of each stage of PMOS transistor and the gate of the same stage of PMOS transistor is connected to the power supply.

5. The low-power consumption reference voltage source according to claim 1, wherein each stage of self-cascode structure comprises a NMOS transistor No. 1 and a NMOS transistor No. 2; and the drain electrode of the No. 2 NMOS tube of each stage of self-cascode structure is used as one input end of the reference voltage output circuit and is connected with one corresponding output end of the bias compensation circuit.

6. The low-power consumption reference voltage source according to claim 5, wherein the gate of the NMOS transistor No. 1 in each stage of the self-cascode structure is connected to the gate of the NMOS transistor No. 2; the drain electrode of the No. 1 NMOS tube in each stage of self-cascode structure is connected with the source electrode of the No. 2 NMOS tube; and the substrate of the No. 1 NMOS tube in each stage of self-cascode structure is connected with the ground wire.

7. The low power consumption reference voltage source according to claim 6, wherein the gate of the NMOS transistor No. 2 in each stage of self-cascode structure is connected to the drain of the NMOS transistor No. 2 in the same stage of self-cascode structure.

8. The low-power consumption reference voltage source according to claim 7, wherein a connection point of a drain of the N-th self-cascode NMOS transistor No. 1 and a source of the N-th self-cascode NMOS transistor No. 2 serves as an output terminal of the reference voltage output circuit, and is configured to output a reference voltage.

9. The low-power consumption reference voltage source according to claim 8, wherein a connection point of the drain of the No. 1 NMOS transistor of the k-1 self-cascode structure and the source of the No. 2 NMOS transistor of the k-1 self-cascode structure is connected to the source of the No. 1 NMOS transistor of the k-1 self-cascode structure; wherein k is an integer greater than or equal to 2 and less than or equal to N.

10. The low-power consumption reference voltage source according to claim 9, wherein the source of the NMOS transistor No. 1 of the 1 st stage self-cascode structure is connected to ground.

11. The low power consumption reference voltage source according to claim 8, wherein each stage is connected to the output terminal of the reference voltage output circuit from the substrate of NMOS transistor No. 2 in cascode configuration.

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