CN108427472B - Reference voltage output circuit - Google Patents
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- CN108427472B CN108427472B CN201810225465.5A CN201810225465A CN108427472B CN 108427472 B CN108427472 B CN 108427472B CN 201810225465 A CN201810225465 A CN 201810225465A CN 108427472 B CN108427472 B CN 108427472B
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Abstract
The embodiment of the invention discloses a reference voltage output circuit, which comprises: a conversion circuit, a voltage generation circuit, and an output circuit; the conversion circuit is connected with the reference current source, the conversion circuit is connected with the voltage generation circuit, and the voltage generation circuit is connected with the output circuit; the conversion circuit receives a reference current input by the reference current source, converts the reference current according to a first conversion parameter to obtain a first reference current, and outputs the first reference current to the voltage generation circuit; a voltage generation circuit that divides the voltage based on the first reference current, generates at least a first reference voltage, and outputs the first reference voltage to an output circuit; the output circuit biases the first reference voltage, generates a second reference voltage, and outputs the second reference voltage.
Description
Technical Field
The present invention relates to integrated circuit technology and microelectronic technology, and in particular, to a reference voltage output circuit.
Background
As the feature size of integrated circuits is continuously reduced and the integration level is continuously enhanced, it is increasingly common to integrate multiple voltage-withstanding devices on the same chip, and the demand for integrating multiple voltage sources on the chip is also increasingly enhanced.
In the prior art, the voltage source function on a chip is realized by adopting an operational amplifier, and when the chip needs a plurality of voltage sources, a plurality of operational amplifiers also need to be simultaneously arranged. Fig. 1 is a schematic diagram of a multi-voltage power supply generating circuit in the prior art. Operational amplifiers are circuit units with a relatively high amplification factor. In an actual circuit, a certain functional module is usually formed together with a feedback network. The circuit is complicated due to the existence of the operational amplifier, so that the power consumption of a chip is high, the area of the operational amplifier is large, and excessive chip space is occupied.
Disclosure of Invention
To solve the above technical problem, an embodiment of the present invention provides a reference voltage output circuit.
The technical scheme of the embodiment of the invention is as follows:
the embodiment of the invention provides a reference voltage output circuit, which comprises: a conversion circuit, a voltage generation circuit, and an output circuit; the conversion circuit is connected with a reference current source, the conversion circuit is connected with the voltage generation circuit, and the voltage generation circuit is connected with the output circuit;
after receiving the reference current input by the reference current source, the conversion circuit converts the reference current according to a first conversion parameter to obtain a first reference current, and outputs the first reference current to the voltage generation circuit;
the voltage generation circuit divides the voltage based on the first reference current, generates at least a first reference voltage, and outputs the first reference voltage to the output circuit;
and the output circuit biases the first reference voltage, generates and outputs a second reference voltage.
As one implementation, the conversion circuit includes: a first field effect transistor and a second field effect transistor;
the drain electrode of the first field effect transistor is connected with the reference current source, the drain electrode of the first field effect transistor, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are connected in common, and the drain electrode of the second field effect transistor is connected with the voltage generating circuit;
wherein the first conversion parameter is determined by the first FET channel size parameter and the second FET channel size parameter.
As one implementation, the voltage generation circuit includes: a third field effect transistor and a first reference resistor;
the source electrode of the third field effect transistor is connected with the first end of the first reference resistor, the drain electrode of the third field effect transistor is connected with the conversion circuit, the second end of the first reference resistor is grounded, the drain electrode of the third field effect transistor is connected with the grid electrode of the third field effect transistor, and the drain electrode of the third field effect transistor is connected with the output circuit.
As one implementation, the voltage generation circuit further includes a second reference resistor;
the drain electrode of the third field effect transistor is connected with the second end of the second reference resistor, the first end of the second reference resistor is connected with the conversion circuit, and the first end of the second reference resistor is connected with the output circuit.
Further, the voltage generation circuit further comprises a third reference resistor;
the second end of the third reference resistor is connected with the first end of the second reference resistor, the first end of the third reference resistor is connected with the conversion circuit, and the first end of the third reference resistor is connected with the output circuit.
As an implementation, the voltage generation circuit further includes:
the source electrode of the third field effect transistor is grounded, and the drain electrode of the third field effect transistor is connected with the second end of the first reference resistor; or the like, or, alternatively,
the source electrode of the third field effect transistor is connected with the first end of the third reference resistor, and the drain electrode of the third field effect transistor is connected with the conversion circuit; or the like, or, alternatively,
the source electrode of the third field effect transistor is connected with the first end of the second reference resistor, and the drain electrode of the third field effect transistor is connected with the second end of the third reference resistor;
and shifting the first reference voltage through the third field effect transistor, generating the first reference voltage and outputting the first reference voltage.
As one implementation, the output circuit includes: a fourth field effect transistor and a bias resistor;
the grid electrode of the fourth field effect transistor is connected with the voltage generating circuit, the source electrode of the fourth field effect transistor is connected with the first end of the bias resistor, the second end of the bias resistor is grounded, and the source electrode of the fourth field effect transistor is connected with the first analog load;
and the first reference voltage received by the grid electrode of the fourth field effect transistor is biased through the bias resistor, and the second reference voltage is generated and output.
As one implementation, the output circuit includes: a fifth field effect transistor and a first current mirror circuit; the first current mirror circuit comprises a sixth field effect transistor and a seventh field effect transistor;
the drain electrode of the sixth field effect transistor, the conversion circuit, the grid electrode of the sixth field effect transistor and the grid electrode of the seventh field effect transistor are connected in common, the source electrode of the sixth field effect transistor is grounded, the grid electrode of the fifth field effect transistor is connected with the voltage generation circuit, the source electrode of the fifth field effect transistor is connected with the drain electrode of the seventh field effect transistor, the source electrode of the seventh field effect transistor is grounded, and the source electrode of the fifth field effect transistor is connected with the second analog load;
the first reference voltage received by the grid electrode of the fifth field effect transistor is biased through the first current mirror circuit, and the second reference voltage is generated and output.
As one implementation, the output circuit includes: a transconductance linear circuit and a second current mirror circuit; the transconductance linear circuit comprises a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor and a twelfth field effect transistor; the second current mirror circuit comprises a sixth field effect transistor and an eighth field effect transistor;
the grid electrode of the ninth field effect transistor, the grid electrode of the tenth field effect transistor and the voltage generating circuit are connected in common, the source electrode of the ninth field effect transistor is connected with the source electrode of the eleventh field effect transistor, the source electrode of the tenth field effect transistor is connected with the source electrode of the twelfth field effect transistor, the drain electrode of the eleventh field effect transistor, the grid electrode of the twelfth field effect transistor and the drain electrode of the eighth field effect transistor are connected in common, and the grid electrode of the eighth field effect transistor, the grid electrode of the sixth field effect transistor, the drain electrode of the sixth field effect transistor and the converting circuit are connected in common; the source electrode of the eighth field effect transistor and the drain electrode of the twelfth field effect transistor are both grounded, and the source electrode of the tenth field effect transistor and the source electrode of the twelfth field effect transistor are both connected with a third analog load;
and the transconductance linear circuit is used for adjusting a driving factor of the first reference voltage received by the grid electrode of the ninth field effect transistor and the grid electrode of the tenth field effect transistor, and the second current mirror circuit is used for biasing the adjusted first reference voltage to generate and output the second reference voltage.
As an implementation manner, the adjusting, by the transconductance linear circuit, a driving factor of the first reference voltage commonly received by the gate of the ninth field effect transistor and the gate of the tenth field effect transistor includes:
increasing the driving factor by a source current at a source of the tenth fet;
and reducing the driving factor by sinking current at the source of the twelfth FET.
As an implementation manner, the conversion circuit further includes a thirteenth field effect transistor;
the grid electrode of the thirteenth field effect tube, the grid electrode of the first field effect tube and the drain electrode of the first field effect tube are connected in common, and the drain electrode of the thirteenth field effect tube is connected with the output circuit;
and after receiving the reference current through the grid electrode of the first field effect transistor, converting the reference current according to a second conversion parameter to generate and output a second reference current.
As one implementation, the second conversion parameter is determined by the first fet channel size parameter and the third fet channel size parameter.
The reference voltage output circuit of the embodiment of the invention comprises: a conversion circuit, a voltage generation circuit, and an output circuit; the conversion circuit is connected with the reference current source, the conversion circuit is connected with the voltage generation circuit, and the voltage generation circuit is connected with the output circuit; the conversion circuit receives a reference current input by the reference current source, converts the reference current according to a first conversion parameter to obtain a first reference current, and outputs the first reference current to the voltage generation circuit; a voltage generation circuit that divides the voltage based on the first reference current, generates at least a first reference voltage, and outputs the first reference voltage to an output circuit; the output circuit biases the first reference voltage, generates a second reference voltage, and outputs the second reference voltage. The invention multiplexes one path of reference current through the conversion circuit, generates at least one reference voltage through the voltage generation circuit, and adopts the output circuit to perform bias processing and output the reference voltage, thereby avoiding using a complex operational amplifier structure, realizing an on-chip multi-path voltage source structure, having low power consumption and smaller integral volume, and being more suitable for a plurality of voltage sources.
Drawings
FIG. 1 is a schematic diagram of a multi-voltage power supply generating circuit in the prior art;
fig. 2 is a schematic diagram of a logic structure of a reference voltage output circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a reference voltage output circuit according to a second embodiment of the present invention;
fig. 4 is a schematic diagram of a reference voltage output circuit according to a third embodiment of the present invention;
fig. 5 is a schematic diagram of a reference voltage output circuit according to a fourth embodiment of the present invention;
fig. 6 is a schematic diagram of a reference voltage output circuit according to a fifth embodiment of the present invention.
Detailed Description
So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings.
Fig. 2 is a logic schematic diagram of a reference voltage output circuit according to a first embodiment of the present invention, and as shown in fig. 2, the reference voltage output circuit according to the first embodiment of the present invention includes: a conversion circuit 201, a voltage generation circuit 202, and an output circuit 203; the conversion circuit 201 is connected to a reference current source Iref, the conversion circuit 201 is connected to the voltage generation circuit 202, and the voltage generation circuit 202 is connected to the output circuit 203.
In this embodiment, the reference current source is used to provide a reference current and input the reference current to the conversion circuit, and in order to enable the whole circuit to work normally, an external dc voltage source needs to be provided for the reference voltage output circuit in this embodiment.
The principle of operation of the circuit of fig. 2 is as follows:
the conversion circuit 201 receives a reference current input by the reference current source Iref, converts the reference current according to a first conversion parameter to obtain a first reference current, and outputs the first reference current to the voltage generation circuit 202;
the voltage generation circuit 202 divides the voltage based on the first reference current, generates at least a first reference voltage, and outputs the first reference voltage to the output circuit 203;
the output circuit 203 biases the first reference voltage, generates a second reference voltage, and outputs the second reference voltage.
In this embodiment, the conversion circuit 201 multiplexes the reference current input by the reference current source, and generates a first reference current according to a first conversion parameter, where the first conversion parameter is determined according to the specification and size of a circuit device in the conversion circuit 201, and the first conversion parameter is actually a proportional parameter, for example, a ratio of the reference current to the first reference current to be generated is 2, and the ratio 2 is the first conversion parameter.
The conversion circuit 201 in this embodiment may be a current mirror circuit structure, and the output first reference current is obtained by copying the input reference current according to a certain ratio according to the current mirror. When the voltage generation circuit 202 divides the voltage based on the first reference current, one or more first reference voltages may be generated according to the requirement of the output voltage source of the output circuit 203.
It should be understood by those skilled in the art that the multi-reference voltage source output circuit in the embodiment of the present invention is an active circuit, and the active circuit must be at a reasonable dc operating point of current and voltage to normally operate according to the design requirement, i.e., the bias is to make the device operate at the required dc operating point. The method of biasing is not limited to the use of a bias resistor and current mirror circuit.
The embodiment of the invention has the advantages that one path of reference current is multiplexed by the conversion circuit, at least one reference voltage is generated by the voltage generation circuit, and the output circuit is adopted for bias processing and outputting the reference voltage, so that the use of a complex operational amplifier structure is avoided, an on-chip multi-path voltage source structure is realized, the power consumption is low, the whole volume is smaller, and the multi-path voltage source structure is more suitable for a plurality of voltage sources.
Fig. 3 is a schematic diagram of a multi-reference-voltage-source output circuit according to a second embodiment of the present invention, and fig. 3 shows a specific connection relationship among the conversion circuit 201, the voltage generation circuit 202, and the output circuit 203 based on the multi-reference-voltage-source output circuit in fig. 2.
The conversion circuit 201 includes: a first field effect transistor MP _ Imir10 and a second field effect transistor MP _ Imir 11;
the drain of the first fet MP _ Imir10 is connected to the reference current source Iref, the drain of the first fet MP _ Imir10, the gate of the first fet MP _ Imir10, and the gate of the second fet MP _ Imir11 are connected in common, and the drain of the second fet MP _ Imir11 is connected to the voltage generating circuit 202;
wherein the first conversion parameter is determined by the first fet MP _ Imir10 channel dimension parameter and the second fet MP _ Imir11 channel dimension parameter.
In this embodiment, the first fet MP _ Imir10 and the second fet MP _ Imir11 are P-channel fets PMOS transistors, or N-channel fets NMOS transistors, where the P-channel fets PMOS transistors are only one preferred embodiment of the present invention.
In this embodiment, the source of the first fet MP _ Imir10 and the source of the second fet MP _ Imir11 are both connected to an external dc voltage source AVDD, and the whole circuit is powered by the external voltage source. The first conversion parameter is determined according to the channel size parameter of the first field effect transistor MP _ Imir10 and the channel size parameter of the second field effect transistor MP _ Imir11The over-conversion circuit 201 converts the reference current into a first reference current, for example, the first conversion parameter is K, so that the first reference current is IMP_Imir11＝KIMP_Imir10＝KIref。
It should be understood by those skilled in the art that, here, MP _ Imir10 and MP _ Imir11 in fig. 3 constitute PMOS current mirrors, and the first conversion parameter K in the foregoing needs to satisfy the condition that the third field-averaging transistor MN _ ref in the voltage generation circuit shifts the first reference voltage to cancel the gate-source voltage on the output tubes MN _ out1, MN _ out2, and MN _ out3, where MN _ out1, MN _ out2, and MN _ out3 are reference voltage output tubes.
The voltage generation circuit 202 includes: a third field effect transistor MN _ ref and a first reference resistor Rref 1;
the source of the third fet MN _ ref is connected to the first end of the first reference resistor Rref1, the drain of the third fet MN _ ref is connected to the switching circuit 201, the second end of the first reference resistor Rref1 is grounded, the drain of the third fet MN _ ref is connected to the gate of the third fet MN _ ref, and the drain of the third fet MN _ ref is connected to the output circuit 203.
The voltage generation circuit 202 further includes a second reference resistor Rref 2;
the drain of the third fet MN _ ref is connected to the second terminal of the second reference resistor Rref2, the first terminal of the second reference resistor Rref2 is connected to the switching circuit 201, and the first terminal of the second reference resistor Rref2 is connected to the output circuit 203.
The voltage generation circuit 202 further includes a third reference resistor Rref 3;
a second terminal of the third reference resistor Rref3 is connected to a first terminal of the second reference resistor Rref2, a first terminal of the third reference resistor Rref3 is connected to the switching circuit 201, and a first terminal of the third reference resistor Rref3 is connected to the output circuit 203.
The voltage generation circuit 202 further includes:
the source of the third field effect transistor MN _ ref is grounded, and the drain of the third field effect transistor MN _ ref is connected to the second end of the first reference resistor Rref 1; or the like, or, alternatively,
the source of the third fet MN _ ref is connected to the first end of the third reference resistor Rref3, and the drain of the third fet MN _ ref is connected to the switching circuit 201; or the like, or, alternatively,
the source of the third fet MN _ ref is connected to the first terminal of the second reference resistor Rref2, and the drain of the third fet MN _ ref is connected to the second terminal of the third reference resistor Rref 3;
the first reference voltage is shifted by the third field effect transistor MN _ ref, and the first reference voltage is generated and output.
In this embodiment, the third fet MN _ ref is an NMOS transistor, where the third fet MN _ ref is used to shift the first reference voltage, and the voltage generation circuit 202 performs the voltage division and shift processes as follows:
first, in the conversion circuit 201, the first reference current I flowing through the second field effect transistor MP _ Imir11MP_Imir11Voltage division is performed on the first reference resistor Rref1, the second reference resistor Rref2, and the third reference resistor Rref3, and a first reference voltage is generated.
Then, the third fet MN _ ref connected in series with the reference resistor is used for voltage shifting to offset the gate-source voltage of the output tubes MN _ out1, MN _ out2, MN _ out3, wherein MN _ out1 is the fourth fet, MN _ out2 is the fifth fet, MN _ out3 is the tenth fet.
So that Vout1 is K × Iref × Rref1+ VGS_MN_ref-VGS_MN_out1
Wherein, VGS_MN_refIs the voltage difference between the gate and the source of MN _ ref, VGS_MN_out1Is the voltage difference between the gate and source of MN _ out1, where VGS_MN_refAnd VGS_MN_out1Are equal in value.
A first reference voltage is output at MN _ out1 as,
Vout1＝K×Iref×Rref1；
the same principle is that:
a first reference voltage is output at MN _ out2 as,
Vout2＝K×Iref×(Rref1+Rref2)；
a first reference voltage is output at MN _ out2 as,
Vout3＝K×Iref×(Rref1+Rref2+Rref3)；
vout1, Vout1, and Vout1 are labeled voltage output terminals, respectively.
It should be noted that the third fet MN _ ref is connected in series with the first reference resistor Rref1, the second reference resistor Rref2, and the third reference resistor Rref3, where the third fet may also be a PMOS transistor.
The output circuit 203 includes: a fourth field effect transistor MN _ out1 and a bias resistor Rs 1;
the gate of the fourth fet MN _ out1 is connected to the voltage generating circuit 202, the source of the fourth fet MN _ out1 is connected to the first end of the bias resistor Rs1, the second end of the bias resistor Rs1 is grounded, and the source of the fourth fet MN _ out1 is connected to the first analog load Rload 1;
the first reference voltage received by the gate of the fourth field effect transistor MN _ out1 is biased by the bias resistor Rs1, and the second reference voltage is generated and output.
The output circuit 203 includes: a fifth field effect transistor MN _ out2 and a first current mirror circuit; the first current mirror circuit comprises a sixth field effect transistor MN _ Imir20 and a seventh field effect transistor MN _ Imir 21;
a drain of the sixth fet MN _ Imir20, the conversion circuit 201, a gate of the sixth fet MN _ Imir20, and a gate of the seventh fet MN _ Imir21 are connected in common, a source of the sixth fet MN _ Imir20 is grounded, a gate of the fifth fet MN _ out2 is connected to the voltage generation circuit 202, a source of the fifth fet MN _ out2 is connected to a drain of the seventh fet MN _ Imir21, a source of the seventh fet MN _ Imir21 is grounded, and a source of the fifth fet MN _ out2 is connected to a second analog load Rload 2;
wherein the first reference voltage received by the gate of the fifth field effect transistor MN _ out2 is biased by the first current mirror circuit, and the second reference voltage is generated and output.
The output circuit includes: a transconductance linear circuit and a second current mirror circuit; the transconductance linear circuit comprises a ninth field-effect tube MN _ s3, a tenth field-effect tube MN _ out3, an eleventh field-effect tube MP _ s31 and a twelfth field-effect tube MP _ s 32; the second current mirror circuit comprises a sixth field effect transistor MN _ Imir20 and an eighth field effect transistor MN _ Imir 22;
a gate of the ninth fet MN _ s3, a gate of the tenth fet MN _ out3, and the voltage generating circuit 202 are connected in common, a source of the ninth fet MN _ s3 is connected to a source of the eleventh fet MP _ s31, a source of the tenth fet MN _ out3 is connected to a source of the twelfth fet MP _ s32, a drain of the eleventh fet MP _ s31, a gate of the eleventh fet MP _ s31, a gate of the twelfth fet MP _ s32, and a drain of the eighth fet MN _ Imir22 are connected in common, and a gate of the eighth fet MN _ Imir22, a gate of the sixth fet MN _ Imir20, a drain of the sixth fet MN _ irir 20, and the converting circuit 201 are connected in common; the source of the eighth fet MN _ Imir22 and the drain of the twelfth fet MP _ s32 are both grounded, and the source of the tenth fet MN _ out3 and the source of the twelfth fet MP _ s32 are both connected to a third analog load Rload 3;
the transconductance linear circuit is used for adjusting a driving factor of the first reference voltage commonly received by the gate of the ninth field-effect transistor MN _ s3 and the gate of the tenth field-effect transistor MN _ out3, and the second current mirror circuit is used for biasing the adjusted first reference voltage to generate and output the second reference voltage.
The adjusting, by the transconductance linear circuit, the drive factor of the first reference voltage commonly received by the gate of the ninth fet MN _ s3 and the gate of the tenth fet MN _ out3 includes:
at the source of the tenth fet MN _ out3, increasing the drive factor by sourcing current;
at the source of the twelfth FET MP _ s32, the drive factor is reduced by a sink current.
In the present embodiment, fig. 3 shows three different types of output circuits 203.
In the first output circuit LDO1, the first reference voltage is mainly biased by a bias resistor RS 1. In the present invention, the fourth fet MN _ out1 adopts an NMOS transistor as an output transistor of the output circuit 203, which can be replaced by a PMOS transistor in practical application. Here, the drain of the fourth fet MN _ out1 needs to be connected to the external dc voltage source AVDD.
In the second output circuit LDO2, the first reference voltage is mainly biased by a current mirror circuit, wherein the current mirror circuit of the present invention is composed of two NMOS transistors, i.e., the sixth fet MN _ Imir20 and the seventh fet MN _ Imir21, which can also be replaced by PMOS transistors. The fifth field effect transistor MN _ out2 adopts an NMOS transistor as an output transistor of the output circuit.
It should be understood by those skilled in the art that the drain of the fifth fet MN _ out2 is connected to the external voltage source AVDD, and the drain of the sixth fet MN _ Imir20 is used for receiving the second reference current from the converting circuit 201.
In the third output circuit LDO3, a transconductance linear circuit is mainly used to adjust the driving factor of the output voltage, and a current mirror circuit is also used to bias, wherein the current mirror circuit is also composed of NMOS transistors, in order to simplify the circuit structure, a part of the structure of the current mirror circuit is that the sixth field effect transistor MN _ Imir20 is designed in the second output circuit, and the eighth field effect transistor MN _ Imir22 is designed in the third output circuit, which does not affect the stability of the whole circuit and does not cause other effects. The cross-conductor linear circuit consists of a ninth field-effect tube MN _ s3, a tenth field-effect tube MN _ out3, an eleventh field-effect tube MP _ s31 and a twelfth field-effect tube MP _ s32, wherein the eighth field-effect tube, the ninth field-effect tube and the tenth field-effect tube are all NMOS tubes, and the eleventh field-effect tube MP _ s31 and the twelfth field-effect tube MP _ s32 are all PMOS tubes. In practical application, according to different design requirements, the POMO tube can be replaced by the NMOS tube, and the NMOS tube can be replaced by the PMOS tube.
It should be noted that, here, the ninth fet MN _ s3 and the tenth fet MN _ out3 are both connected to the external dc voltage source AVDD. The pull-up current provides current to the load (e.g., current flows out of the source of MN _ out3 into the load), and the design herein prevents the potential at this point from decreasing as current flows out of the source of MN _ out 3. The tenth fet MN _ out3 is an NMOS transistor, and serves as a source follower to provide current to the load. The driving factor of the first reference voltage, i.e. the driving capability of the first reference voltage, is increased by the source current, i.e. the driving capability is increased, so that the potential at the point is prevented from being reduced as the current flows out of the source terminal of the MN _ out 3.
Similarly, sinking current draws current from the load (current flows out of the load into the source of MP _ s 32), and the present design avoids the potential at this point rising as current flows into the source of MP _ s 32. The twelfth fet MP _ s32 is a PMOS transistor and acts as a source follower to sink current from the load. The driving factor of the first reference voltage, i.e., the driving capability of the first reference voltage, is reduced by the sink current, i.e., the driving capability of the first reference voltage is reduced, thereby preventing the potential at the point from rising as the current flows into the source terminal of MP _ s 32.
The output circuit with three different types has the characteristics that the output tube of the LDO1 in fig. 3 adopts the current of the bias resistor Rs1 as the direct current bias current of the output tube, and the structure is simpler. The output tube of the LDO2 in fig. 3 uses the current of the current mirror as the dc bias current of the output tube, and the accuracy of the output Vout2 is higher. The LDO3 of fig. 3 employs a transconductance linear circuit to provide pull-up and pull-down current capability to the output node Vout 3.
The conversion circuit 201 further includes a thirteenth field effect transistor MP _ Imir 12;
a gate of the thirteenth fet MP _ Imir12, a gate of the first fet MP _ Imir10, and a drain of the first fet MP _ Imir10 are connected in common, and a drain of the thirteenth fet MP _ Imir12 is connected to the output circuit 203;
and after receiving the reference current through the gate of the first field effect transistor MP _ Imir10, converting the reference current according to a second conversion parameter to generate and output a second reference current.
The second conversion parameter is determined by the channel size parameter of the first fet MP _ Imir10 and the channel size parameter of the third fet MP _ Imir 12.
In the embodiment of the present invention, a thirteenth field effect transistor MP _ Imir12 is connected in parallel to the current mirror structure in the converting circuit 201, and the operating principle of the current mirror structure is the same as that of the converting circuit described above, and the current mirror structure can provide a second reference current for the output circuit 203, so that the second output circuit LDO2 and the third output circuit LDO3 of the required current mirror circuit can ensure that the accuracy of the output voltage is higher when the current of the current mirror is used as the dc bias current of the output tube.
The embodiment of the invention has the advantages that one path of reference current is multiplexed by the conversion circuit, at least one reference voltage is generated by the voltage generation circuit, and the output circuit is adopted for bias processing and outputting the reference voltage, so that the use of a complex operational amplifier structure is avoided, an on-chip multi-path voltage source structure is realized, the power consumption is low, the whole volume is smaller, and the multi-path voltage source structure is more suitable for a plurality of voltage sources.
In the process of circuit design, more branch voltage source outputs can be formed by using the same principle as LDO1, LDO2 and LDO3 in the second embodiment.
Fig. 4 shows a reference voltage output circuit according to a third embodiment of the present invention, which is modified from the second embodiment of the present invention as shown in fig. 4 by using only two reference resistors, and the LDO2 is designed with the same structure as the LDO 1.
In the present embodiment, LDO1 and LDO2 respectively use resistors Rs1 and Rs2 to generate dc bias currents.
The embodiment of the invention has the advantages that one path of reference current is multiplexed by the conversion circuit, at least one reference voltage is generated by the voltage generation circuit, and the output circuit is adopted for bias processing and outputting the reference voltage, so that the use of a complex operational amplifier structure is avoided, an on-chip multi-path voltage source structure is realized, the power consumption is low, the whole volume is smaller, and the multi-path voltage source structure is more suitable for a plurality of voltage sources.
Fig. 5 shows a reference voltage output circuit according to a fourth embodiment of the present invention, which is modified from the second embodiment of the present invention in that three reference resistors are used, and LDO3 is designed with the same structure as LDO2, as shown in fig. 5.
In the present embodiment, LDOs 1 and 2 each use current mirror currents (MN _ Imir21 and MN _ Imir22) to generate dc bias currents.
The embodiment of the invention has the advantages that one path of reference current is multiplexed by the conversion circuit, at least one reference voltage is generated by the voltage generation circuit, and the output circuit is adopted for carrying out bias processing and outputting the reference voltage, so that the use of a complex operational amplifier structure is avoided, an on-chip multi-path voltage source structure is realized, the power consumption is low, the whole volume is small, the on-chip multi-path voltage source structure is more suitable for a plurality of voltage sources, and the advantage of high precision of the output voltage is realized.
Fig. 6 shows a reference voltage output circuit according to a fifth embodiment of the present invention, which is modified from the second embodiment of the present invention in that three reference resistors are used, and LDO2 is designed with the same structure as LDO3, as shown in fig. 6.
In the embodiment, each of LDO2 and LDO3 has a transconductance linear structure.
The embodiment of the invention has the advantages that one path of reference current is multiplexed by the conversion circuit, at least one reference voltage is generated by the voltage generation circuit, and the output circuit is adopted for bias processing and outputting the reference voltage, so that the use of a complex operational amplifier structure is avoided, an on-chip multi-path voltage source structure is realized, the power consumption is low, the whole volume is small, and the invention is more suitable for a plurality of voltage sources, so that LDO2 and LDO3 have the capabilities of pull-up current and pull-down current.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A reference voltage output circuit, comprising: a conversion circuit, a voltage generation circuit, and an output circuit; the conversion circuit is connected with a reference current source, the conversion circuit is connected with the voltage generation circuit, and the voltage generation circuit is connected with the output circuit;
after receiving the reference current input by the reference current source, the conversion circuit converts the reference current according to a first conversion parameter to obtain a first reference current, and outputs the first reference current to the voltage generation circuit;
the voltage generation circuit divides the voltage based on the first reference current, generates at least a first reference voltage, and outputs the first reference voltage to the output circuit;
the output circuit biases the first reference voltage, generates and outputs a second reference voltage;
wherein the output circuit comprises: a fifth field effect transistor and a first current mirror circuit; the first current mirror circuit comprises a sixth field effect transistor and a seventh field effect transistor;
the drain electrode of the sixth field effect transistor, the conversion circuit, the grid electrode of the sixth field effect transistor and the grid electrode of the seventh field effect transistor are connected in common, the source electrode of the sixth field effect transistor is grounded, the grid electrode of the fifth field effect transistor is connected with the voltage generation circuit, the source electrode of the fifth field effect transistor is connected with the drain electrode of the seventh field effect transistor, the source electrode of the seventh field effect transistor is grounded, and the source electrode of the fifth field effect transistor is connected with the second analog load;
biasing, by the first current mirror circuit, the first reference voltage received by the gate of the fifth field effect transistor, and generating and outputting the second reference voltage;
and/or
A transconductance linear circuit and a second current mirror circuit; the transconductance linear circuit comprises a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor and a twelfth field effect transistor; the second current mirror circuit comprises a sixth field effect transistor and an eighth field effect transistor;
the grid electrode of the ninth field effect transistor, the grid electrode of the tenth field effect transistor and the voltage generating circuit are connected in common, the source electrode of the ninth field effect transistor is connected with the source electrode of the eleventh field effect transistor, the source electrode of the tenth field effect transistor is connected with the source electrode of the twelfth field effect transistor, the drain electrode of the eleventh field effect transistor, the grid electrode of the twelfth field effect transistor and the drain electrode of the eighth field effect transistor are connected in common, and the grid electrode of the eighth field effect transistor, the grid electrode of the sixth field effect transistor, the drain electrode of the sixth field effect transistor and the converting circuit are connected in common; the source electrode of the eighth field effect transistor and the drain electrode of the twelfth field effect transistor are both grounded, and the source electrode of the tenth field effect transistor and the source electrode of the twelfth field effect transistor are both connected with a third analog load;
and the transconductance linear circuit is used for adjusting a driving factor of the first reference voltage received by the grid electrode of the ninth field effect transistor and the grid electrode of the tenth field effect transistor, and the second current mirror circuit is used for biasing the adjusted first reference voltage to generate and output the second reference voltage.
2. The reference voltage output circuit according to claim 1, wherein the conversion circuit comprises: a first field effect transistor and a second field effect transistor;
the drain electrode of the first field effect transistor is connected with the reference current source, the drain electrode of the first field effect transistor, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are connected in common, and the drain electrode of the second field effect transistor is connected with the voltage generating circuit;
wherein the first conversion parameter is determined by the first FET channel size parameter and the second FET channel size parameter.
3. The reference voltage output circuit according to claim 2, wherein the voltage generation circuit includes: a third field effect transistor and a first reference resistor;
the source electrode of the third field effect transistor is connected with the first end of the first reference resistor, the drain electrode of the third field effect transistor is connected with the conversion circuit, the second end of the first reference resistor is grounded, the drain electrode of the third field effect transistor is connected with the grid electrode of the third field effect transistor, and the drain electrode of the third field effect transistor is connected with the output circuit.
4. The reference voltage output circuit according to claim 3, wherein the voltage generation circuit further includes a second reference resistance;
the drain electrode of the third field effect transistor is connected with the second end of the second reference resistor, the first end of the second reference resistor is connected with the conversion circuit, and the first end of the second reference resistor is connected with the output circuit.
5. The reference voltage output circuit according to claim 4, wherein the voltage generation circuit further includes a third reference resistance;
the second end of the third reference resistor is connected with the first end of the second reference resistor, the first end of the third reference resistor is connected with the conversion circuit, and the first end of the third reference resistor is connected with the output circuit.
6. The reference voltage output circuit according to claim 5, wherein the voltage generation circuit further comprises:
the source electrode of the third field effect transistor is grounded, and the drain electrode of the third field effect transistor is connected with the second end of the first reference resistor; or the like, or, alternatively,
the source electrode of the third field effect transistor is connected with the first end of the third reference resistor, and the drain electrode of the third field effect transistor is connected with the conversion circuit; or the like, or, alternatively,
the source electrode of the third field effect transistor is connected with the first end of the second reference resistor, and the drain electrode of the third field effect transistor is connected with the second end of the third reference resistor;
and shifting the first reference voltage through the third field effect transistor, generating the first reference voltage and outputting the first reference voltage.
7. The reference voltage output circuit according to claim 6, wherein the output circuit comprises: a fourth field effect transistor and a bias resistor;
the grid electrode of the fourth field effect transistor is connected with the voltage generating circuit, the source electrode of the fourth field effect transistor is connected with the first end of the bias resistor, the second end of the bias resistor is grounded, and the source electrode of the fourth field effect transistor is connected with the first analog load;
and the first reference voltage received by the grid electrode of the fourth field effect transistor is biased through the bias resistor, and the second reference voltage is generated and output.
8. The reference voltage output circuit of claim 1, wherein the adjusting, by the transconductance linear circuit, the driving factor of the first reference voltage commonly received by the gate of the ninth fet and the gate of the tenth fet comprises:
increasing the driving factor by a source current at a source of the tenth fet;
and reducing the driving factor by sinking current at the source of the twelfth FET.
9. The reference voltage output circuit according to claim 2, wherein the conversion circuit further comprises a thirteenth field effect transistor;
the grid electrode of the thirteenth field effect tube, the grid electrode of the first field effect tube and the drain electrode of the first field effect tube are connected in common, and the drain electrode of the thirteenth field effect tube is connected with the output circuit;
and after receiving the reference current through the grid electrode of the first field effect transistor, converting the reference current according to a second conversion parameter to generate and output a second reference current.
10. The reference voltage output circuit of claim 9, wherein the second conversion parameter is determined by the first fet channel size parameter and the thirteenth fet channel size parameter.
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| CN201810225465.5A CN108427472B (en) | 2018-03-19 | 2018-03-19 | Reference voltage output circuit |
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| CN201810225465.5A CN108427472B (en) | 2018-03-19 | 2018-03-19 | Reference voltage output circuit |
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| CN112527046B (en) * | 2019-09-17 | 2022-07-01 | 成都纳能微电子有限公司 | Voltage conversion current circuit with high power supply rejection ratio |
| CN115617115B (en) * | 2022-10-31 | 2023-04-21 | 北京智芯微电子科技有限公司 | Reference voltage generating circuit, chip and electronic equipment |
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| US4958123A (en) * | 1987-12-23 | 1990-09-18 | U.S. Philips Corporation | Circuit arrangement for processing sampled analogue electrical signals |
| US6963188B2 (en) * | 2004-04-06 | 2005-11-08 | Atmel Corporation | On-chip power supply interface with load-independent current demand |
| CN103235633B (en) * | 2013-05-15 | 2015-10-21 | 聚辰半导体(上海)有限公司 | A kind of bidirectional current reconditioning circuit and current scalping method thereof |
| CN105929887B (en) * | 2016-05-18 | 2017-09-05 | 华南理工大学 | A kind of broadband low power consumption current difference channel |
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Address after: 510663 8th floor, building C2, Chuangxin building, No. 182, Kexue Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Guangzhou Huizhi Microelectronics Co.,Ltd. Address before: 510663 unit c3-802, innovation building, 182 science Avenue, Science City, Guangzhou high tech Industrial Development Zone, Guangdong Province Patentee before: SMARTER MICROELECTRONICS (GUANG ZHOU) Co.,Ltd. |