CN106018926A - Micro-current detection circuit - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits and relates to a micro-current detection circuit. A high-speed weak-current detector circuit applicable to large capacitance is divided into a front-level transimpedance amplifier, a voltage and current converter and a rear-level transimpedance amplifier. The front-level transimpedance amplifier is a low-input-impedance low-gain transimpedance amplifier, achieves part of gain of the circuit under wide enough band, isolates large capacitance input into a node, and inhibits first-level noise. The intermediate stage is the voltage and current converter, voltage signals output by the first-level transimpedance amplifier are converted into current signals, and processing of the rear-level transimpedance amplifier is benefited. The rear-level transimpedance amplifier is a high-gain transimpedance amplifier, provides certain gain for the circuit and improves circuit driving capacity. Thus, the whole structure can achieve wide band and high gain.

Description

A kind of micro-current sensing circuit

Technical field

The invention belongs to electronic circuit technology field, relate to a kind of micro-current sensing circuit.

Background technology

In high-speed sensor integrated circuit, the faintest electricity that sensor produces after receiving other non-electrical signals Stream signal, meanwhile, these sensor front end parasitic capacitances are bigger.Especially in high speed optoelectronic integrated circuit, light Electric diode produces faint current signal after receiving optical signal.Process information for the ease of late-class circuit, need Current signal is converted into the voltage signal of suitable amplitude, therefore it is required that prime Weak current signal detection circuit has relatively Big gain；And in the case of considering that sensor front end parasitic capacitance, particularly electric capacity are relatively big so that overall Circuit can not obtain high gain and big bandwidth simultaneously, is especially requiring that integrated circuit has preferable noise-induced In the case of energy, the compromise of gain and bandwidth becomes apparent from.

The parasitic capacitance of adjustable type cascade (RGC) circuit structure energy preferably isolated preceding-terminal sensor, but make an uproar Acoustic performance is poor；Other current detection circuits are typically only suitable for the situation that parasitic capacitance is less.

Summary of the invention

To be solved by this invention, it is simply that high-gain cannot to be realized for above-mentioned existing micro-current sensing circuit simultaneously With the restriction of high bandwidth, the problem that especially bandwidth is the widest in the case of photocell parasitic capacitance is big.Propose A kind of high speed weak current detector circuit being applicable to bulky capacitor.

The technical scheme is that a kind of high speed weak current detector circuit being applicable to bulky capacitor, including before Level trans-impedance amplifier, voltage current adapter, rear class trans-impedance amplifier and biasing circuit；Described prime is put across resistance Big device is by the first resistance R1, the second resistance R2, the 3rd resistance RF1, the first electric capacity CF1, a NMOS Pipe MN1 and the second NMOS tube MN2 are constituted；The grid of the first NMOS tube MN1 is detection electric current input End, the drain electrode of the first NMOS tube MN1 is followed by power supply by the first resistance R1, the first NMOS tube MN1 Source ground；The grid of the second NMOS tube MN2 meets the drain electrode of the first NMOS tube MN1, the 2nd NMOS The drain electrode of pipe MN2 connects power supply, and the source electrode of the second NMOS tube MN2 is by ground connection after the second resistance R2；The The grid of one NMOS tube MN1 is followed by the second NMOS tube M2 source electrode and the second electricity by the 3rd resistance RF1 The junction point of resistance R2；First electric capacity CF1 and the 3rd resistance RF1 is in parallel.Described voltage current adapter is by Four resistance R3, the second electric capacity C1, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS Pipe MN5, the first PMOS MP1, the second PMOS MP2 and operational amplifier are constituted；Operation amplifier The in-phase end of device is the input of voltage current adapter, and the end of oppisite phase of operational amplifier passes sequentially through the 4th resistance R3 and the second electric capacity C1 ground connection, the grid of output termination the 3rd NMOS tube MN3 of operational amplifier；The The drain electrode of three NMOS tube MN3 connects the drain electrode of the first PMOS MP1, the source of the 3rd NMOS tube MN3 Pole connects the drain electrode of the 4th NMOS tube MN4；The source ground of the 4th NMOS tube MN4, the 4th NMOS The grid of pipe MN4 connects the grid of the 5th NMOS tube MN5；The drain electrode of the 5th NMOS tube MN5 connects second The drain electrode of PMOS MP2, the source ground of the 5th NMOS tube MN5；First PMOS MP1 Source electrode connects power supply, and the grid of the first PMOS MP1 connects the grid of the second PMOS MP2；2nd PMOS The source electrode of pipe MP2 connects power supply, the drain electrode of the second PMOS MP2 and the drain electrode of the 5th NMOS tube MN5 It is connected, for the output IOUT1 of voltage current adapter.Described rear class trans-impedance amplifier is that a standard is amplified across resistance Device.

Beneficial effects of the present invention is, the high speed weak current detector circuit being applicable to bulky capacitor of the present invention is divided into Prime trans-impedance amplifier, voltage current adapter and rear class trans-impedance amplifier three grades, prime trans-impedance amplifier is low Input impedance, the trans-impedance amplifier of low gain, realize a part of gain of circuit under sufficiently wide bandwidth, every From the bulky capacitor of input node, the noise of the suppression first order；Intergrade is Voltage to current transducer level, by the first order The voltage signal of trans-impedance amplifier output is converted into current signal, it is simple to rear class trans-impedance amplifier processes；Rear class across Impedance amplifier is high-gain trans-impedance amplifier, provides certain gain for circuit and increases drives ability.From And overall architecture can realize bandwidth and high-gain.

Accompanying drawing explanation

Fig. 1 is micro-current sensing circuit framework proposed by the invention；

Fig. 2 is a kind of example circuit of the present invention shifted to an earlier date level trans-impedance amplifier；

Fig. 3 is carried voltage current adapter electrical block diagram by the present invention；

Fig. 4 is rear class trans-impedance amplifier electrical block diagram proposed by the invention.

Detailed description of the invention

Below in conjunction with the accompanying drawings, technical scheme is described in detail:

In the present invention, it is contemplated that signal input node parasitic capacitance is big, can have a strong impact on the increasing of trans-impedance amplifier Benefit bandwidth product, it is impossible on the premise of meeting transmission speed, weak current signal is amplified to output suitably by a step Voltage signal.Therefore, as it is shown in figure 1, the present invention will be divided into prime across resistance and rear class trans-impedance amplifier two across resistance Level realizes total transimpedance gain, and front and back stages connects with a voltage-current converter circuit between resistance.Prime across Impedance amplifier is the trans-impedance amplifier of low input impedance, low gain, realizes the one of circuit under sufficiently wide bandwidth Fractionated gain, the bulky capacitor of isolation input node, the noise of the suppression first order；Owing to prime is across the letter of resistance output Number being voltage signal, in order to rear class can continue normal amplification across resistance, centre addition voltage-current converter circuit is by front The voltage signal of level output is converted into current signal, and meanwhile, voltage-current converter circuit is provided that certain electric current Gain；Prime is the least across the voltage signal of resistance output, and it is big that rear class voltage amplifier realizes difficulty, therefore Rear class selects trans-impedance amplifier.Material is thus formed circuit structure shown in Fig. 1, be also the circuit protected of the present invention Structure.Multistage amplifier noise coefficient calculates formula

$N_{F1~n}=N_{F1}+\frac{N_{F2}-1}{G_1}+\frac{N_{F3}-1}{G_1{G}_2}+\frac{N_{F4}-1}{G_1{G}_2{G}_3}+...+\frac{N_{Fn}-1}{G_1{G}_2{G}_3...G_{(n-1)}}$

Wherein N_FxFor the noise coefficient of xth level amplifier, G_xGain for xth level amplifier.By above formula Can draw, the overall noise factor of multistage amplifier depends primarily on the noise coefficient of the first order, the most below Amplifier is the least on total noise coefficient impact.For the first order, noise coefficient should be the least, and gain is most Amount is big.In the present invention, owing to input node parasitic capacitance is big, therefore to expect enough bandwidth, gain can not Too big, the noise coefficient of prime trans-impedance amplifier can only be reduced as far as possible.Common source configuration circuit has the spy that noise is little Point, therefore the present invention selects common source configuration as first order trans-impedance amplifier.Protected due to the present invention is one Plant architecture and method, and be not limited to specific trans-impedance amplifier physical circuit.For the ease of illustrating and understanding this The content of invention, is the most only an example with prime trans-impedance amplifier shown in Fig. 2, illustrates the benefit of the present invention. Certainly the present invention can also use other concrete trans-impedance amplifier structures to realize.Shown in Fig. 2, prime is put across resistance The transimpedance gain of big device is R_F1, carry a width of:

${\mathrm{\ω}}_{-3dB}=\frac{g_{mn1}{R}_1}{2\mathrm{\π}\·(C_p+C_{F1})R_{F1}}$

C_pFor input parasitic capacitance, g_mn1For NMOS tube M1 across resistance.

Equivalence to the noise of input is

$\stackrel{\‾}{V_{n,in}^2}=4kT(\frac{2}{3g_{mn1}}+\frac{1}{g_{mn1}^2{R}_1})+\frac{K}{C_{ox}WL}\frac{1}{f}$

Drawn by bandwidth formula and input noise formula, by increasing g_mn1And R₁Bandwidth and attenuating can be increased simultaneously Noise, in conjunction with transimpedance gain R_F1, so that prime trans-impedance amplifier is meeting bandwidth demand, have simultaneously Of a sufficiently low noise coefficient.

As it is shown on figure 3, in voltage-current converter circuit, NMOS tube MN4 and MN5 provide direct current biasing for circuit, PMOS MP1 and MP2 are current mirror, the electric current after conversion is exported rear class, and provides certain electric current Gain.Voltage-current converter circuit mutual conductance is g_m=V_IN1/R₃。

From the point of view of comprehensive prime trans-impedance amplifier and voltage current adapter, it is achieved be the function of Current amplifier, electricity Flow enhancement is g_m=m_RF1/R₃, m is the breadth length ratio ratio with the breadth length ratio of MP1 of PMOS MP2.

Rear class trans-impedance amplifier is tradition trans-impedance amplifier, but owing to sensor parasitic capacitance is isolated, because of This rear class trans-impedance amplifier input node parasitic capacitance is the parasitic capacitance of front stage circuits outlet tube, therefore bandwidth For

${\mathrm{\ω}}_{-3dB}=\frac{A}{2\mathrm{\π}\·(C_{db.MP2}+C_{db.MN5}+C_{in2})R_{F2}}$

C_db.MP2For the electric capacity between the drain electrode of PMOS MP2 and substrate, C_db.MN5Drain for NMOS tube MN5 And the electric capacity between substrate, C_in2For rear class trans-impedance amplifier input capacitance.Because C_db.MP2、C_db.MN5And C_in2 The least, therefore rear class trans-impedance amplifier can be in the case of meeting bandwidth, by R_F2Arrange the biggest.

By above-mentioned analysis, the total transimpedance gain of the carried current detection circuit of the present invention is

$g_m=\frac{{\mathrm{mR}}_{F1}{R}_{F2}}{R_3}$

And the big parasitic capacitance of current detection circuit input node is isolated by prime low gain trans-impedance amplifier, rear class is across resistance Amplifier input capacitance will become the least, therefore for the bandwidth of integrated circuit and ratio of gains tradition trans-impedance amplifier, Can arrange is higher, meets the demand in high-gain, broadband.

Claims (1)

1. a micro-current sensing circuit, including prime trans-impedance amplifier, voltage current adapter, rear class trans-impedance amplifier and partially Circuits；Described prime trans-impedance amplifier by the first resistance R1, the second resistance R2, the 3rd resistance RF1, the first electric capacity CF1, First NMOS tube MN1 and the second NMOS tube MN2 are constituted；The grid of the first NMOS tube MN1 is defeated for detection electric current Entering end, the drain electrode of the first NMOS tube MN1 is followed by power supply by the first resistance R1, the source electrode of the first NMOS tube MN1 Ground connection；The grid of the second NMOS tube MN2 connects the drain electrode of the first NMOS tube MN1, the leakage of the second NMOS tube MN2 Pole connects power supply, and the source electrode of the second NMOS tube MN2 is by ground connection after the second resistance R2；The grid of the first NMOS tube MN1 Pole is followed by the second NMOS tube M2 source electrode and the junction point of the second resistance R2 by the 3rd resistance RF1；First electric capacity CF1 with 3rd resistance RF1 is in parallel.Described voltage current adapter by the 4th resistance R3, the second electric capacity C1, the 3rd NMOS tube MN3, 4th NMOS tube MN4, the 5th NMOS tube MN5, the first PMOS MP1, the second PMOS MP2 and computing Amplifier is constituted；The in-phase end of operational amplifier is the input of voltage current adapter, and the end of oppisite phase of operational amplifier leads to successively Cross the 4th resistance R3 and the second electric capacity C1 ground connection, the grid of output termination the 3rd NMOS tube MN3 of operational amplifier；The The drain electrode of three NMOS tube MN3 connects the drain electrode of the first PMOS MP1, and the source electrode of the 3rd NMOS tube MN3 connects the 4th The drain electrode of NMOS tube MN4；The source ground of the 4th NMOS tube MN4, the grid of the 4th NMOS tube MN4 connects The grid of five NMOS tube MN5；The drain electrode of the 5th NMOS tube MN5 connects the drain electrode of the second PMOS MP2, and the 5th The source ground of NMOS tube MN5；The source electrode of the first PMOS MP1 connects power supply, the grid of the first PMOS MP1 Connect the grid of the second PMOS MP2；The source electrode of the second PMOS MP2 connects power supply, the leakage of the second PMOS MP2 Pole is connected with the drain electrode of the 5th NMOS tube MN5, for the output IOUT1 of voltage current adapter.