JP2008072590A - Amplifier circuit and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To expand the linearity at a low gain in a variable gain amplifier. <P>SOLUTION: In a variable gain amplifier VGA obtained by controlling current source connected to common source of differential pair SP<SB>1</SB>consisting of the same size by control voltage, a linearization circuit LCC where a differential pair SP2 using a transistor whose size ratio (M:K) is different and another differential pair SP3 whose size ratio (K:M) is different are connected in parallel is constituted. The VGA and the LCC are connected in parallel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention is a technique related to high linearization of a variable gain amplifier.

  In a receiver that receives a radio signal, the power of the radio signal is about 100 dB, so the amplitude of the received signal is at a predetermined level at the input of the A / D converter that converts the received analog signal into a digital signal. Need to control.

  On the other hand, if the transmitter knows that more input power than necessary is transmitted on the receiving side, the transmitting power is controlled so that a predetermined level can be received on the receiving side.

The function of changing the gain of the receiver and the function of changing the transmission power are performed by a variable gain amplifier. A conventional example of the variable gain amplifier VGA is shown in FIG. Between the common source terminal and the ground of the MOS transistors M1 and M2 forming a differential pair SP1, the variable current source I ₁ is connected. The output current is taken from the drain terminals of the MOS transistors M1 and M2. For simplification of the drawing, the differential pair SP1 is shown in FIG. 13 (b).

  By the way, the variable gain differs depending on the operation region of the MOS transistors M1 and M2. The operation region where the gate voltage is higher than the gate threshold voltage and the drain current increases in proportion to the gate voltage is called a strong inversion region, and the operation region where the gate voltage is lower than the gate threshold voltage and the drain current hardly flows. Is called the weak inversion region. In the relationship between the gate voltage and the drain current, the strong inversion region shows a square characteristic, and the weak inversion region shows an exponential characteristic.

Here, when the MOS transistors M1 and M2 have a square characteristic, the mutual conductance gm corresponding to the gain is
gm = 2√ (βI _d )
It is expressed as Here, β = (1/2) μ Cox (W / L), μ is the mobility, Cox is the capacitance of the oxide film, W is the gate width, and L is the gate length. I _d is the drain current.

When the MOS transistors M1 and M2 have exponential characteristics, the mutual conductance gm is
gm = I _d / (nV _T )
It is expressed as Here, n represents a constant related to the process, and VT represents a thermal voltage, which is 26 mV at room temperature.

Here, MOS transistors M1 and M2 are for the case of square characteristic, consider the input range of the input voltage V _in consisting of a potential difference of the voltage applied to the gate terminal of the MOS transistors M1 and M2. Incidentally, here, for example, a range in which linearity is ensured (a range in which the gain is constant) is set as the input range R, but this input range R is a non-linear range in which linearity is not ensured (input voltage V _in Range in which the gain changes in response to a change in the

When the MOS transistor M1 is cut off (no current flows) and the current Id flows only in the MOS transistor M2, the voltage Vlim applied to both ends of the gate terminals of the MOS transistors M1 and M2 is
Vlim = √ (I _d / β)
It is. This voltage Vlim serves as an index of the input range R of the variable gain amplifier (differential amplifier) VGA.

  From the above equation representing the voltage Vlim, if the current Id is decreased to reduce the gain, Vlim will decrease. FIG. 14 shows the voltage Vlim at the mutual conductance G1max when the current Id is maximized and the gain is maximized, and at the mutual conductance G1min when the current Id is decreased and the gain is minimized.

  Therefore, as the gain is lowered, the linearity of the variable gain amplifier VGA deteriorates (that is, the input range R decreases). However, in this case, it is assumed that the influence of distortion on the output side of the variable gain amplifier VGA is not considered. As the current Id is further reduced, the square characteristic changes to an exponential characteristic. In the exponential characteristic, the characteristic is almost the same as that of the bipolar transistor, so that the input range R is lowered to about nVT. Thereafter, the input range R does not decrease.

  FIG. 15 shows a transmission unit TX using a direct modulation scheme. The quadrature modulator OM includes mixers MX1 and MX2 and a phase shifter PH, and modulates the LO signal output from the local oscillator LO11 with an I / Q signal obtained through a D / A converter and an LPF sequentially. The output is input to the variable gain amplifier VGA, and the signal amplitude is adjusted by the control signal. The output of the variable gain amplifier VGA is amplified by the power amplifier PA at the next stage, and radio waves are emitted from an antenna (not shown) via the filter BPF. In this case, the output of the quadrature modulator OM is constant regardless of the power emitted from the antenna.

When the variable gain amplifier VGA shown above is used, when the gain is lowered, the input range R is reduced, so that the output signal is distorted. When the output signal is distorted, the modulation accuracy is deteriorated and unnecessary radiation increases. Therefore, it is necessary to reduce the distortion of the output signal as much as possible.
JP 2001-196880 A T. Yamaji, et.al., “A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range”, IEEE J. Solid-State Circuits, pp.553-558, May, 2002.

  An object of the present invention is to expand linearity (that is, a range in which gain is constant) at a low gain in a variable gain amplifier.

An amplifier circuit according to one embodiment of the present invention includes:
A first transistor having a gate terminal serving as a first input terminal; a second transistor having a gate terminal serving as a second input terminal and having a dimensional ratio of K: M (K>M); A first differential amplifier circuit comprising: a first current source for supplying a first current to a source terminal of one transistor and a source terminal of the second transistor;
A third transistor having a gate terminal serving as a third input terminal, a fourth transistor having a gate terminal serving as a fourth input terminal and a dimensional ratio of M: K, and a source terminal of the third transistor; And a second current source for supplying a second current to the source terminal of the fourth transistor, and a second differential amplifier circuit having the same gain as that of the first differential amplifier circuit;
A fifth transistor having a gate terminal serving as a fifth input terminal; a sixth transistor having a gate terminal serving as a sixth input terminal and having a dimensional ratio of 1: 1 to the fifth transistor; and a source terminal of the fifth transistor And a variable current source that supplies a third current to the source terminal of the sixth transistor, and the gain of the first differential amplifier circuit is greater than the first differential amplifier circuit when the third current has a first magnitude. The third current and the fifth transistor are combined so that the third current is smaller than the gain of the first differential amplifier circuit when the third current is a second magnitude different from the first magnitude. A third differential amplifier circuit;
With
The first input terminal, the third input terminal and the fifth input terminal are connected to each other to form one end of a differential input terminal,
The second input terminal, the fourth input terminal and the sixth input terminal are connected to each other to form the other end of the differential input terminal;
The drain terminal of the first transistor, the drain terminal of the third transistor and the drain terminal of the fifth transistor are connected to each other to form one end of a differential output end,
The drain terminal of the second transistor, the drain terminal of the fourth transistor, and the drain terminal of the sixth transistor are connected to each other to form the other end of the differential output terminal.

  An amplifier circuit according to one embodiment of the present invention includes a structure in which each transistor of the amplifier circuit is configured as a bipolar transistor, and the gate terminal, the source terminal, and the drain terminal are read as a base terminal, an emitter terminal, and a collector terminal, respectively. It is a thing.

  A communication device according to one embodiment of the present invention is a communication device including a transmission circuit, in which an amplifier circuit connected to a subsequent stage of a modulator included in the transmission circuit adopts the configuration of the amplifier circuit.

  According to the present invention, the linearity at the time of low gain can be expanded in the variable gain amplifier.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a variable gain amplifier 10 according to an embodiment of the present invention. The variable gain amplifier (that is, an amplifier circuit) 10 includes a variable gain amplifier VGA having first and second transistors M1 and M2 and a first current source I1 having substantially the same gate width, and the variable gain amplifier VGA. The third and fourth transistors M3 and M4 and the second current source I2 which are connected in parallel and have different gate widths, and the fifth and sixth transistors M5 and M6 and the third current source I3 which have different gate widths. The gate width ratio between the third transistor M3 and the fourth transistor M4 is substantially equal to the gate width ratio between the sixth transistor M6 and the fifth transistor M5. And a linearization circuit LCC.

  That is, the sources of the first and second transistors M1 and M2 are connected in common and connected to the first current source I1, and the sources of the third and fourth transistors M3 and M4 are connected in common and connected to the second. The sources of the fifth and sixth transistors M5 and M6 are connected in common and connected to the third current source I3.

  The gates of the first, third, and fifth transistors M1, M3, and M5 are commonly connected and connected to the first voltage input terminal VIN1, and the second, fourth, and sixth transistors M2, M4, and M6 are connected. The gates are commonly connected and connected to the second voltage input terminal VIN2.

  The drains of the first, third, and fifth transistors M1, M3, and M5 are commonly connected and connected to the first current output terminal IOUT1, and the second, fourth, and sixth transistors M2, M4, and M6 are connected. The drains are connected in common and connected to the second current output terminal IOUT2.

When the first current source I1 generates the _first gain control current I1 based on a gain control signal supplied from the outside, that is, the gain control voltage _VCNT , the gain control voltage _VCNT increases in response to the increase. The first gain control current I ₁ is generated so as to decrease the first gain control current I ₁ .

Second and third current sources I2 and I3 are the second gain control current I ₂ having substantially the same current value generated respectively, and the gain control voltage V _CNT and gain control currents I _1, I ₂ relationship As the current characteristic indicating the current characteristic, the current characteristic is different from that of the first current source I1.

Incidentally, the first transistor in the present embodiment corresponds to the fifth transistor in the claims, and similarly, the second transistor in the present embodiment corresponds to the sixth transistor. The third transistor in this embodiment corresponds to the first transistor, the fourth transistor in this embodiment corresponds to the second transistor, and the fifth transistor in this embodiment corresponds to the third transistor. The fourth transistor in the form corresponds to the third transistor. The first current source I1 in the present embodiment corresponds to a variable current source that supplies a third current, and the second current source I2 in the present embodiment has a first current that supplies the first current. The third current source I3 in the present embodiment corresponds to the second current source that supplies the second current. The differential pair SP1 in the present embodiment corresponds to the third differential amplifier circuit, the differential pair SP2 in the present embodiment corresponds to the first differential amplifier circuit, and the differential pair in the present embodiment. SP3 corresponds to the second differential amplifier circuit. Further, the first voltage input terminal VIN1 in the present embodiment corresponds to one end of the differential input end, and the second voltage input terminal VIN2 in the present embodiment corresponds to the other end of the differential input end. The first current output terminal IOUT1 in the embodiment corresponds to one end of the differential output end, and the second current output terminal IOUT2 in the present embodiment corresponds to the other end of the differential output end. Further, the differential pair SP1 (third differential amplifier circuit) has a gain of the differential pair SP2 (first differential amplifier circuit) when the gain control current I ₁ (third current) is the first magnitude. Larger than the gain of the differential pair SP1 (first differential amplifier circuit) when the gain control current I ₁ (third current) is a second magnitude different from the first magnitude. The control current I ₁ (third current) and the first transistor (fifth transistor) were combined.

Here, the variable gain amplifier G1 (VGA) is composed of a differential amplifier, and the tail current flowing through the variable current source I1, that is, the gain control current I ₁ is composed of f (V _CNT ) controlled by the gain control voltage V _CNT. . Here, f (V _CNT ) is a gain control current I ₁ that decreases exponentially as the gain control voltage V _CNT increases, and f (V _CNT ) = A exp (−V _CNT ).

On the other hand, the amplifier G2 has a configuration in which a differential pair SP2 having a gate width ratio of M: K and a differential pair SP3 having a gate width ratio of K: M are connected in parallel. The gate length is the same for all differential pairs. Each gain control current is I ₂ and is expressed by a function g (V _CNT ) different from f (V _CNT ) with respect to the gain control voltage V _CNT .

  Here, the amplifier G2 is used to expand the linearity at the time of low gain in the variable gain amplifier G1, and is referred to as a linearization circuit (LCC). Amplifier G2, ie LCC, is connected in parallel with variable gain amplifier G1.

  FIG. 2 shows the differential pair portion of the variable gain amplifier G1 and the amplifier G2 shown in FIG. 1 using simplified symbols. Note that there are two gain control currents of the amplifier G2, but the simplified symbol is only one. Hereinafter, the operation of the variable gain amplifier 10 will be described.

As described above, the tail current of the variable gain amplifier G1, that is, the gain control current I ₁ here, is the current I ₁ = A exp that changes exponentially with respect to the gain control voltage V _CNT input from the outside. It is represented by (-V _CNT ).

Here, it is assumed that the gain control voltage V _CNT changes from the voltage V _CNT0 to the voltage V _CNT1 , and the gain control current I ₁ changes from the maximum A exp (−V _CNT0 ) to the minimum A exp (−V _CNT1 ). . When the gain control current I ₁ is a maximum value, MOS transistors of the variable gain amplifier G1 operates in strong inversion region.

  This condition means that the MOS transistor of the variable gain amplifier G1 is not made larger than necessary. That is, in the strong inversion region, the current density flowing through the MOS transistor is much higher than that in the weak inversion region, so that the size of the MOS transistor can be made smaller than operating in the weak inversion region. That is, the cutoff frequency fT of the MOS transistor can be increased, and the parasitic capacitor of the MOS transistor can be reduced, so that high speed can be improved with a small current.

At this time, since the mutual conductance of the variable gain amplifier G1 is expressed by gm = 2√ (βI ₁ ) (I ₁ ≈I _d ), the mutual conductance changes exponentially with respect to _VCNT . This characteristic is hereinafter referred to as a linear-in-dB characteristic. When the gain control voltage is V _CNT0 , the mutual conductance takes the highest value and is G1max. When the gain control voltage V _CNT is increased, the mutual conductance gradually decreases, and the maximum value V _CNT1 is the lowest G1min.

On the other hand, the operation of the LCC, that is, the amplifier G2, will be described in two cases. First, as shown in FIG. 2, without depending on the gain control voltage V _CNT, described for the first approach to the gain control current I ₂ of the amplifier G2 constant. FIG. 3 shows the relationship between the gain control currents I ₁ and I ₂ and the gain control voltage _VCNT at this time.

In this case, the first current source I1, in response to the gain control voltage V _CNT is increased, so as to reduce the first gain control current I ₁ exponentially, first gain control current I ₁ And the second and third current sources I2 and I3 generate a _second gain control current I2 having a substantially constant value, respectively.

The amplifier G2 has a configuration in which two asymmetric differential pairs are connected. Transconductance gm2 of each, when the gain control current I _2, the gate width ratio of the differential pair to be equal to the transconductance G1min M: setting the K.

By doing so, the amplifier G2 is the gain control voltage V _CNT always constant current 2I ₂ flows irrespective of the gate width ratio M: when the offset voltage VOFF which is a function of K, the peak of the transconductance gm2 mutual The amplifier has a value equal to the peak of the conductance G1min. Note that VOFF = {(m−1) / (m + 1)} / √ (mβ) × I2. Here, m = M / K, M> K.

FIG. 4 shows the mutual conductance of the variable gain amplifier G1 and the amplifier G2 at the minimum gain and the maximum gain. Incidentally, here, for example, a range in which linearity is ensured (a range in which the gain is constant) is set as the input range R, but this input range R is a non-linear range in which linearity is not ensured (input voltage V _in Range in which the gain changes in response to a change in the

  As apparent from FIG. 4, since the input range R of the variable gain amplifier G1 is wide at the maximum gain and the mutual conductance G1max is high, the small mutual conductance gm2 of the amplifier G2 can be ignored. The input range R is determined by the mutual conductance G1max.

On the other hand, to reduce the gain control current I _1, when the mutual conductance of the variable gain amplifier G1 and minimum G1min, transconductance gm2 of amplifier G2 has a peak at a predetermined offset voltage VOFF, yet the value is equal to G1min . In this case, the mutual conductance G1min of the variable gain amplifier G1 and the two mutual conductances gm2 in the amplifier G2 are added, so that the input range R is expanded by at least the offset voltage VOFF when there is no amplifier G2.

FIG. 5 shows the gain, that is, the dependence of the mutual conductance, on the gain control voltage _VCNT . When the MOS transistor is operating in the strong inversion region at the minimum gain of the variable gain amplifier G1 (that is, when operating in the strong inversion region for all gains), the V _CNT dependence of the variable gain amplifier G1 is Shows linear-in-dB characteristics, and the vertical axis is a logarithmic graph.

In this case, since the mutual conductance of the amplifier G2 is constant, the mutual conductance G of the entire variable gain amplifier 10 may be slightly high near the minimum gain. This is because the mutual conductance of the amplifier G2 near the offset voltage VOFF = 0V (V _in = 0) is added to the mutual conductance of the variable gain amplifier G1.

Accordingly, the mutual conductance G = G1 + G2 of the entire variable gain amplifier 10 is higher than the minimum value of the variable gain amplifier G1. However, this deviation always occurs and is anticipated in advance, and can be avoided by adjusting the gain control signal _VCNT . Further, when the gain control characteristic does not require high accuracy, there is no problem because the deviation of the gain control characteristic is small.

  Here, a method for making the linear-in-dB characteristic more accurate will be described. In this case, the variable gain amplifier VGA operates the first and second transistors M1 and M2 in the strong inversion region in the vicinity of the maximum gain in the gain range that the variable gain amplifier VGA can change, and in the vicinity of the minimum gain, The first and second transistors M1 and M2 are operated in the weak inversion region.

  If the minimum gain Gmin of the variable gain amplifier G1 is set to operate in the weak inversion region, the gain control characteristic of the variable gain amplifier G1 deviates from the linear-in-dB characteristic. That is, when the transition is made from the strong inversion region to the weak inversion region, the slope of the linear-in-dB characteristic becomes steep so as to transition from 1 to 2.

  Figure 6 shows this characteristic. In this way, when the mutual conductance Gmin is set in the weak inversion region, the slope of the linear-in-dB characteristic of the variable gain amplifier G1 changes, but the overall mutual conductance increases due to the mutual conductance of the amplifier G2. By using, the range of the lnear-in-dB characteristic (gain range GR that can be changed) can be increased compared to the case of FIG.

Next, as shown in FIG. 7, a second method for making the gain control current I ₂ of the amplifier G2 dependent on the gain control voltage _VCNT will be described. In FIG. 7, since the gain control current I ₂ is different from the gain control current I ₁ , I ₂ = g (V _CNT ) is described.

In this case, the first current source I1, in response to the gain control voltage V _CNT is increased, so as to reduce the first gain control current I ₁ exponentially, first gain control current I ₁ The second and third current sources I2 and I3 respectively generate the _second gain control current I2 so as to increase monotonously as the gain control voltage _VCNT increases.

As a control method, as shown in FIG. 8, when the gain control voltage _VCNT increases, the gain control current I ₂ also increases. That is, I ₂ = g (V _CNT ) = B ₁ (V _CNT ) × V _CNT ; B ₁ (V _CNT ) ≧ 0. However, when the mutual conductance of the variable gain amplifier G1 is minimized G1min, as in the first approach to the gain control current I ₂ is constant, the peak transconductance gm2 of amplifier G2 is equal to the peak of the transconductance G1min Thus, the gain control current I ₂ and the gate width ratio M: K of the differential pair are set.

By doing so, since it reduces the gain control current I ₂ of the amplifier G2 when setting the maximum gain, and low power consumption can be achieved. Here, only one asymmetric differential pair is considered, but the same is true even when there are a plurality of pairs.

  FIG. 9 shows gain control characteristics when the variable gain amplifier G1 is all in the strong inversion region up to the minimum gain. As shown in FIG. 5, the variable gain amplifier G1 has a linear-in-dB gain control characteristic, but the overall gain control characteristic G = G1 + G2 including the amplifier G2 is linear-in near the minimum gain. Deviation from -dB occurs. However, this deviation always occurs and is expected in advance, and can be avoided by adjusting the gain control voltage VCNT. Further, when the gain control characteristic does not require high accuracy, there is no problem because the deviation of the gain control characteristic is small.

  A method for reducing the deviation from the linear-in-dB gain control characteristic will be described with reference to FIG. MOS transistors have a strong inversion region and a weak inversion region depending on operating conditions, and input / output characteristics are a square characteristic and an exponential characteristic, respectively. For this reason, the gain slope is 1 to 2. As shown in FIG. 6, if the minimum gain of the variable gain amplifier G1 is set in the weak inversion region, the minimum mutual conductance G1min of the variable gain amplifier G1 and the peak of the mutual conductance gm2 of the amplifier G2 are added. The overall transconductance G = G1 + G2 of the variable gain amplifier 20 can maintain the linear-in-dB characteristic up to the minimum gain.

  By the way, if the variable gain amplifiers 10 and 20 according to the present embodiment are provided after the quadrature modulator (not shown) in the transmitter (FIG. 15), it is possible to avoid the input range R from being reduced even if the gain is lowered. Can do. Thereby, distortion of the output signal can be suppressed, and deterioration of modulation accuracy and increase of unnecessary radiation can be suppressed.

Thus, according to the present embodiment, the differential pair SP1 having a gate width ratio of 1: 1, the differential pair SP2 having a gate width ratio of M: K, and the differential pair having a gate width ratio of K: M. SP3 are connected in parallel, gain control current I ₁ of the differential pair SP1 exponentially reduced against the gain control voltage V _CNT, the gain control current I ₂ of the differential pair SP2 and SP3 to the gain control current I ₁ Use a different current. Moreover, either a constant value irrespective of the gain control voltage V _CNT, or increases with respect to the gain control voltage V _CNT. By making the transconductance when the gain by the differential pair SP1 is the minimum gain the same as the transconductance of the differential pairs SP2 and SP3, the linearity at the minimum gain can be expanded.

  Thus, since the linearity of the variable gain amplifier at the time of low gain can be expanded, the variable range per stage of the variable gain amplifier can be widened. As a result, the number of necessary stages of the variable gain amplifier can be reduced, so that power consumption can be reduced.

  In the above-described embodiment, the amplifier G2 (LCC) has been described using a differential pair having a gate width ratio of M: K and a differential pair having a gate width ratio of K: M connected in parallel. However, if this idea is expanded, a differential pair with a gate width ratio of M1: K1 and K1: M1, a differential pair with a gate width ratio of M2: K2 and K2: M2, Mn: Kn and Kn: Mn If differential pairs having a gate width ratio of 2 are connected in parallel, the linear range can be further expanded. However, when used in an RF circuit, increasing the number of parallels increases the parasitic capacitance and increases the signal loss, so it is better to reduce the number of parallels. For example, as described above, there are many cases where the number of parallelism is two, that is, n = 1 is suitable.

  In the above-described embodiment, it has been described that the input range at the time of low gain is expanded in the application of the transmitter. However, in the application of the receiver, it is generally necessary to expand the input range at the time of low gain. This is because the receiver is controlled to obtain a predetermined amplitude. For example, when the input signal of the variable gain amplifier 10 (29) becomes large, the gain of the variable gain amplifier 10 (20) is reduced so that the output of the variable gain amplifier 10 (20) becomes constant.

  The variable gain amplifiers 10 and 20 of the present embodiment can be applied to the variable gain amplifier VGA of the transmission unit TX and the variable gain amplifier VGA of the reception unit. FIG. 11 shows a direct modulation transmitter / receiver 30.

  The receiving unit RX includes a low-noise amplifier LNA having a fixed gain at the first stage, and amplifies a weak signal received with low noise. Thereafter, the signal is input to the quadrature demodulator OD that converts the frequency into an I / Q signal via the variable gain amplifier VGA. When the variable gain amplification function is added to the function of the low noise amplifier LNA, the variable gain amplifier VGA can be omitted. The I / Q signal is input to the variable gain amplifier VGA in order to match the amplitude suitable for the input level of the A / D converter after unnecessary waves outside the desired band are removed by the low-pass filter LPF.

  The transmission unit TX is the same as that shown in FIG. The variable gain amplifiers 10 and 20 of the present embodiment are applicable to the above-described variable gain amplifier VGA.

  In the above-described embodiment, the variable gain amplifier 10 (20) using the MOS transistor has been described. However, as shown in FIG. 12, the same effect can be obtained by using the bipolar transistor.

  In this case, the variable gain amplifier (that is, the amplifier circuit) 30 includes a variable gain amplifier VGA having first and second bipolar transistors B1 and B2 and a first current source I1 having substantially the same emitter area, and the variable gain. The third and fourth bipolar transistors B3 and B4 and the second current source I2 connected in parallel to the amplifier VGA and having different emitter areas, and the fifth and sixth bipolar transistors B5 and B6 having the different emitter areas and the second The ratio of the emitter areas of the third bipolar transistor B3 and the fourth bipolar transistor B4 is the ratio of the emitter areas of the sixth bipolar transistor B6 and the fifth bipolar transistor B5. And a linearization circuit LCC formed so as to be substantially equal to.

  That is, the emitters of the first and second bipolar transistors B1 and B2 are connected in common and connected to the first current source I1, and the emitters of the third and fourth bipolar transistors B3 and B4 are connected in common. Connected to the second current source I2, the emitters of the fifth and sixth bipolar transistors B5 and B6 are connected in common and connected to the third current source I3.

  The bases of the first, third, and fifth bipolar transistors B1, B3, and B5 are connected in common and connected to the first voltage input terminal VIN1, and the second, fourth, and sixth bipolar transistors B2, B4, and The bases of B6 are connected in common and connected to the second voltage input terminal VIN2.

  The collectors of the first, third and fifth bipolar transistors B1, B3 and B5 are connected in common and connected to the first current output terminal IOUT1, and the second, fourth and sixth bipolar transistors B2, B4 and The collectors of B6 are commonly connected and connected to the second current output terminal IOUT2.

When the first current source I1 generates the _first gain control current I1 based on the gain control voltage _VCNT applied from the outside, the first gain source I1 responds to the increase in the gain control voltage _VCNT. to reduce the control current I _1, and generates a first gain control current I _1.

Second and third current sources I2 and I3 are the second gain control current I ₂ having substantially the same current value generated respectively, and the gain control voltage V _CNT and gain control currents I _1, I ₂ relationship As the current characteristic indicating the current characteristic, the current characteristic is different from that of the first current source I1.

  That is, the variable gain amplifier G1 is a variable gain amplifier having a linear-in-dB characteristic, and the amplifier G2 improves the linearity of the variable gain amplifier G1 when the gain is low.

Here, the gain control current I ₂ = g (VCNT) for controlling the gain of the amplifier G2 is different from the gain control current I ₁ = f (V _CNT ) of the variable gain amplifier G1. That is, in the above-described embodiment, the MOS transistor at the maximum gain is limited to the square characteristic, but this embodiment is effective even if the operating region of the MOS transistor at the maximum gain is an exponential characteristic. is there. However, in the MOS transistor, the input / output characteristics change depending on the operation region, but in the bipolar transistor, the operation region does not change. For this reason, it is impossible to correct the linear-in-dB characteristics shown in FIG. 6 and FIG.

The block diagram of the variable gain amplifier of this Embodiment. The block diagram of the variable gain amplifier of this Embodiment. Gain control current I ₂ of the gain control current I ₁ and the amplifier G2 of the variable gain amplifier G1. Comparison of the input range of the variable gain amplifier G1 and the input range of the variable gain amplifier G1 and the amplifier G2. Gain control characteristic by variable gain amplifier G1 and amplifier G2 of square characteristic. Gain control characteristics by variable gain amplifier G1 and amplifier G2 having square characteristics and exponential characteristics. The block diagram of the variable gain amplifier of this Embodiment. Gain control current I ₂ of the gain control current I ₁ and the amplifier G2 of the variable gain amplifier G1. Gain control characteristic by variable gain amplifier G1 and amplifier G2 of square characteristic. Gain control characteristics by variable gain amplifier G1 and amplifier G2 having square characteristics and exponential characteristics. A direct conversion type transceiver including the variable gain amplifier of the present embodiment. The block diagram of the variable gain amplifier of other embodiment. Conventional variable gain amplifier. The input range of maximum gain and minimum gain of a conventional variable gain amplifier. Direct conversion transmitter.

Explanation of symbols

VGA: Variable gain amplifier
M: MOS transistor
LCC: Linearization circuit
SP: differential pair
G: Amplifier
LNA: Low noise amplifier
BPF: Band pass filter
LPF: Low-pass filter
A / D: Analog to digital converter
D / A: Digital-to-analog converter
LO: Local oscillator

Claims (8)

A first transistor having a gate terminal serving as a first input terminal; a second transistor having a gate terminal serving as a second input terminal and having a dimensional ratio of K: M (K>M); A first differential amplifier circuit comprising: a first current source for supplying a first current to a source terminal of one transistor and a source terminal of the second transistor;
A third transistor having a gate terminal serving as a third input terminal, a fourth transistor having a gate terminal serving as a fourth input terminal and a dimensional ratio of M: K, and a source terminal of the third transistor; And a second current source for supplying a second current to the source terminal of the fourth transistor, and a second differential amplifier circuit having the same gain as that of the first differential amplifier circuit;
A fifth transistor having a gate terminal serving as a fifth input terminal; a sixth transistor having a gate terminal serving as a sixth input terminal and having a dimensional ratio of 1: 1 to the fifth transistor; and a source terminal of the fifth transistor And a variable current source that supplies a third current to the source terminal of the sixth transistor, and the gain of the first differential amplifier circuit is greater than the first differential amplifier circuit when the third current has a first magnitude. The third current and the fifth transistor are combined so that the third current is smaller than the gain of the first differential amplifier circuit when the third current is a second magnitude different from the first magnitude. A third differential amplifier circuit;
With
The first input terminal, the third input terminal and the fifth input terminal are connected to each other to form one end of a differential input terminal,
The second input terminal, the fourth input terminal and the sixth input terminal are connected to each other to form the other end of the differential input terminal;
The drain terminal of the first transistor, the drain terminal of the third transistor and the drain terminal of the fifth transistor are connected to each other to form one end of a differential output end,
An amplifier circuit, wherein the drain terminal of the second transistor, the drain terminal of the fourth transistor, and the drain terminal of the sixth transistor are connected to each other to form the other end of the differential output terminal.   2. The amplification according to claim 1, wherein the variable current source supplies a third current whose relationship with a control voltage having a linear relationship with an output current of the differential output terminal is exponential. circuit. The variable current source decreases the third current exponentially as the control voltage increases,
The amplifier circuit according to claim 2, wherein the first and second current sources generate the first and second currents having substantially constant values, respectively. The variable current source decreases the third current exponentially as the control voltage increases,
3. The amplifier circuit according to claim 2, wherein the first and second current sources generate the first and second currents so as to monotonously increase as the control voltage increases. 4. A seventh transistor having a gate terminal serving as a seventh input terminal; an eighth transistor having a gate terminal serving as an eighth input terminal and having a dimensional ratio of L: N (K ≠ M); A fourth differential amplifier circuit having a fourth current source for supplying a fourth current to a source terminal of the eighth transistor and a source terminal of the eighth transistor;
The seventh input terminal is connected to the one end of the differential input terminal;
The eighth input terminal is connected to the other end of the differential input terminal;
The drain terminal of the seventh transistor serves as the one end of the differential output end;
2. The amplifier circuit according to claim 1, wherein a drain terminal of the eighth transistor serves as the other end of the differential output terminal. The first and second transistors are formed by MOS transistors,
The first differential amplifier circuit operates the first and second transistors in a strong inversion region near a maximum gain in a gain range that can be changed by the first differential amplifier, and near the minimum gain, The amplifier circuit according to claim 1, wherein the first and second transistors are operated in a weak inversion region. A first transistor having a base terminal serving as a first input terminal, a second transistor having a base terminal serving as a second input terminal and a dimensional ratio of K: M (K>M); A first differential amplifier circuit having a first current source for supplying a first current to an emitter terminal of one transistor and an emitter terminal of the second transistor;
A third transistor having a base terminal serving as a third input terminal, a fourth transistor having a base terminal serving as a fourth input terminal and a dimensional ratio of M: K, and an emitter terminal of the third transistor; And a second current source for supplying a second current to the emitter terminal of the fourth transistor, and a second differential amplifier circuit having the same gain as the gain of the first differential amplifier circuit;
A fifth transistor having a base terminal serving as a fifth input terminal, a sixth transistor having a base terminal serving as a sixth input terminal and a dimensional ratio of 1: 1 with the fifth transistor, and an emitter terminal of the fifth transistor And a variable current source for supplying a third current to the emitter terminal of the sixth transistor, and when the third current has a first magnitude, the gain of the first differential amplifier circuit is larger than the gain of the first differential amplifier circuit. The third current and the fifth transistor are combined so that the third current is smaller than the gain of the first differential amplifier circuit when the third current is a second magnitude different from the first magnitude. A third differential amplifier circuit;
With
The first input terminal, the third input terminal and the fifth input terminal are connected to each other to form one end of a differential input terminal,
The second input terminal, the fourth input terminal and the sixth input terminal are connected to each other to form the other end of the differential input terminal;
The collector terminal of the first transistor, the collector terminal of the third transistor, and the collector terminal of the fifth transistor are connected to each other to form one end of a differential output end,
An amplifying circuit, wherein a collector terminal of the second transistor, a collector terminal of the fourth transistor, and a collector terminal of the sixth transistor are connected to each other to form the other end of the differential output terminal. In a communication device having a transmission circuit,
The amplifier circuit connected to the subsequent stage of the modulator included in the transmission circuit is:
A first transistor having a gate terminal serving as a first input terminal; a second transistor having a gate terminal serving as a second input terminal and having a dimensional ratio of K: M (K>M); A first differential amplifier circuit comprising: a first current source for supplying a first current to a source terminal of one transistor and a source terminal of the second transistor;
A third transistor having a gate terminal serving as a third input terminal, a fourth transistor having a gate terminal serving as a fourth input terminal and a dimensional ratio of M: K, and a source terminal of the third transistor; And a second current source for supplying a second current to the source terminal of the fourth transistor, and a second differential amplifier circuit having the same gain as that of the first differential amplifier circuit;
A fifth transistor having a gate terminal serving as a fifth input terminal; a sixth transistor having a gate terminal serving as a sixth input terminal and having a dimensional ratio of 1: 1 to the fifth transistor; and a source terminal of the fifth transistor And a variable current source that supplies a third current to the source terminal of the sixth transistor, and the gain of the first differential amplifier circuit is greater than the first differential amplifier circuit when the third current has a first magnitude. The third current and the fifth transistor are combined so that the third current is smaller than the gain of the first differential amplifier circuit when the third current is a second magnitude different from the first magnitude. A third differential amplifier circuit;
With
The first input terminal, the third input terminal and the fifth input terminal are connected to each other to form one end of a differential input terminal,
The second input terminal, the fourth input terminal and the sixth input terminal are connected to each other to form the other end of the differential input terminal;
The drain terminal of the first transistor, the drain terminal of the third transistor and the drain terminal of the fifth transistor are connected to each other to form one end of a differential output end,
The communication device, wherein the drain terminal of the second transistor, the drain terminal of the fourth transistor, and the drain terminal of the sixth transistor are connected to each other to form the other end of the differential output terminal.

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