CN106017385A - Preparation method of step height standard sample block with nominal height ranging from 10 mu m to 100 mu m - Google Patents

Preparation method of step height standard sample block with nominal height ranging from 10 mu m to 100 mu m Download PDF

Info

Publication number
CN106017385A
CN106017385A CN201610578470.5A CN201610578470A CN106017385A CN 106017385 A CN106017385 A CN 106017385A CN 201610578470 A CN201610578470 A CN 201610578470A CN 106017385 A CN106017385 A CN 106017385A
Authority
CN
China
Prior art keywords
etching
height
sample block
preparation
silicon wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610578470.5A
Other languages
Chinese (zh)
Other versions
CN106017385B (en
Inventor
冯亚南
李锁印
韩志国
吴爱华
赵琳
许晓青
梁法国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 13 Research Institute
Original Assignee
CETC 13 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 13 Research Institute filed Critical CETC 13 Research Institute
Priority to CN201610578470.5A priority Critical patent/CN106017385B/en
Publication of CN106017385A publication Critical patent/CN106017385A/en
Application granted granted Critical
Publication of CN106017385B publication Critical patent/CN106017385B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01BMEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/02Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness
    • G01B21/04Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness by measuring coordinates of points
    • G01B21/042Calibration or calibration artifacts
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01BMEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/02Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness
    • G01B21/08Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness for measuring thickness
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes

Abstract

The invention discloses a preparation method of a step height standard sample block with nominal height ranging from 10 mu m to 100 mu m, and the preparation method belongs to the technical field of step profiler calibration. The preparation method comprises the steps of: adopting a double-side polished silicon wafer as a substrate material; growing an oxidation layer on the surface of the silicon wafer; painting a photoresist on the surface of oxidation layer; exposing, wherein a mask plate is negative plate, and a graphic region is a light-transmitting region; removing the photoresist from the light-transmitting region; adopting a reactive ion etching machine for etching, and etching the oxidation layer in a step region which is not masked by the photoresist away; adopting a deep reactive ion etching machine for etching the silicon wafer, and etching the silicon wafer in the step region which is not masked by the photoresist, wherein the etching depth is less than the nominal height of the standard sample block to be prepared; removing the photoresist; carrying out wet etching, wherein the etching depth reaches the requirement of the nominal height; and sputtering a metal protective layer on the surface of the silicon wafer, so as to prepare the desired standard sample block. The preparation method can accurately control the step height, meets the requirements of the standard sample block, and is low in cost.

Description

A kind of preparation method of nominal height 10 μm-100 μm standard step height sample block
Technical field
The invention belongs to step instrument collimation technique field, particularly relate to the preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block.
Background technology
The test problem of a large amount of shoulder height is related to during integrated circuit and micro electronic mechanical system (MEMS) processing technology, the accurate measurement to step parameter, it is to ensure that the important means of device quality.At present, in semicon industry, shoulder height is measured by main use step instrument, and wherein the measuring method of step instrument mainly has: contact type measurement method and optical measuring method.Regardless of the step instrument of type, it is measured parameter and is the height value in samples vertical direction.Finding shows: China has thousand of of various step class measuring instruments, and this quasi-instrument is widely used in research and production unit, and the popularity rate of instrument is the highest.In order to ensure that step instrument obtains accurate data in the range of gamut, it should use a series of standard step height sample block consistent with step instrument range that step instrument is calibrated.
External VLSI has the standard step height sample block of micron dimension, use mask plate as substrate, use dry etch process to prepare step standard sample, the sample block depth of parallelism prepared by the method, have good uniformity, roughness is little, it is possible to meet the demand of semicon industry calibration step class measuring instrument.But, use mask plate to prepare step sample block processing technique as substrate complicated, cost is high.The domestic shoulder height sample block not having micron dimension, the step of altitude range 10 μm-100 μm uses two gauge block lapping-ins on optical flat to obtain, but the step accuracy obtained is low, step is discontinuous, roughness is poor, it is impossible to meet semicon industry demand.
Summary of the invention
The technical problem to be solved is to provide the preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block, can accurately control shoulder height, meets the requirement as standard sample, and low cost.
For solving above-mentioned technical problem, the technical solution used in the present invention is: the preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block, comprises the steps:
(1) use the silicon wafer of twin polishing as backing material, clean, be dried;
(2) oxide layer is grown at silicon wafer surface;
(3) at oxide layer surface resist coating, baking;
(4) by deep UV exposure, wherein mask plate is egative forme, and graphics field is transparent area;
(5) develop in aqueous slkali, remove the photoresist of transparent area, then toast;
(6) use reactive ion etching machine to perform etching, the oxide layer not having the stepped area of photoresist masking is etched away;
(7) using deep reaction ion etching machine engraving erosion silicon wafer, perform etching the silicon wafer of the stepped area not having photoresist masking, etching depth is less than the nominal height of standard sample to be prepared;
(8) acetone soln is used to remove photoresist;
(9) wet etching: the silicon wafer of the stepped area not having oxide layer to shelter is proceeded etching;Etching depth reaches nominal height requirement, and etching terminates, cleaning silicon chip;
(10) at silicon wafer surface splash-proofing sputtering metal protective layer, desired standard sample is prepared.
In step (1), first use acid electronic cleaning agent, then with deionized water ultrasonic cleaning 10-20 minute, then use alkalescence electronic cleaning agent, then with deionized water ultrasonic cleaning 10-20 minute, dry 10-20 minute afterwards;Wherein the order of acid electronic cleaning agent and alkalescence electronic cleaning agent is interchangeable.
In step (2), using thermal oxidation technology growth oxide layer, the thickness of oxide layer is 400 nm-500nm。
In step (2), thermal oxidation technology is dry-oxygen oxidation+wet-oxygen oxidation+dry-oxygen oxidation, the method that wherein wet oxygen uses hydrogen-oxygen synthesis.
In step (3), thickness 3 μm-4 μm of photoresist, toast 5-15 minute at a temperature of 100-150 DEG C.
In step (5), develop in NaOH solution, remove the photoresist of transparent area, then toast 5-15 minute at a temperature of 100-150 DEG C.
In step (6), etching gas is CHF3, etch rate is 120-160nm/min.
In step (7), etching depth is the nominal height μm that subtracts 5, and etching gas is SF6And C4F8, etch rate is set as 4 μm/min-5 μm/min.
In step (9), silicon wafer being placed in the Tetramethylammonium hydroxide corrosive liquid that concentration is 47%, perform etching the silicon wafer of the stepped area not having oxide layer to shelter, etch rate is 1 μm/min;Etching terminates to use ultrasonic cleaning silicon chip.
In step (10), coat of metal is crome metal, and thickness is 80 nm -100nm。
Use and have the beneficial effects that produced by technique scheme: the present invention uses silicon wafer as substrate, uses deep reaction ion etching technique to prepare step, when etching depth is close to nominal height, then uses wet-etching technology that bench floor is carried out smooth treatment.The shoulder height sample block prepared by this etching technics, can accurately control step height dimension, the surface roughness that can obtain again and step side perpendicularity, meets the requirement as standard sample.
Accompanying drawing explanation
Fig. 1 is the structure chart of step one of the present invention;
Fig. 2 is the structure chart of step 2 of the present invention;
Fig. 3 is the structure chart of step 3 of the present invention;
Fig. 4 is the structure chart of step 4 of the present invention;
Fig. 5 is the structure chart of step 5 of the present invention;
Fig. 6 is the structure chart of step 6 of the present invention;
Fig. 7 is the structure chart of step 7 of the present invention;
Fig. 8 is the structure chart of step 8 of the present invention;
Fig. 9 is the structure chart of step 9 of the present invention;
Figure 10 is the structure chart of step 10 of the present invention;
Figure 11 is sample block stability assessment datagram of the present invention;
Figure 12 is the schematic diagram figure of the silicon wafer prepared;
Figure 13 is the schematic diagram that the silicon wafer prepared is divided into standard sample;
Figure 14 is the structure chart of the single standard sample prepared;
In figure: 1, silicon wafer;2, oxide layer;3, photoresist;4, coat of metal.
Detailed description of the invention
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings.
The present invention proposes a kind of use semiconductor etching process, with silicon chip as substrate, the method preparing 10 μm-100 μm standard step height sample blocks: use silicon wafer as substrate, deep reaction ion etching (DRIE etches-Deep reactive ion etching) technique is used to prepare step, when etching depth is close to desired size, then use wet-etching technology that bench floor is carried out smooth treatment.The shoulder height sample block prepared by this etching technics, can accurately control step height dimension, and the surface roughness that simultaneously can obtain and step side perpendicularity meet the requirement as standard substance.
The preparation method of the present invention a kind of nominal height 10 μm-100 μm standard step height sample block, comprises the steps:
(1) use the silicon wafer 1 of twin polishing as backing material, clean, be dried;
(2) in silicon wafer 1 superficial growth oxide layer 2;
(3) at oxide layer 2 surface resist coating 3, baking;
(4) by deep UV exposure, wherein mask plate is egative forme, and graphics field is transparent area;
(5) develop in aqueous slkali, remove the photoresist 3 of transparent area, then toast;
(6) use reactive ion etching machine to perform etching, the oxide layer 2 of the stepped area not having photoresist 3 to shelter is etched away;
(7) using deep reaction ion etching machine engraving erosion silicon wafer 1, perform etching the silicon wafer 1 of the stepped area not having photoresist 3 to shelter, etching depth is less than the nominal height of standard sample to be prepared;
(8) acetone soln is used to remove photoresist 3;
(9) wet etching: the silicon wafer 1 of the stepped area not having oxide layer to shelter is proceeded etching;Etching depth reaches nominal height requirement, and etching terminates, cleaning silicon chip;
(10) at silicon wafer 1 surface splash-proofing sputtering metal protective layer 4, desired standard sample is prepared.
Below by concrete data parameters, the preparation process further illustrating the present invention is as follows:
(1) using the silicon wafer of twin polishing as backing material, the crystalline phase of silicon wafer is 100;Successively use two kinds of different electronic cleaning agents of soda acid, deionized water ultrasonic cleaning 15 minutes, afterwards drying 15 minutes, as shown in Figure 1.Wherein, the solution that acid electronic cleaning agent is made up of deionized water, 30% hydrogen peroxide, 25% ammonia 14:3:1 by volume.The solution that alkalescence electronic cleaning agent is made up of deionized water, 30% hydrogen peroxide, 36% hydrochloric acid 7:1:1 by volume, such combination can be washed different impurity off, clean up thoroughly;
(2) using the oxide layer 2 of thermal oxidation technology growth 460nm, concrete technology is dry-oxygen oxidation+wet-oxygen oxidation+dry-oxygen oxidation, the method that wherein wet oxygen uses hydrogen-oxygen synthesis, as shown in Figure 2;
(3) it is coated with 3 μm-4 μm photoresists 3 at silicon chip surface, baking 10 minutes at a temperature of 120 DEG C, as shown in Figure 3;
(4) by deep UV exposure, wherein mask plate is egative forme, and graphics field is transparent area, as shown in Figure 4;
(5) develop in NaOH solution, remove the photoresist of transparent area, then baking 10 minutes at a temperature of 120 DEG C, as shown in Figure 5;
(6) using reactive ion etching machine to perform etching, the oxide layer not having the stepped area of photoresist masking etched away, etching gas is CHF3, etch rate is 150nm/min, and etching speed is fast, as shown in Figure 6;
(7) use deep reaction ion etching machine etching silicon wafer, the silicon chip of the stepped area not having photoresist masking is performed etching, as it is shown in fig. 7, etching gas is SF6And C4F8, namely it is passed through SF simultaneously6And C4F8, SF6Primarily serve the effect of etching, C4F8Being polymer protective effect, etch rate is set as 4 μm/min-5 μm/min, and etching depth is the calibrated altitude of standard sample the to be prepared μm that subtracts 5;
(8) acetone soln is used to remove photoresist, as shown in Figure 8;
(9) wet etching: as it is shown in figure 9, silicon chip to be placed into the Tetramethylammonium hydroxide ((CH that concentration is 47%3)4N(OH)·5H2O) in corrosive liquid, the silicon chip of the stepped area not having oxide layer to shelter being proceeded etching, etching depth reaches nominal height, and etch rate is 1 μm/min;Etching terminates to use ultrasonic cleaning silicon chip;
(10) at silicon chip surface splash-proofing sputtering metal chromium, sputtering thickness is 90nm, as shown in Figure 10.
The silicon wafer prepared is as shown in figure 12, in order to easy to use, after having prepared, silicon wafer is carried out scribing arrangement, the silicon wafer of one six cun is divided into the square-like block as shown in fig. 13 that of more than 100 10mm × 10mm, then it is fixed on the quartzy pedestal of 25mm × 25mm × 3mm, as shown in figure 14.Same silicon wafer can prepare more than 100 the identical sample block of shoulder height, namely shoulder height has identical structure, identical size, identical depth of groove.
Wherein, the height of step is controlled by etching technics, and the length of etch period determines the height of step.A series of sample blocks of differing heights to use multiple wafer to prepare, and by parameters such as the times that regulation etches, the time that each silicon wafer etching is different, thus can prepare the sample block of a series of differing heights.After sample block etching terminates, use step instrument that the shoulder height of sample block is measured, controlled the concrete height of step by measurement result.If the sample block of preparation is not reaching to expection height, then the parameter adjusting etching is needed again to prepare.
Height through wet method backward step has reached desired depth.The effect of splash-proofing sputtering metal chromium has two: one to be to protect sample block; after wet method terminates; the bottom surface of the step obtained is silicon; upper surface is silicon dioxide, and silicon is oxidizable, the most exposed in atmosphere; the silicon generation oxidation reaction of bottom surface; to gradually change the height of step, as standard substance, the stability of sample block will can not get ensureing;Two scope of applications being to increase sample block, step instrument includes contact pin type and optical profile type two kinds, optics step instrument measurement has certain limitation, the semipermeable membranes such as silicon dioxide cannot be measured, the sample block of preparation would be unavailable for the calibration of optics step instrument, after sputtering layer of metal chromium, avoid the limitation that optics step instrument is measured, extend the range of sample block.Due to coat of metal be on sample block uniform fold one layer as shown in Figure 10, namely the step upper and lower surface of sample block increases identical height, therefore after splash-proofing sputtering metal chromium, does not interferes with the shoulder height of sample block.
After prepared by sample block, using white light interferometer or nano-measuring machine with laser measurement function to calibrate sample block, both instruments can be traceable to optical maser wavelength, illustrates that the measured value of instrument is accurately.The nominal height such as preparing sample block is 10 μm, and the result of calibration is 9.95 μm, then then step instrument is calibrated by 9.95 μm as standard value.This sample block is measured, it is assumed that the result that step instrument is measured is 10.50 μm, then the step instrument measurement error when measuring the step about height 10 μm is 10.50 μm-9.95 μm=0.55 μm with step instrument.May determine that step instrument can meet the requirement of daily measurement by this error amount.
Use the present invention, a series of shoulder height can be prepared, such as 10 μm, 20 μm, 50 μm, 100 μm.Different height can also be designed for the specific requirement of step instrument.
Wherein, wet etching is a chemical reaction process purely, it is to utilize the chemical reaction between solution and pre-etachable material to remove the part sheltered for masked membrane material and reach to etch purpose, its shortcoming is: bore quarter serious, poor to the controlling of figure, the perpendicularity of the step i.e. obtained is poor, the step sample block directly using wet etching to prepare can not meet the requirement as standard substance, no longer carries out description of test at this.
The present invention is as a example by the print that nominal height is 50 μm, design two kinds of etch approach: DRIE etchings and DRIE etching+wet etching, wherein DRIE etching+wet etching is first to use DRIE etching, make etching depth close to step desired size namely the nominal height of standard sample that needs preparation, then use wet etching that the bottom surface of step is processed.The surface roughness of the print relatively completed.After having etched, the sample block roughness made is measured by the white light interferometer using Brooker company model to be GT-X8, and measurement result is as shown in table 1.
Table 1 be nominal height be the roughness measurement results of 50 μm prints
Parameter DRIE etches DRIE etching+wet etching
Surface roughness Ra/nm 11.4 6.2
Can be seen that the surface quality using DRIE etching+wet etching of the present invention to obtain is better than DRIE and etches the surface quality obtained from experimental result.
The stability of the sample block using DRIE etching+wet etching method to prepare 50 μm is monitored, in 12 months, step sample block has been carried out 12 stability assessments.As shown in figure 11, the result of appraisal show that the stability of sample block is (49.7468 ± 0.0166) μm to experimental result, and sample block does not occur significantly to change, and height value has preferable stability.

Claims (10)

1. the preparation method of nominal height 10 μm-100 μm standard step height sample block, it is characterised in that comprise the steps:
(1) use the silicon wafer (1) of twin polishing as backing material, clean, be dried;
(2) in silicon wafer (1) superficial growth oxide layer (2);
(3) on oxide layer (2) surface resist coating (3), baking;
(4) by deep UV exposure, wherein mask plate is egative forme, and graphics field is transparent area;
(5) develop in aqueous slkali, remove the photoresist (3) of transparent area, then toast;
(6) use reactive ion etching machine to perform etching, the oxide layer (2) of the stepped area not having photoresist (3) to shelter is etched away;
(7) using deep reaction ion etching machine engraving erosion silicon wafer (1), perform etching the silicon wafer (1) of the stepped area not having photoresist (3) to shelter, etching depth is less than the nominal height of standard sample to be prepared;
(8) acetone soln is used to remove photoresist (3);
(9) wet etching: the silicon wafer (1) of the stepped area not having oxide layer to shelter is proceeded etching, and etching depth reaches nominal height requirement, and etching terminates, cleaning silicon chip;
(10) on silicon wafer (1) surface splash-proofing sputtering metal protective layer (4), desired standard sample is prepared.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterized in that, in step (1), first use acid electronic cleaning agent, again with deionized water ultrasonic cleaning 10-20 minute, then use alkalescence electronic cleaning agent, then with deionized water ultrasonic cleaning 10-20 minute, dry 10-20 minute afterwards;Wherein the order of acid electronic cleaning agent and alkalescence electronic cleaning agent is interchangeable.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterised in that in step (2), uses thermal oxidation technology growth oxide layer (2), and the thickness of oxide layer (2) is 400 nm-500nm.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 3, it is characterized in that, in step (2), thermal oxidation technology is dry-oxygen oxidation+wet-oxygen oxidation+dry-oxygen oxidation, the method that wherein wet oxygen uses hydrogen-oxygen synthesis.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterised in that in step (3), thickness 3 μm-4 μm of photoresist (3), toast 5-15 minute at a temperature of 100-150 DEG C.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterized in that, in step (5), develop in NaOH solution, remove the photoresist of transparent area, then toast 5-15 minute at a temperature of 100-150 DEG C.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterised in that in step (6), etching gas is CHF3, and etch rate is 120-160nm/min.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterized in that, in step (7), etching depth is the nominal height μm that subtracts 5, etching gas is SF6 and C4F8, and etch rate is set as 4 μm/min-5 μm/min.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterized in that, in step (9), silicon wafer (1) is placed in the Tetramethylammonium hydroxide corrosive liquid that concentration is 47%, performing etching the silicon wafer (1) of the stepped area not having oxide layer (2) to shelter, etch rate is 1 μm/min;Etching terminates to use ultrasonic cleaning silicon chip.
The preparation method of a kind of nominal height 10 μm-100 μm standard step height sample block the most according to claim 1, it is characterised in that in step (10), coat of metal (4) is crome metal, and thickness is 80 nm-100nm.
CN201610578470.5A 2016-07-21 2016-07-21 preparation method of step height standard sample block with nominal height of 10-100 mu m Active CN106017385B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610578470.5A CN106017385B (en) 2016-07-21 2016-07-21 preparation method of step height standard sample block with nominal height of 10-100 mu m

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610578470.5A CN106017385B (en) 2016-07-21 2016-07-21 preparation method of step height standard sample block with nominal height of 10-100 mu m

Publications (2)

Publication Number Publication Date
CN106017385A true CN106017385A (en) 2016-10-12
CN106017385B CN106017385B (en) 2019-12-17

Family

ID=57117211

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610578470.5A Active CN106017385B (en) 2016-07-21 2016-07-21 preparation method of step height standard sample block with nominal height of 10-100 mu m

Country Status (1)

Country Link
CN (1) CN106017385B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106931916A (en) * 2017-03-07 2017-07-07 中国计量大学 A kind of micro-nano step standard jig and its tracking method
CN108182006A (en) * 2016-12-08 2018-06-19 佛山市顺德区美的电热电器制造有限公司 A kind of anti-microbial touch panel and preparation method thereof and equipment of cooking
CN109444472A (en) * 2018-12-19 2019-03-08 中国电子科技集团公司第十三研究所 Scanning electron microscope alignment pattern print and preparation method
CN109755147A (en) * 2018-11-26 2019-05-14 北京铂阳顶荣光伏科技有限公司 Membrane photovoltaic component test method and membrane photovoltaic component
CN109855572A (en) * 2018-12-25 2019-06-07 中国电子科技集团公司第十三研究所 For calibrating the line-spacing template and preparation method of optical profilometer roughness
CN111024016A (en) * 2019-12-04 2020-04-17 中国电子科技集团公司第十三研究所 Film thickness sample and preparation method of film thickness sample
CN111024017A (en) * 2019-12-04 2020-04-17 中国电子科技集团公司第十三研究所 Film thickness sample and preparation method of film thickness sample
CN112158794A (en) * 2020-09-04 2021-01-01 杭州探真纳米科技有限公司 Method for preparing atomic force microscope probe stepped substrate by adopting plasma etching
CN112490115A (en) * 2020-12-01 2021-03-12 苏州大学 Transparent flexible monocrystalline silicon material and preparation method thereof
CN114543688A (en) * 2022-01-17 2022-05-27 中国电子科技集团公司第十三研究所 Step height standard sample block, preparation method and white light interferometer calibration method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1920476A (en) * 2006-06-30 2007-02-28 西安交通大学 Nano multi-step height sample plate and its preparation
CN102707568A (en) * 2012-06-08 2012-10-03 北京工业大学 Photo-etching method of bottom surface of multi-step apparatus structure
CN103132039A (en) * 2013-02-28 2013-06-05 广东省计量科学研究院 Metal film preparation method
CN103681306A (en) * 2013-12-30 2014-03-26 国家电网公司 Etching method of nitrogen, oxygen and silicon of gentle and smooth sidewall morphology
CN104101736A (en) * 2014-08-11 2014-10-15 常州碳维纳米科技有限公司 Preparation method for nanoscale step standard sample applied to calibration
WO2014185818A1 (en) * 2013-05-13 2014-11-20 Gurevich Aleksei Sergeevich Ellipsometer
CN105737879A (en) * 2016-03-01 2016-07-06 中国电子科技集团公司第十三研究所 Micron grade raster calibration sample wafer with step height

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1920476A (en) * 2006-06-30 2007-02-28 西安交通大学 Nano multi-step height sample plate and its preparation
CN102707568A (en) * 2012-06-08 2012-10-03 北京工业大学 Photo-etching method of bottom surface of multi-step apparatus structure
CN103132039A (en) * 2013-02-28 2013-06-05 广东省计量科学研究院 Metal film preparation method
WO2014185818A1 (en) * 2013-05-13 2014-11-20 Gurevich Aleksei Sergeevich Ellipsometer
CN103681306A (en) * 2013-12-30 2014-03-26 国家电网公司 Etching method of nitrogen, oxygen and silicon of gentle and smooth sidewall morphology
CN104101736A (en) * 2014-08-11 2014-10-15 常州碳维纳米科技有限公司 Preparation method for nanoscale step standard sample applied to calibration
CN105737879A (en) * 2016-03-01 2016-07-06 中国电子科技集团公司第十三研究所 Micron grade raster calibration sample wafer with step height

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
施敏: "《半导体制造工艺基础》", 30 April 2007 *
雷李华等: "纳米台阶标准样板的制备和表征", 《微纳电子技术》 *
龚勇清等: "《激光原理与全息技术》", 31 August 2010 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108182006A (en) * 2016-12-08 2018-06-19 佛山市顺德区美的电热电器制造有限公司 A kind of anti-microbial touch panel and preparation method thereof and equipment of cooking
CN106931916A (en) * 2017-03-07 2017-07-07 中国计量大学 A kind of micro-nano step standard jig and its tracking method
CN109755147A (en) * 2018-11-26 2019-05-14 北京铂阳顶荣光伏科技有限公司 Membrane photovoltaic component test method and membrane photovoltaic component
CN109444472A (en) * 2018-12-19 2019-03-08 中国电子科技集团公司第十三研究所 Scanning electron microscope alignment pattern print and preparation method
CN109855572A (en) * 2018-12-25 2019-06-07 中国电子科技集团公司第十三研究所 For calibrating the line-spacing template and preparation method of optical profilometer roughness
CN111024016A (en) * 2019-12-04 2020-04-17 中国电子科技集团公司第十三研究所 Film thickness sample and preparation method of film thickness sample
CN111024017A (en) * 2019-12-04 2020-04-17 中国电子科技集团公司第十三研究所 Film thickness sample and preparation method of film thickness sample
CN112158794A (en) * 2020-09-04 2021-01-01 杭州探真纳米科技有限公司 Method for preparing atomic force microscope probe stepped substrate by adopting plasma etching
CN112158794B (en) * 2020-09-04 2024-03-22 杭州探真纳米科技有限公司 Method for preparing atomic force microscope probe stepped substrate by adopting plasma etching
CN112490115A (en) * 2020-12-01 2021-03-12 苏州大学 Transparent flexible monocrystalline silicon material and preparation method thereof
CN114543688A (en) * 2022-01-17 2022-05-27 中国电子科技集团公司第十三研究所 Step height standard sample block, preparation method and white light interferometer calibration method

Also Published As

Publication number Publication date
CN106017385B (en) 2019-12-17

Similar Documents

Publication Publication Date Title
CN106017385A (en) Preparation method of step height standard sample block with nominal height ranging from 10 mu m to 100 mu m
US5534359A (en) Calibration standard for 2-D and 3-D profilometry in the sub-nanometer range and method of producing it
TW200305250A (en) Methodology for repeatable post etch cd in a production tool
JPH034341B2 (en)
CN107993956B (en) Preparation method of line spacing standard sample wafer
TW201533838A (en) Substrate holder, support table for a lithographic apparatus, lithographic apparatus and device manufacturing method
CN102707568B (en) Photo-etching method of bottom surface of multi-step apparatus structure
US20050252282A1 (en) Methods of fabricating structures for characterizing tip shape of scanning probe microscope probes and structures fabricated thereby
Sharstniou et al. Roughness suppression in electrochemical nanoimprinting of Si for applications in silicon photonics
CN111128964B (en) Nanometer-sized line spacing standard sample wafer and preparation method thereof
CN108319107A (en) A kind of production method of nano-imprint stamp
CN109855572A (en) For calibrating the line-spacing template and preparation method of optical profilometer roughness
CN111137846A (en) Preparation method of micron-level step height standard sample block
JP2010271228A (en) Reference member for calibrating dimension of electronic microscope device, method of manufacturing the same, and method of calibrating electronic microscope device using the same
US6238936B1 (en) Method of using critical dimension mapping to qualify a new integrated circuit fabrication etch process
JP2005064117A (en) Method, device, and mask for near-field exposure
CN103303860A (en) Method for generating 0-50nm of random-height nano step on surface of Si
CN111573616B (en) Composite high aspect ratio groove standard template and preparation method thereof
Sun Micromachining based on Porous silicon
CN108892101A (en) Silicon face nanoprocessing method based on friction induction TMAH selective etch
CN111693003A (en) Wafer-level nanoscale measurement standard device and manufacturing method thereof
CN103258758A (en) Monitoring method and control wafer for particles in film thickness measuring machine platform
CN109399558A (en) Gallium arsenide surface nanoprocessing method based on photochemistry assisted selective etching
US20160064889A1 (en) Full polymer microresonators
CN102789017B (en) Method for manufacturing multistage micro-mirror through inversely adjusting thick film

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant