CN106017385B - preparation method of step height standard sample block with nominal height of 10-100 mu m - Google Patents

preparation method of step height standard sample block with nominal height of 10-100 mu m Download PDF

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CN106017385B
CN106017385B CN201610578470.5A CN201610578470A CN106017385B CN 106017385 B CN106017385 B CN 106017385B CN 201610578470 A CN201610578470 A CN 201610578470A CN 106017385 B CN106017385 B CN 106017385B
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etching
silicon wafer
height
sample block
photoresist
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CN106017385A (en
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冯亚南
李锁印
韩志国
吴爱华
赵琳
许晓青
梁法国
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CETC 13 Research Institute
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/02—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness
    • G01B21/04—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness by measuring coordinates of points
    • G01B21/042—Calibration or calibration artifacts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/02—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness
    • G01B21/08—Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness for measuring thickness
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Sampling And Sample Adjustment (AREA)
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

the invention discloses a preparation method of a step height standard sample block with a nominal height of 10-100 mu m, belonging to the technical field of step instrument calibration. The invention comprises the following steps: adopting a silicon wafer with double-sided polishing as a substrate material; growing an oxide layer on the surface of the silicon wafer; coating photoresist on the surface of the oxide layer; exposing, wherein the mask is a negative plate, and the pattern area is a light-transmitting area; removing the photoresist in the light-transmitting area; etching by using a reactive ion etching machine, and etching the oxide layer of the step region without the photoresist mask; etching the silicon wafer by using a deep reactive ion etching machine, and etching the silicon wafer in the step area without the masking of the photoresist, wherein the etching depth is less than the nominal height of the standard sample block to be prepared; removing the photoresist; wet etching is carried out, and the etching depth meets the requirement of the nominal height; and sputtering a metal protective layer on the surface of the silicon wafer to prepare the required standard sample block. The invention can accurately control the height of the step, meets the requirement of serving as a standard sample block and has low cost.

Description

Preparation method of step height standard sample block with nominal height of 10-100 mu m
Technical Field
The invention belongs to the technical field of step instrument calibration, and particularly relates to a preparation method of a step height standard sample block with a nominal height of 10-100 micrometers.
background
the integrated circuit and the Micro Electro Mechanical System (MEMS) relate to the test problem of a large number of step heights in the manufacturing process, and the accurate measurement of step parameters is an important means for ensuring the quality of devices. At present, a step meter is mainly used for measuring the step height in the semiconductor industry, wherein the step meter mainly comprises the following measuring methods: contact measurement and optical measurement. Regardless of the type of the step meter, the measurement parameters are height values of the sample in the vertical direction. The investigation result shows that: china has thousands of measuring instruments for various steps, and the instruments are widely applied to scientific research and production units and have high popularization rate. In order to ensure that the step meter obtains accurate data in the full-scale range, a series of step height standard sample blocks consistent with the use range of the step meter are used for calibrating the step meter.
The foreign VLSI has a step height standard sample block with micron magnitude, a mask is used as a substrate, and a dry etching process is adopted to prepare the step standard sample block. However, the processing technology for preparing the step sample block by using the mask as the substrate is complex and high in cost. The method has the advantages that no micron-level step height sample block exists in China, steps with the height range of 10-100 mu m are obtained by grinding two measuring blocks on a flat crystal, and the obtained steps are low in accuracy, discontinuous and poor in roughness, and cannot meet the requirements of the semiconductor industry.
Disclosure of Invention
The invention aims to provide a method for preparing a step height standard sample block with the nominal height of 10-100 mu m, which can accurately control the step height, meet the requirements of serving as the standard sample block and has low cost.
in order to solve the technical problems, the technical scheme adopted by the invention is as follows: a method for preparing a step height standard block with a nominal height of 10-100 μm comprises the following steps:
(1) silicon wafers with two polished surfaces are used as substrate materials, and the substrate materials are cleaned and dried;
(2) Growing an oxide layer on the surface of the silicon wafer;
(3) coating photoresist on the surface of the oxide layer, and baking;
(4) exposing by deep ultraviolet light, wherein the mask is a negative plate, and the graphic area is a light-transmitting area;
(5) Developing in alkali solution to remove the photoresist in the light-transmitting area, and then baking;
(6) Etching by using a reactive ion etching machine, and etching the oxide layer of the step region without the photoresist mask;
(7) Etching the silicon wafer by using a deep reactive ion etching machine, and etching the silicon wafer in the step area without the masking of the photoresist, wherein the etching depth is less than the nominal height of the standard sample block to be prepared;
(8) Removing the photoresist by using an acetone solution;
(9) Wet etching: continuously etching the silicon wafer in the step area without the masking of the oxide layer; when the etching depth reaches the nominal height requirement, cleaning the silicon wafer after the etching is finished;
(10) and sputtering a metal protective layer on the surface of the silicon wafer to prepare the required standard sample block.
In the step (1), firstly, using an acidic electronic cleaning agent, then ultrasonically cleaning for 10-20 minutes by using deionized water, then using an alkaline electronic cleaning agent, ultrasonically cleaning for 10-20 minutes by using deionized water, and then spin-drying for 10-20 minutes; wherein the order of the acidic electronic cleaning agent and the alkaline electronic cleaning agent can be interchanged.
in the step (2), an oxide layer is grown by using a thermal oxidation process, wherein the thickness of the oxide layer is 400nm-500 nm.
in the step (2), the thermal oxidation process comprises dry oxygen oxidation, wet oxygen oxidation and dry oxygen oxidation, wherein the wet oxygen is synthesized by hydrogen and oxygen.
In the step (3), the photoresist is 3 μm-4 μm thick and baked at 100-150 deg.C for 5-15 minutes.
In the step (5), developing in NaOH solution to remove the photoresist in the light-transmitting region, and then baking at 100-150 ℃ for 5-15 minutes.
In the step (6), the etching gas is CHF3The etching rate is 120-160 nm/min.
In the step (7), the etching depth is the nominal height minus 5 μm, and the etching gas is SF6and C4F8the etching rate is set to 4 μm/min to 5 μm/min.
In the step (9), the silicon wafer is placed into a tetramethyl ammonium hydroxide corrosive liquid with the concentration of 47%, and the silicon wafer in the step area without the masking of the oxide layer is etched, wherein the etching rate is 1 mu m/min; and cleaning the silicon wafer by using ultrasonic after the etching is finished.
in the step (10), the metal protective layer is chromium metal with a thickness of 80nm-100 nm.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the invention uses silicon wafer as substrate, uses deep reactive ion etching process to prepare step, when the etching depth is close to nominal height, uses wet etching process to smooth the bottom surface of step. The step height sample block prepared by the etching process can accurately control the height dimension of the step, can obtain good surface roughness and step side surface verticality, and meets the requirements of serving as a standard sample block.
Drawings
FIG. 1 is a block diagram of a first step of the present invention;
FIG. 2 is a block diagram of step two of the present invention;
FIG. 3 is a block diagram of step three of the present invention;
FIG. 4 is a block diagram of step four of the present invention;
FIG. 5 is a block diagram of step five of the present invention;
FIG. 6 is a block diagram of step six of the present invention;
FIG. 7 is a block diagram of step seven of the present invention;
FIG. 8 is a block diagram of step eight of the present invention;
FIG. 9 is a block diagram of step nine of the present invention;
FIG. 10 is a block diagram of step ten of the present invention;
FIG. 11 is a graph of sample stability assessment data in accordance with the present invention;
FIG. 12 is a schematic view of a prepared silicon wafer;
FIG. 13 is a schematic illustration of a prepared silicon wafer divided into standard sample blocks;
FIG. 14 is a block diagram of a prepared single master piece;
in the figure: 1. a silicon wafer; 2. an oxide layer; 3. photoresist; 4. and a metal protective layer.
Detailed Description
the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention provides a method for preparing a standard sample block with step height of 10-100 mu m by using a semiconductor etching process and taking a silicon wafer as a substrate, which comprises the following steps: the method comprises the steps of using a silicon wafer as a substrate, preparing the steps by adopting a deep reactive ion etching (DRIE etching-deep reactive ion etching) process, and smoothing the bottom surfaces of the steps by adopting a wet etching process when the etching depth is close to an expected size. The step height sample block prepared by the etching process can accurately control the height dimension of the step, can obtain good surface roughness and step side surface verticality, and meets the requirements of serving as standard substances.
the invention relates to a method for preparing a step height standard sample block with a nominal height of 10-100 mu m, which comprises the following steps:
(1) Cleaning and drying a silicon wafer 1 with two polished surfaces as a substrate material;
(2) growing an oxide layer 2 on the surface of a silicon wafer 1;
(3) coating photoresist 3 on the surface of the oxide layer 2, and baking;
(4) Exposing by deep ultraviolet light, wherein the mask is a negative plate, and the graphic area is a light-transmitting area;
(5) Developing in alkali solution to remove the photoresist 3 in the light transmission area, and then baking;
(6) etching by using a reactive ion etcher, and etching off the oxide layer 2 of the step region without being masked by the photoresist 3;
(7) Etching the silicon wafer 1 by using a deep reactive ion etching machine, and etching the silicon wafer 1 in a step area without masking by the photoresist 3, wherein the etching depth is less than the nominal height of a standard sample block to be prepared;
(8) removing the photoresist 3 by using an acetone solution;
(9) wet etching: continuously etching the silicon wafer 1 in the step area without the masking of the oxide layer; when the etching depth reaches the nominal height requirement, cleaning the silicon wafer after the etching is finished;
(10) and sputtering a metal protective layer 4 on the surface of the silicon wafer 1 to prepare the required standard sample block.
the preparation process of the present invention is further illustrated below with specific data parameters as follows:
(1) A silicon wafer with double-sided polishing is used as a substrate material, and the crystalline phase of the silicon wafer is 100; two different electronic cleaning agents, namely acid and alkali, and deionized water are sequentially used for ultrasonic cleaning for 15 minutes, and then are dried for 15 minutes, as shown in figure 1. The acidic electronic cleaning agent is a solution composed of deionized water, 30% of hydrogen peroxide and 25% of ammonia water according to the volume ratio of 14:3: 1. The alkaline electronic cleaning agent is a solution consisting of deionized water, 30% hydrogen peroxide and 36% hydrochloric acid according to the volume ratio of 7:1:1, and different impurities can be washed off by the combination, so that the cleaning is thorough;
(2) Growing a 460nm oxide layer 2 by using a thermal oxidation process, specifically dry oxygen oxidation, wet oxygen oxidation and dry oxygen oxidation, wherein the wet oxygen is synthesized by using hydrogen and oxygen, as shown in fig. 2;
(3) Coating a photoresist 3 with the thickness of 3-4 μm on the surface of the silicon wafer, and baking at the temperature of 120 ℃ for 10 minutes, as shown in figure 3;
(4) exposing by deep ultraviolet light, wherein the mask is a negative plate, and the pattern area is a light-transmitting area, as shown in FIG. 4;
(5) developing in NaOH solution to remove the photoresist in the light-transmitting area, and then baking at 120 deg.C for 10 min, as shown in FIG. 5;
(6) etching with a reactive ion etcher to remove the oxide layer in the step region without the masking of photoresist, wherein the etching gas is CHF3The etching rate is 150nm/min, and the etching speed is high, as shown in FIG. 6;
(7) Etching the silicon wafer by using a deep reactive ion etcher to etch the silicon wafer in the step region without the masking of the photoresist, wherein the etching gas is SF as shown in FIG. 76And C4F8I.e. simultaneously introducing SF6and C4F8，SF6Mainly plays a role of etching, C4F8is to startthe polymer protection function, the etching rate is set to be 4-5 mu m/min, and the etching depth is the calibrated height of the standard sample block to be prepared minus 5 mu m;
(8) removing the photoresist using an acetone solution, as shown in fig. 8;
(9) Wet etching: as shown in FIG. 9, the silicon wafer was set to a concentration of 47% tetramethylammonium hydroxide ((CH)3)4N(OH)·5H2O), continuously etching the silicon wafer in the step area without the masking of the oxide layer in the etching solution, wherein the etching depth reaches the nominal height, and the etching rate is 1 mu m/min; cleaning the silicon wafer by using ultrasonic after etching;
(10) And sputtering chromium metal on the surface of the silicon wafer to the sputtering thickness of 90nm, as shown in FIG. 10.
The prepared silicon wafer is shown in fig. 12, and for convenience of use, after the preparation is completed, the silicon wafer is subjected to dicing and sorting, and a six-inch silicon wafer is diced into one hundred square blocks of 10mm × 10mm as shown in fig. 13, and then fixed on a quartz base of 25mm × 25mm × 3mm as shown in fig. 14. More than 100 sample blocks with the same step height can be prepared on the same silicon wafer, namely the step heights have the same structure, the same size and the same groove depth.
The height of the step is controlled by the etching process, and the length of the etching time determines the height of the step. A series of sample blocks with different heights are prepared by using a plurality of wafers, and each silicon wafer is etched for different time by adjusting parameters such as etching time, so that a series of sample blocks with different heights can be prepared. And after the etching of the sample block is finished, measuring the step height of the sample block by using a step meter, and controlling the specific height of the step through a measurement result. If the prepared sample block does not reach the expected height, the etching parameters need to be adjusted for preparing again.
the height of the step reaches the expected depth after the wet process. The effect of sputtering metallic chromium is two: firstly, protecting a sample block, wherein after the wet method is finished, the bottom surface of the obtained step is silicon, the upper surface of the step is silicon dioxide, the silicon is easy to oxidize and is directly exposed in air, the silicon on the bottom surface undergoes oxidation reaction, the height of the step is gradually changed to serve as a standard substance, and the stability of the sample block cannot be guaranteed; and secondly, the application range of the sample block is enlarged, the step instrument comprises a contact pin type step instrument and an optical type step instrument, the measurement of the optical step instrument has certain limitation, the semi-permeable membranes such as silicon dioxide and the like cannot be measured, the prepared sample block cannot be used for the calibration of the optical step instrument, the limitation of the measurement of the optical step instrument is avoided after a layer of metal chromium is sputtered, and the application range of the sample block is expanded. As the metal protective layer is formed by uniformly covering a layer on the sample block as shown in figure 10, namely the upper surface and the lower surface of the step of the sample block are increased by the same height, the step height of the sample block cannot be influenced after metal chromium is sputtered.
After the sample block is prepared, the sample block is calibrated by using a white light interferometer or a nanometer measuring machine with a laser measuring function, and the two instruments can trace the laser wavelength, so that the measured value of the instrument is accurate. For example, if the nominal height of the prepared sample block is 10 μm and the calibration result is 9.95 μm, the step meter is calibrated by using 9.95 μm as the standard value. This block was measured with a step meter, and assuming that the result of the step meter measurement was 10.50 μm, the measurement error of the step meter when measuring a step of about 10 μm in height was 10.50 μm to 9.95 μm =0.55 μm. The error value can be used for judging that the step instrument can not meet the requirement of daily measurement.
With the present invention, a range of step heights can be prepared, such as 10 μm, 20 μm, 50 μm, 100 μm. Different heights can be designed according to the specific requirements of the step meter.
the wet etching is a pure chemical reaction process, and uses a chemical reaction between a solution and a pre-etching material to remove a part masked by a masking film material to achieve the purpose of etching, and has the following disadvantages: the drilling and etching are serious, the controllability of the pattern is poor, namely the verticality of the obtained step is poor, the step sample block prepared by directly using wet etching cannot meet the requirement of serving as a standard substance, and experimental explanation is not carried out.
the invention takes a sample wafer with the nominal height of 50 mu m as an example, and designs two etching schemes: DRIE etching, DRIE etching and wet etching, wherein the DRIE etching and the wet etching are firstly carried out by adopting the DRIE etching, so that the etching depth is close to the expected size of the step, namely the nominal height of the standard sample block to be prepared, and then the wet etching is adopted to treat the bottom surface of the step. The surface roughness of the fabricated coupons was compared. After the etching was completed, the roughness of the produced sample piece was measured using a white light interferometer of model GT-X8 of Bruker, and the measurement results are shown in Table 1.
Table 1 shows the results of roughness measurements on a sample wafer having a nominal height of 50 μm
Parameter(s) DRIE etching DRIE etching and wet etching
Surface roughness Ra/nm 11.4 6.2
The experimental results show that the surface quality obtained by adopting the DRIE etching and the wet etching of the invention is superior to that obtained by the DRIE etching.
The stability of the sample block with the size of 50 micrometers prepared by using the DRIE etching and wet etching method is monitored, and the stability of the step sample block is evaluated for 12 times within 12 months. The experimental results are shown in fig. 11, and the examination results show that the sample block has the stability of (49.7468 ± 0.0166) μm, the sample block has no significant change, and the height value has better stability.

Claims (9)

1. a method for preparing a step height standard sample block with a nominal height of 10-100 μm is characterized by comprising the following steps:
(1) a silicon wafer (1) with two polished surfaces is used as a substrate material, and is cleaned and dried;
(2) growing an oxide layer (2) on the surface of a silicon wafer (1);
(3) Coating photoresist (3) on the surface of the oxide layer (2), and baking;
(4) Exposing by deep ultraviolet light, wherein the mask is a negative plate, and the graphic area is a light-transmitting area;
(5) developing in alkali solution, removing the photoresist (3) in the light transmission area, and then baking;
(6) Etching by using a reactive ion etcher, and etching off the oxide layer (2) of the step region without being masked by the photoresist (3);
(7) Etching the silicon wafer (1) by using a deep reactive ion etching machine, and etching the silicon wafer (1) in the step area without being masked by the photoresist (3), wherein the etching depth is less than the nominal height of the standard sample block to be prepared;
(8) removing the photoresist (3) by using an acetone solution;
(9) Wet etching: continuously etching the silicon wafer (1) in the step area without the oxide layer masking, wherein the etching depth meets the requirement of the nominal height, and cleaning the silicon wafer after the etching is finished;
(10) sputtering a metal protective layer (4) on the surface of a silicon wafer (1) to prepare a required standard sample block;
In the step (2), the oxide layer (2) is grown by using a thermal oxidation process, and the thickness of the oxide layer (2) is 400nm-500 nm.
2. The method for preparing the step height standard sample block with the nominal height of 10-100 μm as claimed in claim 1, wherein in the step (1), firstly, an acidic electronic cleaning agent is used, then, deionized water is used for ultrasonic cleaning for 10-20 minutes, then, an alkaline electronic cleaning agent is used, then, deionized water is used for ultrasonic cleaning for 10-20 minutes, and then, the step is dried for 10-20 minutes; or firstly using an alkaline electronic cleaning agent, then using deionized water to carry out ultrasonic cleaning for 10-20 minutes, then using an acidic electronic cleaning agent, then using deionized water to carry out ultrasonic cleaning for 10-20 minutes, and then carrying out spin-drying for 10-20 minutes.
3. The method for preparing the step height standard sample block with the nominal height of 10-100 μm according to claim 1, wherein in the step (2), the thermal oxidation process is dry oxygen oxidation + wet oxygen oxidation + dry oxygen oxidation, wherein the wet oxygen is a hydrogen-oxygen synthesis method.
4. the method as claimed in claim 1, wherein in step (3), the photoresist (3) is 3 μm-4 μm thick and baked at 100-150 ℃ for 5-15 minutes.
5. The method as claimed in claim 1, wherein the step height standard block with a nominal height of 10 μm-100 μm is developed in NaOH solution to remove the photoresist in the light-transmitting region, and then baked at 100-150 ℃ for 5-15 minutes in step (5).
6. The method as claimed in claim 1, wherein in step (6), the etching gas is CHF3, and the etching rate is 160nm/min and 120 nm/min.
7. the method of claim 1, wherein in step (7), the etching depth is reduced by 5 μm from the nominal height, the etching gas is SF6 and C4F8, and the etching rate is set to 4 μm/min to 5 μm/min.
8. the method for preparing the step height standard sample block with the nominal height of 10-100 μm as claimed in claim 1, wherein in the step (9), the silicon wafer (1) is placed into a tetramethylammonium hydroxide etching solution with the concentration of 47%, and the silicon wafer (1) in the step area without being masked by the oxide layer (2) is etched at the etching rate of 1 μm/min; and cleaning the silicon wafer by using ultrasonic after the etching is finished.
9. The method for preparing a step height standard block with a nominal height of 10-100 μm as claimed in claim 1, wherein in step (10), the metal protective layer (4) is metallic chromium with a thickness of 80-100 nm.
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