CN107993956B - Preparation method of line spacing standard sample wafer - Google Patents
Preparation method of line spacing standard sample wafer Download PDFInfo
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- CN107993956B CN107993956B CN201711223205.6A CN201711223205A CN107993956B CN 107993956 B CN107993956 B CN 107993956B CN 201711223205 A CN201711223205 A CN 201711223205A CN 107993956 B CN107993956 B CN 107993956B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The embodiment of the invention provides a preparation method of a line spacing standard sample wafer, and relates to the technical field of semiconductors. The method comprises the following steps: carrying out first pretreatment on a substrate; growing a silicon nitride layer on the upper surface of the first region of the substrate; etching the silicon nitride layer to the substrate, and forming a plurality of silicon nitride grating structures and/or silicon nitride grating structures with different cycle sizes in the first region; subjecting the substrate to a second pretreatment; growing a silicon dioxide layer on the upper surface of the second area of the substrate; etching the silicon dioxide layer to the substrate, and forming a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with different periodic sizes in the second area; and growing a metal layer on the upper surface of the second area. The invention can manufacture the line spacing standard sample wafer meeting the requirements of various measuring instruments by one-time processing technology, and can reduce the cost.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a line spacing standard sample wafer.
Background
The test problem of a large number of line sizes is involved in the manufacturing process of integrated circuits and microwave power devices, and the accurate measurement of line width parameters is an important means for ensuring the quality of the devices. At present, micro-nano line width dimension measuring instruments in the microelectronic industry comprise line width measuring instruments, scanning electron microscopes, atomic force microscopes and the like, and measuring parameters of the micro-nano line width dimension measuring instruments are line dimensions of samples. The research result shows that China has more than two thousand instruments for measuring various line width dimensions, and the instruments are widely applied to scientific research and production units and have high popularization rate. The micro-nano line width dimension measurement instrument is usually calibrated by using a line spacing standard sample wafer, and the structure of the line spacing sample wafer comprises a grating structure and a grid structure. To ensure that this type of instrument obtains accurate data during the measurement process, they should be calibrated using a series of corresponding line-spacing standards.
At present, only a line spacing standard sample wafer with a micron-scale grid structure exists, and the size and the structure of the line spacing sample wafer cannot meet the requirements of line width measurement instrument calibration.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a method for preparing a line spacing standard sample wafer, so as to solve the problem that the size and structure of the line spacing standard sample wafer in the prior art cannot meet the requirement of line width measurement instrument calibration.
The embodiment of the invention provides a method for preparing a gallium oxide field effect transistor, which comprises the following steps: carrying out first pretreatment on a substrate to remove impurities on the surface of the substrate;
growing a silicon nitride layer on the upper surface of the first area of the substrate subjected to the first pretreatment;
etching the silicon nitride layer to the substrate, and forming a silicon nitride pattern structure in the first region, wherein the silicon nitride pattern structure is a plurality of silicon nitride grating structures and/or silicon nitride grating structures with different period sizes;
carrying out second pretreatment on the substrate to remove impurities on the surface of the substrate;
growing a silicon dioxide layer on the upper surface of the second area of the substrate subjected to the second pretreatment; wherein the first region is non-overlapping with the second region;
etching the silicon dioxide layer to the substrate, and forming a silicon dioxide pattern structure in the second area, wherein the silicon dioxide pattern structure is a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with different period sizes;
and growing a metal layer on the upper surface of the second area of the substrate on which the silicon dioxide pattern structure is formed.
Optionally, the growing a silicon nitride layer on the upper surface of the first region of the substrate subjected to the first pretreatment includes:
forming a first protective layer on the upper surface of the second region of the substrate subjected to the first pretreatment;
and depositing a silicon nitride layer of 50-100 nm on the upper surface of the substrate forming the first protective layer by a chemical vapor deposition method.
Further, the etching the silicon nitride layer to the substrate to form a silicon nitride pattern structure in the first region includes:
coating a first photoresist on the upper surface of the silicon nitride layer;
photoetching is carried out through an electron beam photoetching process, and a first photoresist pattern structure is formed in the first area;
etching the silicon nitride layer which is not masked by the first photoresist by an etching process to the substrate to form a plurality of silicon nitride grating structures and/or silicon nitride grating structures with the period size of 200-500 nanometers;
removing the residual first photoresist;
and removing the first protective layer and the silicon nitride layer on the upper surface of the first protective layer.
Optionally, the growing a silicon dioxide layer on the upper surface of the second region of the substrate subjected to the second pretreatment includes:
forming a second protective layer on the upper surface of the first region of the substrate subjected to the second pretreatment;
and growing a silicon dioxide layer of 80-120 nanometers on the upper surface of the substrate forming the second protective layer through a thermal oxidation process.
Further, the etching the silicon dioxide layer to the substrate to form a silicon dioxide pattern structure in the second region includes:
coating a second photoresist on the upper surface of the silicon dioxide layer;
photoetching is carried out through a projection photoetching process, and a second photoresist pattern structure is formed in the second area;
etching the silicon dioxide layer which is not masked by the second photoresist by an etching process to the substrate to form a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with the period sizes of 1-10 micrometers respectively;
and removing the residual second photoresist.
Further, the growing a metal layer on the upper surface of the second region of the substrate on which the silicon dioxide pattern structure is formed includes:
sputtering a metal chromium layer of 10-20 nm on the upper surface of the substrate on which the silicon dioxide pattern structure is formed;
and removing the second protective layer, the silicon dioxide layer on the upper surface of the second protective layer and the metal chromium layer on the upper surface of the second protective layer.
Optionally, the performing a first pretreatment on the substrate includes:
putting the substrate into a first cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the first cleaning solution is a mixed solution of distilled water, ammonia water and hydrogen peroxide, and the volume ratio of the distilled water to the ammonia water to the hydrogen peroxide is 4:1: 1;
washing the substrate to neutrality by using distilled water;
cleaning the substrate in a hydrofluoric acid solution for 2 to 5 minutes;
washing the substrate to neutrality by using distilled water;
putting the substrate into a second cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the second cleaning solution is a mixed solution of distilled water, hydrochloric acid and hydrogen peroxide, and the volume ratio of the distilled water to the hydrochloric acid to the hydrogen peroxide is 4:1: 1;
washing the substrate to neutrality by using distilled water;
the substrate was blow dried with nitrogen.
Optionally, the performing a second pretreatment on the substrate includes:
putting the substrate into a first cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the first cleaning solution is a mixed solution of distilled water, ammonia water and hydrogen peroxide, and the volume ratio of the distilled water to the ammonia water to the hydrogen peroxide is 4:1: 1;
washing the substrate to neutrality by using distilled water;
cleaning the substrate in a hydrofluoric acid solution for 2 to 5 minutes;
washing the substrate to neutrality by using distilled water;
putting the substrate into a second cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the second cleaning solution is a mixed solution of distilled water, hydrochloric acid and hydrogen peroxide, and the volume ratio of the distilled water to the hydrochloric acid to the hydrogen peroxide is 4:1: 1;
washing the substrate to neutrality by using distilled water;
the substrate was blow dried with nitrogen.
Optionally, the method further includes:
forming a first alignment mark at a position corresponding to the silicon nitride pattern structure;
and forming a second alignment mark at the corresponding position of the silicon dioxide pattern structure.
Optionally, in the silicon nitride grating structure and/or the silicon nitride grating structure, the width of the silicon nitride layer is equal to the width between two adjacent silicon nitride layers;
in the silicon dioxide grating structure and/or the silicon dioxide grating structure, the width of the silicon dioxide layer is equal to the width between two adjacent silicon dioxide layers.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: according to the embodiment of the invention, the line spacing standard sample wafers with different cycle sizes and different structures are manufactured on the same substrate through a semiconductor process, the line spacing standard sample wafers meeting the requirements of various measuring instruments are manufactured through one-time processing technology, and the cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a flowchart of an implementation of a method for preparing a standard line-space sample according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating an implementation of a method for manufacturing a standard line-space sample according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating an implementation of a method for manufacturing a standard line-space sample according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a silicon nitride pattern provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of a silicon dioxide pattern structure provided by an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a silicon nitride pattern provided by an embodiment of the present invention;
fig. 7 is a schematic diagram of a silicon dioxide pattern structure provided by an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1, the method for preparing the standard line-space sample includes:
step S101, performing a first pretreatment on the substrate 101 to remove impurities on the surface of the substrate 101.
In the embodiment of the present invention, the substrate 101 is a silicon substrate, a double-sided polished silicon wafer is used as the substrate, and the crystal orientation of the silicon wafer is <100 >. The first pretreatment of the substrate 101 is performed for the purpose of removing impurities from the surface of the substrate 101.
Optionally, the specific implementation method of step S101 is: putting the substrate 101 into a first cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the first cleaning solution is a mixed solution of distilled water, ammonia water and hydrogen peroxide, and the volume ratio of the distilled water to the ammonia water to the hydrogen peroxide is 4:1: 1; washing the substrate 101 to neutrality by using distilled water; cleaning the substrate 101 in a hydrofluoric acid solution for 2 to 5 minutes; washing the substrate 101 to neutrality by using distilled water; putting the substrate 101 into a second cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the second cleaning solution is a mixed solution of distilled water, hydrochloric acid and hydrogen peroxide, and the volume ratio of the distilled water to the hydrochloric acid to the hydrogen peroxide is 4:1: 1; washing the substrate 101 to neutrality by using distilled water; the substrate 101 is blow-dried with nitrogen.
Step S102 is to grow a silicon nitride layer 102 on the upper surface of the first region of the substrate 101 subjected to the first pretreatment.
In the embodiment of the present invention, the substrate 101 is divided into a first region and a second region, the first region is used for preparing a silicon nitride pattern structure, the second region is used for preparing a silicon dioxide pattern structure, and the first region and the second region do not overlap. A silicon nitride layer 102 is grown on the upper surface of the first region by chemical vapor deposition.
Referring to fig. 2(1) and fig. 2(3), optionally, the specific implementation method of step S102 is: forming a first protective layer 202 on an upper surface of the second region of the substrate 201 subjected to the first pretreatment; depositing a silicon nitride layer 203 of 50 nm to 100 nm on the upper surface of the substrate 201 forming the first protective layer 202 by a chemical vapor deposition method.
In the embodiment of the present invention, a layer of photoresist may be deposited on the upper surface of the second region of the substrate 201 as the first protection layer 202 or a shielding layer may be covered on the upper surface of the second region of the substrate 201 as the first protection layer 202, and the shielding layer may be a shielding sheet, including but not limited to a substrate sheet. A silicon nitride layer 203 of 50 nm to 100 nm is grown on the upper surface of the substrate 201 by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the silicon nitride layer 203 covers the upper surface of the substrate 201 in the first region and the upper surface of the first protective layer 202 in the second region.
Step S103, etching the silicon nitride layer 102 to the substrate, and forming a silicon nitride pattern structure 103 in the first region, wherein the silicon nitride pattern structure 103 is a plurality of silicon nitride grating structures and/or silicon nitride grating structures with different period sizes.
Referring to fig. 2(4) to fig. 2(8), optionally, the specific implementation manner of step S103 is: coating a first photoresist 204 on the upper surface of the silicon nitride layer 203; performing photoetching through an electron beam photoetching process to form a photoresist pattern structure 205 in the first area; etching the silicon nitride layer 203 which is not masked by the photoresist by an etching process until reaching the substrate 201 to form a plurality of silicon nitride grating structures and/or silicon nitride grid structures 206 with the period size of 200-500 nanometers; removing the residual photoresist; the first protection layer 202 and the silicon nitride layer 203 on the upper surface of the first protection layer 202 are removed. Through the above process, a silicon nitride pattern structure 206 is formed on the upper surface of the first region of the substrate 201, wherein the silicon nitride pattern structure 206 is a plurality of silicon nitride grating structures and/or silicon nitride grating structures with a period size of 200 nm to 500 nm.
In the embodiment of the invention, first, a first photoresist 204 is coated on the upper surface of the silicon nitride layer 203, the model of the first photoresist 204 is GL2000 photoresist, the thickness of the first photoresist 204 is 230 nanometers, the first photoresist is baked at the temperature of 180 ℃ for 2 minutes, then, a pattern structure to be manufactured is directly written on the first photoresist 204 by using an electron beam lithography process, the first photoresist is developed in an o-xylene solution for 100 seconds, then, the first photoresist in a light transmission area is fixed for 60 seconds, a first photoresist pattern structure 205 is formed, the first photoresist pattern structure 205 is a grating structure and/or a grid structure with the period size of 200 nanometers to 500 nanometers, and then, the dry etching process is used for etching, and nitrogen which is not masked by the first photoresist pattern structure 205 is etchedEtching off the silicon layer 203 to the substrate 201 with SF6And forming a silicon nitride pattern structure 206 at an etching rate of 15nm/min, wherein the silicon nitride pattern structure 206 is a plurality of silicon nitride grating structures and/or silicon nitride grating structures with a period size of 200 nm to 500 nm, and finally removing the first photoresist 204 and the first photoresist pattern structure 205 in the second region, and removing the first protective layer 202 and the silicon nitride layer 203 on the upper surface of the first protective layer 202. In one possible implementation, the first protection layer 202 is a photoresist layer, and the photoresist layer is removed by a photoresist stripping process, and the silicon nitride layer 203 on the upper surface of the photoresist layer is also removed. In another possible implementation manner, the first protection layer 202 is a shielding layer, and the silicon nitride layer 203 on the upper surface of the shielding layer is removed by removing the shielding layer. Through the above process, a plurality of silicon nitride grating structures and/or silicon nitride grating structures with a period size of 200 nm to 500 nm are formed on the upper surface of the first region of the substrate 201.
In an embodiment of the present invention, the period size of the silicon nitride grating structure and/or the silicon nitride grating structure is 200 nm to 500 nm, and is used for calibrating a linewidth measuring instrument, a scanning electron microscope and an atomic force microscope.
Step S104, carrying out second pretreatment on the substrate 101 to remove impurities on the surface of the substrate.
Optionally, the specific implementation manner of step S104 is: putting the substrate 101 into a first cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the first cleaning solution is a mixed solution of distilled water, ammonia water and hydrogen peroxide, and the volume ratio of the distilled water to the ammonia water to the hydrogen peroxide is 4:1: 1; washing the substrate 101 to neutrality by using distilled water; cleaning the substrate 101 in a hydrofluoric acid solution for 2 to 5 minutes; washing the substrate 101 to neutrality by using distilled water; putting the substrate 101 into a second cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the second cleaning solution is a mixed solution of distilled water, hydrochloric acid and hydrogen peroxide, and the volume ratio of the distilled water to the hydrochloric acid to the hydrogen peroxide is 4:1: 1; washing the substrate 101 to neutrality by using distilled water; the substrate 101 is blow-dried with nitrogen. Through the above process steps, a clean substrate surface is obtained.
Step S105, growing a silicon dioxide layer 104 on the upper surface of the second region of the substrate 101 subjected to the second pretreatment.
Referring to fig. 3(1) and fig. 3(2), optionally, the specific implementation manner of step S105 is: forming a second protective layer 207 on the upper surface of the first region of the second pre-treated substrate 201; a silicon dioxide layer 208 of 80 nm to 120 nm is grown on the upper surface of the substrate 201 by a thermal oxidation process.
In the embodiment of the present invention, the silicon dioxide layer 208 covers the upper surface of the second protective layer 207 and the upper surface of the substrate 201 in the second region. The silicon dioxide layer 208 is grown by dry oxygen oxidation, wet oxygen oxidation and then dry oxygen oxidation, wherein the wet oxygen oxidation is a method of hydrogen and oxygen synthesis. The silicon nitride pattern structure 206 of the first region is protected by the second protective layer 207.
Step S106, etching the silicon dioxide layer 104 to the substrate 101, and forming a silicon dioxide pattern structure 105 in the second region, wherein the silicon dioxide pattern structure 105 is a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with a period size of 1 micron to 10 microns respectively.
Referring to fig. 3(3) to fig. 3(6), optionally, the specific implementation manner of step S106 is: coating a second photoresist 209 on the upper surface of the silicon dioxide layer 208; photoetching is carried out through a projection photoetching process, and a second photoresist pattern structure 210 is formed in the second area; etching the silicon dioxide layer 208 which is not masked by the second photoresist through an etching process to the substrate 201 to form a silicon dioxide pattern structure 211, wherein the silicon dioxide pattern structure 211 is a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with the period sizes of 1-10 micrometers respectively; and removing the residual second photoresist.
In the embodiment of the present invention, first, a second photoresist 209 is coated on the upper surface of the silicon dioxide layer 208, the second photoresist 209 is a GL2000 photoresist with a thickness of 400 nm to 500 nm, and the temperature is 130 deg.CBaking for 15 minutes at high temperature, then photoetching by adopting a projection photoetching process with the projection ratio of 1:4, exposing by deep ultraviolet light, wherein the mask is a positive plate, the graphic area of the mask is a non-light-transmitting area, the second photoresist in the light-transmitting area is removed through developing in NaOH solution, and then baked at a temperature of 130 c for 15 minutes, thereby forming a second photoresist pattern structure 210, wherein the second photoresist pattern structure 210 is a plurality of grating structures and/or grating structures having a period size of 1 micron to 10 microns, respectively, and, finally, etching is performed using a dry etching process to remove the silicon dioxide layer 208 not masked by the second photoresist, forming a silicon dioxide pattern structure 211, the silicon dioxide pattern structure 211 is a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with a period size of 1 micron to 10 microns respectively. In the etching process, the etching gas is SF6Or C4F8，SF6Mainly plays a role of etching, C4F8The polymer protection is realized, and the etching rate is set to be 15nm/min to 20 nm/min.
Step S107, growing a metal layer 106 on the upper surface of the second region of the substrate on which the silicon dioxide pattern structure is formed.
Referring to fig. 3(7) and fig. 3(8), the specific implementation manner of step S107 is: sputtering a metal chromium layer 212 with the thickness of 10 nanometers to 20 nanometers on the upper surface of the substrate 201 on which the silicon dioxide pattern structure is formed; and removing the second protective layer 207, the silicon dioxide layer 208 on the upper surface of the second protective layer 207 and the metal chromium layer 212 on the upper surface of the second protective layer 207.
In the embodiment of the present invention, a metal chromium layer 212 with a thickness of 10 nm to 20nm is sputtered on the upper surface of the first region and the upper surface of the second region through a sputtering process, and then the second protective layer 207 of the first region and the silicon dioxide layer 208 and the metal chromium layer 212 on the upper surface of the second protective layer are removed. In a possible implementation manner, the second protection layer 207 is made of photoresist, the second protection layer 207 is removed through a photoresist stripping process, and the silicon dioxide layer 208 and the metal chromium layer 212 on the upper surface of the second protection layer 207 are also removed.
Through sputtering metallic chromium layer 206 on the upper surface in the second region, play the effect of protection on the one hand, prevent that the substrate exposed in the air from being oxidized, lead to the grating height or the grid height of sample wafer to change, another becomes one side, to scanning electron microscope, needs sample wafer electrically conductive, after the upper surface in the second region sputters the metal, has guaranteed the electric conductivity of sample wafer, makes this sample wafer can be applicable to scanning electron microscope.
In the embodiment of the present invention, the silicon nitride pattern structure may be first prepared in the first region, and then the silicon dioxide pattern structure may be prepared in the second region, or the silicon dioxide pattern structure may be first prepared in the second region, and then the silicon nitride pattern structure may be prepared in the first region, which is not limited herein.
The embodiment of the invention manufactures the line spacing standard sample wafers with different cycle sizes and different structures on the same substrate through a semiconductor process, manufactures the line spacing standard sample wafers meeting the requirements of various measuring instruments through one-time processing technology, and can reduce the cost.
Optionally, referring to fig. 4, a first alignment mark 402 is formed in a corresponding position of the silicon nitride pattern structure 401 in the first region. Referring to fig. 5, second alignment marks 502 are formed at corresponding positions of the silicon dioxide pattern structures 501 in the second region. Alignment is facilitated in use by the first alignment mark 402 and the second alignment mark 502.
In this embodiment, when the silicon nitride pattern structure is etched, the first alignment mark 402 is etched on the silicon nitride layer in the first region to reach the substrate, and when the silicon dioxide pattern structure is etched, the second alignment mark 502 is etched on the silicon dioxide layer in the second region to reach the substrate.
Referring to fig. 6, optionally, in the silicon nitride grating structure and/or the silicon nitride grating structure, the width of the silicon nitride layer is equal to the width between two adjacent silicon nitride layers, that is, the width W1 of the silicon nitride layer is equal to the width W2 between two silicon nitride layers in fig. 6, and the sum of W1 and W2 is one period.
Referring to fig. 7, in the silica grating structure and/or the silica grating structure, the width of the silica layer is equal to the width between two adjacent silica layers, i.e., the width L1 of the silica layer is equal to the width L2 between two silica layers in fig. 7, and the sum of L1 and L2 is one period.
In the embodiment of the invention, the substrate is a 4-inch silicon wafer, a plurality of grating structures and/or grating structures with different period sizes are prepared on the silicon wafer, the sample wafer is diced after the preparation of the sample wafer, the sample wafer is divided into a plurality of square small pieces, and each small piece comprises a plurality of grating structures or grating structures with the same period size.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (5)
1. A preparation method of a line spacing standard sample wafer is characterized by comprising the following steps:
carrying out first pretreatment on a substrate to remove impurities on the surface of the substrate;
growing a silicon nitride layer on the upper surface of the first area of the substrate subjected to the first pretreatment;
etching the silicon nitride layer to the substrate, and forming a silicon nitride pattern structure in the first region, wherein the silicon nitride pattern structure is a plurality of silicon nitride grating structures and/or silicon nitride grating structures with different period sizes;
carrying out second pretreatment on the substrate to remove impurities on the surface of the substrate;
growing a silicon dioxide layer on the upper surface of the second area of the substrate subjected to the second pretreatment; wherein the first region is non-overlapping with the second region;
etching the silicon dioxide layer to the substrate, and forming a silicon dioxide pattern structure in the second area, wherein the silicon dioxide pattern structure is a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with different period sizes; growing a metal layer on the upper surface of the second area of the substrate on which the silicon dioxide pattern structure is formed;
the growing a silicon nitride layer on the upper surface of the first region of the substrate subjected to the first pretreatment comprises: forming a first protective layer on the upper surface of the second region of the substrate subjected to the first pretreatment; depositing a silicon nitride layer of 50 nm to 100 nm on the upper surface of the substrate on which the first protective layer is formed by a chemical vapor deposition method;
the growing a silicon dioxide layer on the upper surface of the second region of the substrate subjected to the second pretreatment comprises: forming a second protective layer on the upper surface of the first region of the substrate subjected to the second pretreatment; growing a silicon dioxide layer of 80 to 120 nanometers on the upper surface of the substrate forming the second protective layer through a thermal oxidation process;
the first pre-treating the substrate comprises: putting the substrate into a first cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the first cleaning solution is a mixed solution of distilled water, ammonia water and hydrogen peroxide, and the volume ratio of the distilled water to the ammonia water to the hydrogen peroxide is 4:1: 1; washing the substrate to neutrality by using distilled water; cleaning the substrate in a hydrofluoric acid solution for 2 to 5 minutes; washing the substrate to neutrality by using distilled water; putting the substrate into a second cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the second cleaning solution is a mixed solution of distilled water, hydrochloric acid and hydrogen peroxide, and the volume ratio of the distilled water to the hydrochloric acid to the hydrogen peroxide is 4:1: 1; washing the substrate to neutrality by using distilled water; blowing the substrate with nitrogen;
the second pre-treating the substrate comprises: putting the substrate into a first cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the first cleaning solution is a mixed solution of distilled water, ammonia water and hydrogen peroxide, and the volume ratio of the distilled water to the ammonia water to the hydrogen peroxide is 4:1: 1; washing the substrate to neutrality by using distilled water; cleaning the substrate in a hydrofluoric acid solution for 2 to 5 minutes; washing the substrate to neutrality by using distilled water; putting the substrate into a second cleaning solution with the temperature of 80-90 ℃ for cleaning for 10-15 minutes; the second cleaning solution is a mixed solution of distilled water, hydrochloric acid and hydrogen peroxide, and the volume ratio of the distilled water to the hydrochloric acid to the hydrogen peroxide is 4:1: 1; washing the substrate to neutrality by using distilled water; the substrate was blow dried with nitrogen.
2. The method for preparing a standard line-space sample wafer according to claim 1, wherein the etching the silicon nitride layer to the substrate to form a silicon nitride pattern structure in the first region comprises:
coating a first photoresist on the upper surface of the silicon nitride layer;
photoetching is carried out through an electron beam photoetching process, and a first photoresist pattern structure is formed in the first area;
etching the silicon nitride layer which is not masked by the first photoresist by an etching process to the substrate to form a plurality of silicon nitride grating structures and/or silicon nitride grating structures with the period size of 200-500 nanometers;
removing the residual first photoresist;
and removing the first protective layer and the silicon nitride layer on the upper surface of the first protective layer.
3. The method according to claim 1, wherein the etching the silicon dioxide layer to the substrate to form a silicon dioxide pattern structure in the second region comprises:
coating a second photoresist on the upper surface of the silicon dioxide layer;
photoetching is carried out through a projection photoetching process, and a second photoresist pattern structure is formed in the second area;
etching the silicon dioxide layer which is not masked by the second photoresist by an etching process to the substrate to form a plurality of silicon dioxide grating structures and/or silicon dioxide grating structures with the period sizes of 1-10 micrometers respectively;
and removing the residual second photoresist.
4. The method for preparing a line-space proof sample wafer according to claim 3, wherein the growing a metal layer on the upper surface of the second region of the substrate on which the silicon dioxide pattern structure has been formed comprises:
sputtering a metal chromium layer of 10-20 nm on the upper surface of the substrate on which the silicon dioxide pattern structure is formed;
and removing the second protective layer, the silicon dioxide layer on the upper surface of the second protective layer and the metal chromium layer on the upper surface of the second protective layer.
5. The method of preparing a line-space master according to claim 1, further comprising:
forming a first alignment mark at a position corresponding to the silicon nitride pattern structure;
and forming a second alignment mark at the corresponding position of the silicon dioxide pattern structure.
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| CN108957611B (en) * | 2018-07-13 | 2021-05-14 | 歌尔股份有限公司 | Manufacturing method of grating sheet, grating sheet and display device |
| CN109444473B (en) * | 2018-12-24 | 2021-06-15 | 中国电子科技集团公司第十三研究所 | Line width standard sample and tracking method of standard lines in line width standard sample |
| CN109855572A (en) * | 2018-12-25 | 2019-06-07 | 中国电子科技集团公司第十三研究所 | For calibrating the line-spacing template and preparation method of optical profilometer roughness |
| CN111128964B (en) * | 2019-12-04 | 2021-10-01 | 中国电子科技集团公司第十三研究所 | Nanometer-sized line spacing standard sample wafer and preparation method thereof |
| CN111137846B (en) * | 2019-12-24 | 2023-04-11 | 中国电子科技集团公司第十三研究所 | Preparation method of micron-level step height standard sample block |
| CN111924798B (en) * | 2020-07-22 | 2023-05-16 | 中国电子科技集团公司第十三研究所 | Multilayer film deposition-based trace-searching line width standard sample wafer and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0632296A1 (en) * | 1993-07-02 | 1995-01-04 | Xerox Corporation | Amplitude and phase optical filtering binary diffractive optical element |
| US6570157B1 (en) * | 2000-06-09 | 2003-05-27 | Advanced Micro Devices, Inc. | Multi-pitch and line calibration for mask and wafer CD-SEM system |
| CN101106164A (en) * | 2007-06-29 | 2008-01-16 | 中国电子科技集团公司第十三研究所 | A crossed combined dual cycle grating for quanta trap infrared detector |
| CN101819067A (en) * | 2010-04-20 | 2010-09-01 | 上海大学 | Infrared microscopy specimen and establishment of standard data base thereof |
| CN105737879A (en) * | 2016-03-01 | 2016-07-06 | 中国电子科技集团公司第十三研究所 | Micron grade raster calibration sample wafer with step height |
| CN105865389A (en) * | 2016-06-08 | 2016-08-17 | 上海市计量测试技术研究院 | Micro-nanometer standard sample plate and tracking method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4373877B2 (en) * | 2004-08-09 | 2009-11-25 | 株式会社東芝 | Process management method, monitor mark forming method, and mask for process management |
| US8075299B2 (en) * | 2008-10-21 | 2011-12-13 | Molecular Imprints, Inc. | Reduction of stress during template separation |
-
2017
- 2017-11-29 CN CN201711223205.6A patent/CN107993956B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0632296A1 (en) * | 1993-07-02 | 1995-01-04 | Xerox Corporation | Amplitude and phase optical filtering binary diffractive optical element |
| US6570157B1 (en) * | 2000-06-09 | 2003-05-27 | Advanced Micro Devices, Inc. | Multi-pitch and line calibration for mask and wafer CD-SEM system |
| CN101106164A (en) * | 2007-06-29 | 2008-01-16 | 中国电子科技集团公司第十三研究所 | A crossed combined dual cycle grating for quanta trap infrared detector |
| CN101819067A (en) * | 2010-04-20 | 2010-09-01 | 上海大学 | Infrared microscopy specimen and establishment of standard data base thereof |
| CN105737879A (en) * | 2016-03-01 | 2016-07-06 | 中国电子科技集团公司第十三研究所 | Micron grade raster calibration sample wafer with step height |
| CN105865389A (en) * | 2016-06-08 | 2016-08-17 | 上海市计量测试技术研究院 | Micro-nanometer standard sample plate and tracking method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 可循迹纳米台阶标准样版的制备与表征;曲金成等;《微纳电子技术》;20171120;第54卷(第12期);第一部分-纳米台阶标准样版的制备 * |
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