CN112309826B - Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device - Google Patents

Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device Download PDF

Info

Publication number
CN112309826B
CN112309826B CN201910671910.5A CN201910671910A CN112309826B CN 112309826 B CN112309826 B CN 112309826B CN 201910671910 A CN201910671910 A CN 201910671910A CN 112309826 B CN112309826 B CN 112309826B
Authority
CN
China
Prior art keywords
layer
metal layer
semiconductor device
alloy layer
dry etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910671910.5A
Other languages
Chinese (zh)
Other versions
CN112309826A (en
Inventor
孔真真
王桂磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201910671910.5A priority Critical patent/CN112309826B/en
Publication of CN112309826A publication Critical patent/CN112309826A/en
Application granted granted Critical
Publication of CN112309826B publication Critical patent/CN112309826B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02491Conductive materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02535Group 14 semiconducting materials including tin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a semiconductor device, a manufacturing method and electronic equipment comprising the semiconductor device, wherein the semiconductor device comprises: a substrate; a metal layer formed over the substrate; the alloy layer is formed above the metal layer, wherein the alloy layer completely covers the surface of the metal layer, and the edge of the alloy layer exceeds the edge of the metal layer and is in a suspension state; a mask layer is formed over the alloy layer. The invention takes the mask layer as a hard mask to prepare the GeSn microdisk. Because the selected mask layer is transparent, testing can be performed after fabrication without removing the mask layer.

Description

Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and electronic equipment comprising the semiconductor device.
Background
In optoelectronic devices, geSn materials can extend the spectrum from visible to infrared, and even far infrared. Therefore, the GeSn material has wide application in high-speed electronic devices, high-efficiency photonic devices and infrared photons. In addition, the GeSn alloy can improve the mobility of a carrier, thereby greatly improving the electrical characteristics of a device, so that the GeSn material can also be used as a conductive channel of a field effect transistor and the like. When the epitaxial layer forms a suspended microdisk, the residual compressive stress of the GeSn epitaxial layer is released. Because the solid solubility of Sn in Ge is very low, a GeSn film with high component thickness is difficult to obtain, because the thickness of the GeSn film is too thin, when the GeSn film suspension microdisk is obtained by selective etching, on one hand, the edge of the GeSn film disk is easy to bend and upwarp due to strain release, and the bending and upwarping of the edge of the GeSn film disk can influence the later use of the film, and on the other hand, because the thickness of the GeSn film is too thin, the problem that the GeSn film suspension microdisk is not suitable to support is also existed when the GeSn film suspension microdisk is prepared. Therefore, in the prior art, it is difficult to directly manufacture a thin GeSn film suspension microdisk with high Sn component by selective etching.
Disclosure of Invention
An object of the present invention is to provide, at least in part, a semiconductor device, a method of manufacturing the same, and an electronic apparatus including the semiconductor device.
According to an aspect of the present invention, a semiconductor device includes: a substrate; a metal layer formed over the substrate; an alloy layer formed over the metal layer, wherein the alloy layer completely covers a surface of the metal layer, and an edge of the alloy layer is suspended beyond an edge of the metal layer; and forming a mask layer above the alloy layer, wherein the mask layer is made of a transparent material.
Preferably, the substrate material is Si or GaAs.
Preferably, the material of the metal layer is Ge.
Preferably, the alloy layer material is GeSn.
Preferably, the transparent material is SiO 2 Or Si 3 N 4 A material.
By the invention, siO is sputtered 2 A GeSn microdisk was prepared for the hard mask. Because of SiO 2 Is transparent, so SiO is not removed 2 In the case of (2), the test may be performed after the preparation. Wherein, siO 2 The GeSn microdisk has a supporting effect and can easily obtain an ultrathin (up to 10 nm) GeSn microdisk with strain release.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a substrate, depositing a metal layer above the substrate, and depositing an alloy layer above the metal layer; depositing a mask layer above the alloy layer, wherein the mask layer is made of a transparent material; forming a patterned photoresist over the mask layer; performing a first dry etching process to remove part of the mask layer; performing a second dry etching process to remove a part of the metal layer and the alloy layer; removing the photoresist; and carrying out a third dry etching process to remove the part of the residual metal layer, so that the part of the alloy layer covers the metal layer, and the edge of the alloy layer exceeds the edge of the metal layer and is in a suspension state.
Preferably, the first dry etching process includes using CF 4 Chlorine is used as etching gas for dry etching.
Preferably, the second dry etching process includes dry etching using chlorine as an etching gas.
Preferably, the third dry etching process includes using CF 4 And O 2 And etching with etching gas to perform dry etching.
According to an aspect of the present invention, there is provided an electronic apparatus including an integrated circuit formed of the above semiconductor device.
Preferably, the electronic device further comprises: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
Drawings
Various aspects of this invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 through 7 show a flow chart for fabricating a semiconductor device according to a disclosed embodiment of the invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact.
Furthermore, spatial relationship terms, such as "below", "lower", "above", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.
Fig. 1-6 show a flow chart of a method of manufacturing a semiconductor device according to a disclosed embodiment of the invention.
In this embodiment, the semiconductor device includes: a substrate 101; a metal layer 102 formed over the substrate; an alloy layer 103 formed over the metal layer, wherein the alloy layer completely covers the surface of the metal layer, and an edge of the alloy layer is suspended beyond the edge of the metal layer; a mask layer 104 is formed over the alloy layer, the mask layer 104 being a transparent material.
A substrate 101. In the present embodiment, as shown in fig. 1, the substrate 101 is a bulk silicon semiconductor substrate. Further, the substrate 101 may be a substrate of various forms including, but not limited to, a silicon-on-semiconductor Substrate (SOI), a compound semiconductor substrate (e.g., a GaAs substrate), an alloy semiconductor substrate (e.g., a SiGe substrate), and the like. In some embodiments, the semiconductor substrate may include a doped epitaxial layer.
Continuing with fig. 1, a metal layer 102 is formed over the substrate 101. A metal layer 102 is deposited on the substrate 101. In some embodiments, metal layer 102 comprises Ge element. In some embodiments, the metal layer 102 is formed by any of a variety of deposition techniques, including Low Pressure Chemical Vapor Deposition (LPCVD), atmospheric Pressure Chemical Vapor Deposition (APCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and other suitable deposition techniques.
And an alloy layer 103 formed above the metal layer 102, wherein the alloy layer 103 completely covers the surface of the metal layer 102, and the edge of the alloy layer 103 is suspended beyond the edge of the metal layer 102. The process method for forming the suspended alloy layer comprises the following steps:
in the present embodiment, as shown in fig. 1, an alloy layer 103 is formed over the metal layer 102. The alloy layer 103 uses GeSn material. In some embodiments, alloy layer 103 may be formed using LPCVD, APCVD, PECVD, PVD, or sputtering.
As shown in fig. 2, a mask layer 104 is formed over the alloy layer 103. The mask layer 104 may be a hard mask layer formed of a transparent material, for example, siO 2 、Si 3 N 4 Etc. a transparent material. Specifically, the mask layer 104 is formed by using a low-temperature sputtering method, wherein the low temperature is not more than 300 ℃, and the thickness of the transparent mask layer 104 is not more than 200 nm.
In the present embodiment, a patterned photoresist 105 is formed over the mask layer 104, as shown in fig. 3. The photoresist may be formed by a conventional method, for example, a photoresist may be spin-coated on a mask layer, and then a desired shape of the photoresist may be finally formed through exposure, development and removal steps. Other methods of forming patterned photoresist may also be employed. The photoresist and underlying material are then dry etched.
As shown in fig. 4, a first dry etching process is performed to remove a portion of the mask layer 104, and the mask layer 104 under the photoresist 105 remains. Etching with common Inductively Coupled Plasma (ICP) etcher, wherein the first dry etching adopts CF 4 (ii) a The gas pressure is controlled at 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 400W, and the lower radio frequency power is 100W 4 The total flow rate of (3) is 50sccm.
And a second dry etching process is performed to remove part of the metal layer 102 and the alloy layer 103 as shown in fig. 5. And etching by using a common Inductively Coupled Plasma (ICP) etching machine, wherein the secondary dry etching process adopts chlorine, the air pressure is controlled to be 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 300W, the lower radio frequency power is 45W, and the total flow of the chlorine is 35sccm.
As shown in fig. 6, the photoresist 105 is removed. The photoresist 105 may be removed by a dry stripping process.
As shown in fig. 7, a third dry etching process is performed to remove a portion of the remaining metal layer 102, such that the alloy layer 103 partially covers the metal layer 102, and an edge of the alloy layer 103 exceeds an edge of the metal layer 102 and is in a suspended state. Etching with common Inductively Coupled Plasma (ICP) etcher, wherein the third dry etching process adopts CF 4 +O 2 The gas pressure is controlled at 90mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 200W, and the lower radio frequency power is 0W, CF 4 /O 2 Has a total flow rate of 100sccm, wherein CF is used 4 /O 2 In volume percent, CF 4 Volume ratio of 70%, O 2 The volume ratio is 30%.
In general, the disclosed method produces GeSn thin film suspended microdisk by low temperature sputter deposition of a mask layer of transparent material on an alloy layer (i.e., geSn). The GeSn film suspension micro-disk is characterized in that the mask layer is made of a transparent material, the transparent mask layer is arranged on the GeSn film suspension micro-disk, the performance of the GeSn film suspension micro-disk cannot be affected, after the mask layer acts on the GeSn film suspension micro-disk, the situation that the edge of the etched GeSn film suspension micro-disk bends and upwarps due to stress release can be avoided, a supporting effect can be generated on the GeSn film suspension micro-disk, and the problem that the thin GeSn film suspension micro-disk with high Sn components is difficult to manufacture directly through selective etching in the prior art is solved. In addition, when the mask layer film is prepared by sputtering the transparent material at low temperature, the stress of the prepared mask layer is small, and other stresses cannot be additionally introduced to the GeSn film suspension micro-disk, so that the measurement of the subsequent performance of the GeSn film suspension micro-disk is influenced.
According to an embodiment of the present invention, there is also provided a method of manufacturing a semiconductor device. The method comprises the following steps:
s1: forming a substrate, depositing a metal layer above the substrate, and depositing an alloy layer above the metal layer;
in this step, a metal layer 102 is deposited on the substrate 101, and an alloy layer 103 is deposited over the metal layer 102, and any one of various deposition techniques including Low Pressure Chemical Vapor Deposition (LPCVD), atmospheric Pressure Chemical Vapor Deposition (APCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and other suitable CVD epitaxial techniques may be selected to form the metal layer 102 and the alloy layer 103.
S2: depositing a mask layer above the alloy layer, wherein the mask layer is made of a transparent material;
in this step, the mask layer 104 is also formed using a method specifically using low-temperature sputtering. Specifically, the mask layer 104 is formed by using a low-temperature sputtering method, wherein the low temperature is not more than 300 ℃, and the thickness of the transparent mask layer 104 is not more than 200 nanometers. In some embodiments, a 100 nm thick SiO layer is prepared by low temperature sputtering at 300 ℃ over the alloy layer 103 2 And (5) masking the layer. In other embodiments, by being above the alloy layer 103,adopts low-temperature sputtering at 200 ℃ to prepare SiO with the thickness of 30 nanometers 2 And (5) masking the layer. Of course, the temperature of the low-temperature sputtering can be any temperature such as 120-200 ℃, and the formed SiO 2 Mask layer or Si 3 N 4 The mask layer is a transparent hard mask layer, the thickness of the mask layer is as thin as possible, for example, the thickness of the mask layer is 20 nanometers to 100 nanometers, and the thickness of the mask layer is also based on the fact that after the mask layer acts on the alloy layer (namely, the GeSn film layer), the edge of the alloy layer does not bend and upwarp when the mask layer and the alloy layer (namely, the GeSn film layer) are etched together, and the mask layer is easy to support.
S3: forming a patterned photoresist over the mask layer;
in this step, a photoresist may be formed by a conventional method, for example, a photoresist may be spin-coated on a mask layer, and then a desired shape of the photoresist may be finally formed through exposure, development, and removal steps. Other methods of forming patterned photoresist may also be employed. The photoresist and underlying material are then dry etched.
S4: carrying out a first dry etching process to remove part of the mask layer;
in the step, a common Inductively Coupled Plasma (ICP) etching machine is adopted for etching, wherein CF is adopted for the first dry etching 4 The gas pressure is controlled at 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 400W, and the lower radio frequency power is 100W 4 The total flow rate of (b) is 50sccm.
S5: performing a second dry etching process to remove part of the metal layer and the alloy layer;
in the step, a common Inductively Coupled Plasma (ICP) etching machine is adopted for etching, wherein the secondary dry etching process adopts chlorine, the gas pressure is controlled to be 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 300W, the lower radio frequency power is 45W, and the total flow of the chlorine is 35sccm.
S6: removing the patterned photoresist;
in this step, the patterned photoresist 105 may be removed by a dry stripping process.
S7: and carrying out a third dry etching process to remove the part of the residual metal layer again, so that the part of the alloy layer covers the metal layer, and the edge of the alloy layer exceeds the edge of the metal layer and is in a suspension state.
In the step, a common Inductively Coupled Plasma (ICP) etching machine is adopted for etching, wherein CF is adopted for the third dry etching process 4 +O 2 The gas pressure is controlled at 90mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 200W, and the lower radio frequency power is 0W, CF 4 /O 2 Has a total flow rate of 100sccm, wherein CF is used 4 /O 2 In volume percent, CF 4 Volume ratio of 70%, O 2 The volume ratio is 30%.
In the preparation method, the GeSn microdisk with a thin high Sn component can be directly prepared by selective etching under the etching process condition by controlling the dry etching process condition for three times, the GeSn film suspension microdisk prepared by the method has a thin thickness which can reach 10 to 20 nanometers, and after the GeSn film suspension microdisk and the mask layer of the transparent material act together, the problems that the edge of the thin GeSn film suspension microdisk with the high Sn component in the prior art is bent and upwarps and is not easy to support can be solved, and the preparation method has remarkable beneficial effects.
The components of several embodiments are discussed above so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (11)

1. A semiconductor device, comprising:
a substrate;
a metal layer formed over the substrate;
an alloy layer formed over the metal layer, wherein the alloy layer completely covers a surface of the metal layer, and an edge of the alloy layer is suspended beyond an edge of the metal layer;
and forming a mask layer above the alloy layer by using a low-temperature sputtering method, wherein the low-temperature sputtering temperature is not more than 300 ℃, and the mask layer is a transparent material with the thickness not more than 200 nanometers.
2. The semiconductor device according to claim 1, wherein the substrate material is Si or GaAs.
3. The semiconductor device according to claim 1, wherein a material of the metal layer is Ge.
4. The semiconductor device according to claim 1, wherein the alloy layer material is GeSn.
5. The semiconductor device according to claim 1, wherein the transparent material is SiO 2 Or Si 3 N 4 A material.
6. A method of manufacturing a semiconductor device, comprising:
forming a substrate, depositing a metal layer above the substrate, and depositing an alloy layer above the metal layer;
depositing a mask layer above the alloy layer by using a low-temperature sputtering method, wherein the low-temperature sputtering temperature is not more than 300 ℃, and the mask layer is a transparent material with the thickness not more than 200 nanometers;
forming a patterned photoresist over the mask layer;
performing a first dry etching process to remove part of the mask layer;
performing a second dry etching process to remove part of the metal layer and the alloy layer;
removing the photoresist;
and carrying out a third dry etching process to remove the part of the residual metal layer, so that the part of the alloy layer covers the metal layer, and the edge of the alloy layer exceeds the edge of the metal layer and is in a suspension state.
7. The method of claim 6, wherein the first dry etching process comprises using CF 4 And etching with etching gas to perform dry etching.
8. The method of manufacturing a semiconductor device according to claim 6, wherein the second dry etching process comprises dry etching using chlorine gas as an etching gas.
9. The method of claim 6, wherein the third dry etching process comprises using CF 4 And O 2 And etching with etching gas to perform dry etching.
10. An electronic device comprising an integrated circuit formed from the semiconductor device of any of claims 1~5.
11. The electronic device of claim 10, further comprising: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
CN201910671910.5A 2019-07-24 2019-07-24 Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device Active CN112309826B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910671910.5A CN112309826B (en) 2019-07-24 2019-07-24 Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910671910.5A CN112309826B (en) 2019-07-24 2019-07-24 Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device

Publications (2)

Publication Number Publication Date
CN112309826A CN112309826A (en) 2021-02-02
CN112309826B true CN112309826B (en) 2022-10-21

Family

ID=74329680

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910671910.5A Active CN112309826B (en) 2019-07-24 2019-07-24 Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device

Country Status (1)

Country Link
CN (1) CN112309826B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101768743A (en) * 2008-12-30 2010-07-07 中芯国际集成电路制造(上海)有限公司 Method for etching germanium antimony tellurium alloy materials
CN101895060A (en) * 2010-06-10 2010-11-24 中国科学院苏州纳米技术与纳米仿生研究所 Multiband silicon-based microdisk mixing laser device thereof and preparation method thereof
CN102718180A (en) * 2012-06-28 2012-10-10 中国科学院苏州纳米技术与纳米仿生研究所 Concentric ring core nano silicon micro-disk micro-cavity device and preparation method thereof
CN103641059A (en) * 2013-12-30 2014-03-19 中国人民解放军国防科学技术大学 Silicon-pillared metal film nano-structure array and preparation method thereof
CN103708405A (en) * 2013-11-08 2014-04-09 南京大学 On-chip large-dig-angle silicon oxide micro-disc resonant cavity and manufacturing method for same
CN105480939A (en) * 2015-12-03 2016-04-13 中国科学院物理研究所 Preparation method of three-dimensional structure with liquid full super-hydrophobic function
CN106744657A (en) * 2016-12-09 2017-05-31 中国科学院上海微系统与信息技术研究所 A kind of preparation method of three-dimensional GeSn micro/nano-scales cantilever design
CN108923245A (en) * 2018-07-27 2018-11-30 南京大学 A kind of micro- disk Ramar laser and preparation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7951299B2 (en) * 2007-02-27 2011-05-31 California Institute Of Technology Method of fabricating a microresonator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101768743A (en) * 2008-12-30 2010-07-07 中芯国际集成电路制造(上海)有限公司 Method for etching germanium antimony tellurium alloy materials
CN101895060A (en) * 2010-06-10 2010-11-24 中国科学院苏州纳米技术与纳米仿生研究所 Multiband silicon-based microdisk mixing laser device thereof and preparation method thereof
CN102718180A (en) * 2012-06-28 2012-10-10 中国科学院苏州纳米技术与纳米仿生研究所 Concentric ring core nano silicon micro-disk micro-cavity device and preparation method thereof
CN103708405A (en) * 2013-11-08 2014-04-09 南京大学 On-chip large-dig-angle silicon oxide micro-disc resonant cavity and manufacturing method for same
CN103641059A (en) * 2013-12-30 2014-03-19 中国人民解放军国防科学技术大学 Silicon-pillared metal film nano-structure array and preparation method thereof
CN105480939A (en) * 2015-12-03 2016-04-13 中国科学院物理研究所 Preparation method of three-dimensional structure with liquid full super-hydrophobic function
CN106744657A (en) * 2016-12-09 2017-05-31 中国科学院上海微系统与信息技术研究所 A kind of preparation method of three-dimensional GeSn micro/nano-scales cantilever design
CN108923245A (en) * 2018-07-27 2018-11-30 南京大学 A kind of micro- disk Ramar laser and preparation method thereof

Also Published As

Publication number Publication date
CN112309826A (en) 2021-02-02

Similar Documents

Publication Publication Date Title
KR101433899B1 (en) Method for forming metallic layer on portion etched of substrate, the substrate having the metallic layer formed using the same and a structure formed using the same
US20060289954A1 (en) Method for processing a MEMS/CMOS cantilever based memory storage device
WO2009057764A1 (en) Etching method and method for manufacturing optical/electronic device using the same
CN105810615A (en) Method and system for monitoring in-situ etching of etching sample by employing crystal oscillator
CN106611738B (en) The preparation method of III-V compound substrate on insulator
CN112309826B (en) Semiconductor device, manufacturing method thereof and electronic equipment comprising semiconductor device
CN109216156B (en) Method for sealing wafer on back surface
WO2004082002A1 (en) A method of forming an element of a microelectronic circuit
KR101503535B1 (en) Method for manufacturing semiconductor device
CN108063088B (en) Patterning method of SiC substrate
US20210090949A1 (en) Semiconductor structure and fabrication method thereof
CN109300781B (en) Method for manufacturing ONO film layer
US10141408B2 (en) Method and arrangement for reducing contact resistance of two-dimensional crystal material
CN110211944B (en) Semiconductor device and forming method
CN102176430A (en) Method for eliminating redeposition of side wall of grid and semiconductor device
US20130130503A1 (en) Method for fabricating ultra-fine nanowire
KR101680070B1 (en) Semiconductor structure and method for manufacturing the same
CN111825055B (en) Gold etching method
CN104022063A (en) Method for forming shallow trench
CN111825055A (en) Etching method of gold
JP2004327844A (en) Silicon nitride film, its producing process, and functional device
CN106206404B (en) Semiconductor element and its manufacturing method
JPH0766421A (en) Thin-film transistor and its manufacture
CN111477545B (en) GaN device SiC substrate etching method
US11427731B2 (en) Adhesive silicon oxynitride film

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant