CN112309826A - Semiconductor device and manufacturing method and electronic equipment including the same - Google Patents
Semiconductor device and manufacturing method and electronic equipment including the same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 54
- 239000000956 alloy Substances 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229910005898 GeSn Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 39
- 238000001312 dry etching Methods 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 14
- 239000012780 transparent material Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 description 23
- 239000000725 suspension Substances 0.000 description 18
- 238000004544 sputter deposition Methods 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 5
- 229910052801 chlorine Inorganic materials 0.000 description 5
- 239000000460 chlorine Substances 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02535—Group 14 semiconducting materials including tin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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Abstract
本发明提出了一种半导体器件及制作方法及包括该器件的电子设备，半导体器件包括：衬底；在衬底上方形成的金属层；在金属层上方形成的合金层，其中，合金层完全覆盖金属层的表面，并且合金层的边缘超出金属层的边缘呈悬浮状；在合金层上方形成掩膜层。本发明以掩膜层为硬掩膜制备GeSn微盘。因为选用的掩膜层是透明的，所以在不去除掩膜层的情况下，可以在制备后进行测试。
The invention provides a semiconductor device, a manufacturing method and an electronic device including the device. The semiconductor device includes: a substrate; a metal layer formed on the substrate; an alloy layer formed on the metal layer, wherein the alloy layer completely covers The surface of the metal layer, and the edge of the alloy layer is suspended beyond the edge of the metal layer; a mask layer is formed over the alloy layer. In the invention, the GeSn microdisk is prepared by using the mask layer as the hard mask. Because the selected mask layer is transparent, it can be tested after fabrication without removing the mask layer.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and electronic equipment comprising the semiconductor device.
Background
In optoelectronic devices, GeSn materials can extend the spectral range from visible to infrared, and even far infrared. Therefore, the GeSn material has wide application in high-speed electronic devices, high-efficiency photonic devices and infrared photons. In addition, the GeSn alloy can improve the mobility of a carrier, thereby greatly improving the electrical characteristics of a device, so that the GeSn material can also be used as a conductive channel of a field effect transistor and the like. When the epitaxial layer forms a suspended microdisk, the residual compressive stress of the GeSn epitaxial layer is released. Because the solid solubility of Sn in Ge is very low, a GeSn film with high component thickness is difficult to obtain, because the thickness of the GeSn film is too thin, when the GeSn film suspension micro-disk is obtained by selective etching, on one hand, the edge of the GeSn film disk is easy to bend and upwarp due to strain release, and the edge of the GeSn film disk bends and upwarps to influence the later use of the film, and on the other hand, because the thickness of the GeSn film is too thin, the problem that the GeSn film suspension micro-disk is not suitable to be supported is also existed when the GeSn film suspension micro-disk is prepared. Therefore, in the prior art, it is difficult to directly manufacture a thin GeSn film suspension microdisk with high Sn component by selective etching.
Disclosure of Invention
An object of the present invention is to provide, at least in part, a semiconductor device, a method of manufacturing the same, and an electronic apparatus including the semiconductor device.
According to an aspect of the present invention, a semiconductor device includes: a substrate; a metal layer formed over the substrate; an alloy layer formed over the metal layer, wherein the alloy layer completely covers a surface of the metal layer, and an edge of the alloy layer is suspended beyond an edge of the metal layer; and forming a mask layer above the alloy layer, wherein the mask layer is made of a transparent material.
Preferably, the substrate material is Si or GaAs.
Preferably, the material of the metal layer is Ge.
Preferably, the alloy layer material is GeSn.
Preferably, the transparent material is SiO2Or Si3N4A material.
By the invention, SiO is sputtered2A GeSn microdisk was prepared for the hard mask. Because of SiO2Is transparent, so SiO is not removed2In the case of (3), the test may be performed after the preparation. Wherein, SiO2The GeSn microdisk has a supporting effect and can easily obtain an ultrathin (up to 10nm) GeSn microdisk with strain release.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a substrate, depositing a metal layer above the substrate, and depositing an alloy layer above the metal layer; depositing a mask layer above the alloy layer, wherein the mask layer is made of a transparent material; forming a patterned photoresist over the mask layer; performing a first dry etching process to remove part of the mask layer; performing a second dry etching process to remove a part of the metal layer and the alloy layer; removing the photoresist; and carrying out a third dry etching process to remove the part of the residual metal layer, so that the part of the alloy layer covers the metal layer, and the edge of the alloy layer exceeds the edge of the metal layer and is in a suspension state.
Preferably, the first dry etching process includes using CF4Chlorine is used as etching gas for dry etching.
Preferably, the second dry etching process includes dry etching using chlorine gas as an etching gas.
Preferably, the third dry etching process includes using CF4And O2And etching with etching gas to perform dry etching.
According to an aspect of the present invention, there is provided an electronic apparatus including an integrated circuit formed of the above semiconductor device.
Preferably, the electronic device further comprises: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-7 show a flow chart for fabricating a semiconductor device according to a disclosed embodiment of the invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact.
Furthermore, spatial relationship terms, such as "below", "lower", "above", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.
Fig. 1-6 show a flow chart of a method of manufacturing a semiconductor device according to a disclosed embodiment of the invention.
In this embodiment, the semiconductor device includes: a substrate 101; a metal layer 102 formed over the substrate; an alloy layer 103 formed over the metal layer, wherein the alloy layer completely covers the surface of the metal layer, and an edge of the alloy layer is suspended beyond the edge of the metal layer; a mask layer 104 is formed over the alloy layer, the mask layer 104 being a transparent material.
A substrate 101. In the present embodiment, as shown in fig. 1, the substrate 101 is a bulk silicon semiconductor substrate. Further, the substrate 101 may be a substrate of various forms including, but not limited to, a silicon-on-semiconductor Substrate (SOI), a compound semiconductor substrate (e.g., a GaAs substrate), an alloy semiconductor substrate (e.g., a SiGe substrate), and the like. In some embodiments, the semiconductor substrate may include a doped epitaxial layer.
Continuing with fig. 1, a metal layer 102 is formed over the substrate 101. A metal layer 102 is deposited on the substrate 101. In some embodiments, metal layer 102 comprises Ge element. In some embodiments, the metal layer 102 is formed by any of a variety of deposition techniques, including Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and other suitable deposition techniques.
And an alloy layer 103 formed over the metal layer 102, wherein the alloy layer 103 completely covers the surface of the metal layer 102, and an edge of the alloy layer 103 is suspended beyond an edge of the metal layer 102. The forming of the suspended alloy layer comprises the following process methods:
in the present embodiment, as shown in fig. 1, an alloy layer 103 is formed over the metal layer 102. The alloy layer 103 uses GeSn material. In some embodiments, alloy layer 103 may be formed using LPCVD, APCVD, PECVD, PVD, or sputtering.
As shown in fig. 2, a mask layer 104 is formed over the alloy layer 103. The mask layer 104 may be a hard mask layer formed of a transparent material, for example, SiO2、Si3N4Etc. a transparent material. Specifically, the mask layer 104 is formed by using a low-temperature sputtering method, wherein the low temperature is not more than 300 ℃, and the thickness of the transparent mask layer 104 is not more than 200 nanometers.
In the present embodiment, as shown in fig. 3, a patterned photoresist 105 is formed over the mask layer 104. The photoresist may be formed by a conventional method, for example, a photoresist may be spin-coated on a mask layer, and then a desired shape of the photoresist may be finally formed through exposure, development and removal steps. Other methods of forming patterned photoresist may also be employed. The photoresist and underlying material are then dry etched.
As shown in fig. 4, a first dry etching process is performed to remove a portion of the mask layer 104, and the mask layer 104 under the photoresist 105 remains. Etching with common Inductively Coupled Plasma (ICP) etcher, wherein the first dry etching adopts CF4(ii) a The gas pressure is controlled at 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 400W, and the lower radio frequency power is 100W, CF4The total flow rate of (3) is 50 sccm.
And a second dry etching process is performed to remove part of the metal layer 102 and the alloy layer 103 as shown in fig. 5. And etching by using a common Inductively Coupled Plasma (ICP) etching machine, wherein the secondary dry etching process adopts chlorine, the air pressure is controlled to be 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 300W, the lower radio frequency power is 45W, and the total flow of the chlorine is 35 sccm.
As shown in fig. 6, the photoresist 105 is removed. The photoresist 105 may be removed by a dry stripping process.
As shown in fig. 7, a third dry etching process is performed to remove a portion of the remaining metal layer 102, such that the alloy layer 103 partially covers the metal layer 102, and an edge of the alloy layer 103 exceeds an edge of the metal layer 102 and is in a suspended state. Etching with common Inductively Coupled Plasma (ICP) etcher, wherein the third dry etching process adopts CF4+O2The gas pressure is controlled at 90mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 200W, and the lower radio frequency power is 0W, CF4/O2Has a total flow rate of 100sccm, wherein CF is used4/O2In volume percent, CF4Volume ratio of 70%, O2The volume ratio is 30%.
In general, the disclosed method produces GeSn thin film suspended microdisk by low temperature sputter deposition of a mask layer of transparent material on an alloy layer (i.e., GeSn). The GeSn film suspension micro-disk is characterized in that the mask layer is made of a transparent material, the transparent mask layer is arranged on the GeSn film suspension micro-disk, the performance of the GeSn film suspension micro-disk cannot be affected, after the mask layer acts on the GeSn film suspension micro-disk, the situation that the edge of the etched GeSn film suspension micro-disk bends and upwarps due to stress release can be avoided, a supporting effect can be generated on the GeSn film suspension micro-disk, and the problem that the thin GeSn film suspension micro-disk with high Sn components is difficult to manufacture directly through selective etching in the prior art is solved. In addition, when the mask layer film is prepared by sputtering the transparent material at low temperature, the stress of the prepared mask layer is small, and other stresses cannot be additionally introduced to the GeSn film suspension micro-disk, so that the measurement of the subsequent performance of the GeSn film suspension micro-disk is influenced.
According to an embodiment of the present invention, there is also provided a method of manufacturing a semiconductor device. The method comprises the following steps:
s1: forming a substrate, depositing a metal layer above the substrate, and depositing an alloy layer above the metal layer;
in this step, a metal layer 102 is deposited on the substrate 101, and an alloy layer 103 is deposited over the metal layer 102, and any one of various deposition techniques including Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and other suitable CVD epitaxial techniques may be selected to form the metal layer 102 and the alloy layer 103.
S2: depositing a mask layer above the alloy layer, wherein the mask layer is made of a transparent material;
in this step, the mask layer 104 is also formed using a method specifically using low-temperature sputtering. Specifically, the mask layer 104 is formed by using a low-temperature sputtering method, wherein the low temperature is not more than 300 ℃, and the thickness of the transparent mask layer 104 is not more than 200 nanometers. In some embodiments, a 100 nm thick SiO layer is prepared by low temperature sputtering at 300 ℃ over the alloy layer 1032And (5) masking the layer. In other embodiments, SiO with a thickness of 30 nm is prepared by low temperature sputtering at 200 ℃ above the alloy layer 1032And (5) masking the layer. Of course, the temperature of the low-temperature sputtering can be any temperature such as 120-200 ℃, and the formed SiO2Mask layer or Si3N4The mask layer is a transparent hard mask layer, and the thickness of the mask layer is as thin as possible, for example, the thickness of the mask layer may be 20 nm to 100 nm, and the thickness of the mask layer is determined by that after the mask layer acts on the alloy layer (i.e., GeSn thin film layer), the edge of the alloy layer is not bent and upwarps when the mask layer and the alloy layer (i.e., GeSn thin film layer) are etched together, and the mask layer is easy to support.
S3: forming a patterned photoresist over the mask layer;
in this step, a photoresist may be formed by a conventional method, for example, a photoresist may be spin-coated on a mask layer, and then a desired shape of the photoresist may be finally formed through exposure, development, and removal steps. Other methods of forming patterned photoresist may also be employed. The photoresist and underlying material are then dry etched.
S4: carrying out a first dry etching process to remove part of the mask layer;
in this step, a general Inductively Coupled Plasma (ICP) etcher is used for etching, whichIn the first dry etching, CF is adopted4The gas pressure is controlled at 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 400W, and the lower radio frequency power is 100W, CF4The total flow rate of (3) is 50 sccm.
S5: performing a second dry etching process to remove part of the metal layer and the alloy layer;
in the step, a common Inductively Coupled Plasma (ICP) etching machine is adopted for etching, wherein the secondary dry etching process adopts chlorine, the gas pressure is controlled to be 5mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 300W, the lower radio frequency power is 45W, and the total flow of the chlorine is 35 sccm.
S6: removing the patterned photoresist;
in this step, the patterned photoresist 105 may be removed by a dry stripping process.
S7: and carrying out a third dry etching process to remove the part of the residual metal layer again, so that the part of the alloy layer covers the metal layer, and the edge of the alloy layer exceeds the edge of the metal layer and is in a suspension state.
In the step, a common Inductively Coupled Plasma (ICP) etching machine is adopted for etching, wherein CF is adopted for the third dry etching process4+O2The gas pressure is controlled at 90mT, the reaction temperature of the mixed gas is 20 ℃, the upper radio frequency power is 200W, and the lower radio frequency power is 0W, CF4/O2Has a total flow rate of 100sccm, wherein CF is used4/O2In volume percent, CF4Volume ratio of 70%, O2The volume ratio is 30%.
In the preparation method, the GeSn microdisk with a thin high Sn component can be directly manufactured by selective etching under the etching process condition by controlling the three-time dry etching process condition, the GeSn film suspension microdisk prepared by the method has the advantages of thin thickness which can reach 10 to 20 nanometers, and can overcome the problems of bending and upwarping of the edge of the GeSn film suspension microdisk with the thin high Sn component and difficult support in the prior art after the GeSn film suspension microdisk coacts with the transparent material, and the preparation method has a remarkable beneficial effect.
The components of several embodiments are discussed above so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (11)
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