CN105990419A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN105990419A
CN105990419A CN201610149806.6A CN201610149806A CN105990419A CN 105990419 A CN105990419 A CN 105990419A CN 201610149806 A CN201610149806 A CN 201610149806A CN 105990419 A CN105990419 A CN 105990419A
Authority
CN
China
Prior art keywords
layer
gallium nitride
semiconductor device
epitaxial layer
nitride epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610149806.6A
Other languages
English (en)
Inventor
小林隆
林伯融
陈哲霖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HERMES GROUP CO Ltd
Hermes Epitek Corp
Original Assignee
HERMES GROUP CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HERMES GROUP CO Ltd filed Critical HERMES GROUP CO Ltd
Publication of CN105990419A publication Critical patent/CN105990419A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material

Abstract

一种半导体装置包含:一基板、一缓冲层、及一装置层。缓冲层沉积于基板上,且包括至少一氮化镓磊晶层及沉积于氮化镓磊晶层上的至少一插入层,其中一电子捕捉元素被掺杂入氮化镓磊晶层的一区域,该区域是为邻近该氮化镓磊晶层及其上的插入层之间的一介面。装置层则形成于缓冲层之上。借由上述结构,氮化镓磊晶层的电子被捕捉,而降低电子迁移率,并使得来自缓冲层漏电流被抑制,因此半导体装置的性能也就被提升。本发明亦揭露一种制造上述半导体装置的方法。

Description

半导体装置及其制造方法
【技术领域】
本发明是关于一种半导体装置及其制造方法,尤其是一种较低漏电流的半导体装置及其制造方法。
【背景技术】
在高功率及高频的应用领域,高电子迁移率晶体管(High Electron MobilityTransistor,HEMT)是常见的构造。HEMT构造会产生高电子迁移率的区域,该多个高迁移率的电子可提供非常优越的高频表现。
氮化铝镓/氮化镓(AlGaN/GaN)构造是非常普遍的HEMT装置。其原因首先在于AlGaN/GaN的异质介面能产生二维电子气(2 Dimensional Electron Gas,2DEG)。二维电子气是一种以较高迁移率自由移动的电子气体。氮化铝镓是做为壁障层,而氮化镓则是做为通道层。其次是GaN材料具有高能隙,高崩溃电压,高电子迁移率,高热传导率等特征。氮化铝镓是做为壁障层,而氮化镓则是做为通道层。
可以知道的是,高电子迁移率装置通常需要具有相对较高电阻的半绝缘基板,且功率装置需要较厚的氮化镓磊晶层以提高崩溃电压。基于成长较厚氮化镓磊晶层于硅基板的需要,许多种缓冲层被安插于氮化镓磊晶层及硅基板之间,例如转换层、插入层、或超晶格构造。然而该多个缓冲层会在功率装置产生严重的漏电流问题。于是如何抑制磊晶层的漏电流现象已成为一个重要的议题。
【发明内容】
本发明是关于一种半导体装置及其制造方法,其植入电子捕捉元素于基板及装置层之间的缓冲层,以防止不想要的二维电子气体在缓冲层产生,借此以抑制经由二维电子气体产生的漏电流。
于一实施例中,本发明的半导体装置包含:一基板、一缓冲层、及一装置层。缓冲层是沉积于基板上,且包括至少一氮化镓磊晶层及至少一插入层。插入层是沉积于氮化镓磊晶层之上。氮化镓磊晶层及其上的插入层间有一介面,且氮化镓磊晶层在邻近此介面的区域被植入一电子捕捉元素。装置层则形成于缓冲层上。
在又一实施例中,本发明的半导体装置的制造方法包含:提供一基板;形成一缓冲层于基板上,其中缓冲层包括至少一氮化镓磊晶层及至少一沉积于氮化镓磊晶层上的插入层,且其中氮化镓磊晶层及其上的插入层间有一介面,且氮化镓磊晶层在邻近此介面的区域被植入一电子捕捉元素;及形成一装置层于缓冲层上。
本发明的实施例将配合图示详述于下,借此以使本发明的目的、技术内容、特征及优点更易于了解。
【附图说明】
图1是依本发明一第一实施例的一半导体装置的一示意图。
图2是依本发明一第二实施例的一半导体装置的一示意图。
图3是依本发明一第三实施例的一半导体装置的一示意图。
图4是依本发明一第四实施例的一半导体装置的一示意图。
图5是依本发明一实施例的一半导体装置制造方法的流程图。
【符号说明】
10 基板
20 缓冲层
21 初始层
22 氮化镓磊晶层
221 电子捕捉元素
23 插入层
30 装置层
31 通道层
32 壁障层
33 电极层
2DEG 二维电子气
S51,S52,S53 步骤
【具体实施方式】
以下将详述本发明的各实施例,并配合图式作为例示。除了该多个详细说明的实施例外,本发明亦可广泛地施行于其它的实施例中,任何所述实施例的轻易替代、修改、等效变化都包含在本发明的范围内,本发明的范围是以专利申请范围为基础。在说明书的描述中,为了使读者对本发明有较完整的了解,提供了许多特定细节;然而,本发明能在省略部分或全部特定细节的前提下,仍可实施。此外,众所周知的步骤或元件并未描述于细节中,以避免对本发明形成不必要的限制。图式中相同或类似的元件将以相同或类似符号来表示。需特别注意的是,图式仅为示意之用,并非代表元件实际的尺寸或数量,有些细节可能未完全绘出,以求图式的简洁。
请参照图1。于一实施例中,本发明的半导体装置包含:一基板10、一缓冲层20、及一装置层30。于一实施例中,基板10包含但不限于一硅(Si)基板、一碳化硅(SiC)基板、或一蓝宝石(sapphire)基板。缓冲层20沉积于基板20上。缓冲层20可改善基板10及装置层30之间晶格结构不匹配的问题。为了要成长较厚的磊晶层于基板10上,例如成长较厚的氮化镓磊晶层于硅基板上,缓冲层是必要的。装置层30形成于缓冲层上,以实施此半导体装置的功能。于一实施例中,装置层30包括一通道层31、一壁障层32、及一电极层33。电极层33更包括一源极电极、一栅极电极、及一漏极电极。装置层30的详细构造及材料组成可由已知技术实现,在此不再赘述。
缓冲层20包含至少一氮化镓磊晶层22及至少一沉积于氮化镓磊晶层22上的插入层23。在图1的实施例中,依序自基板10至装置层30,缓冲层20包括一初始层21、多个氮化镓磊晶层22、及多个插入层23,其中多个插入层23及多个氮化镓磊晶层22以交错的方式沉积。于一实施例中,初始层21为一氮化铝(AlN)层;插入层23为一氮化铝或氮化铝镓(AlGaN)层。
承上,在上述结构中,不想要的二维电子气(2DEG)会在氮化镓磊晶层22及其上的插入层23间的介面产生,此会在功率装置造成严重的漏电流问题。于是本发明在氮化镓磊晶层22邻近此介面的一区域植入一种电子捕捉元素221。掺杂在氮化镓磊晶层22的电子捕捉元素221会取代氮化镓磊晶层22的镓或氮原子,而会形成深层受体(deep acceptor)以捕捉氮化镓磊晶层22内的电子,于是不想要的二维电子气就不会形成,而借由二维电子气发生的漏电流也就被抑制。于一实施例中,电子捕捉元素221为铁(Fe)、碳(C)、及镁(Mg)的至少其中之一,较佳者为铁。以氮化镓磊晶层22及其上的插入层23间的介面为基准,有掺杂电子捕捉元素的氮化镓磊晶层22的厚度大于5nm,较佳者氮化镓磊晶层22的厚度大于10nm。于一实施例中,掺杂的电子捕捉元素的其浓度是介于1016至1019cm-3之间。
接续上述,在图1的实施例,电子捕捉元素221是掺杂在最上面一层的氮化镓磊晶层22的一区域,此一区域邻近此氮化镓磊晶层22及其上的插入层23间的介面,但本发明并不限于此。在图2的实施例,每一邻接氮化镓磊晶层22及其上层插入层23间介面的氮化镓磊晶层22都有掺杂电子捕捉元素221,以增加抑制漏电流的效果。
请参考图3。于一实施例中,插入层23,在靠近其本身及其下的氮化镓磊晶层22的介面之处,亦掺杂电子捕捉元素221。也就是说,掺杂有电子捕捉元素221的区域跨越氮化镓磊晶层22及其上的插入层23的介面。要注意的是,电子捕捉元素221也可以掺杂于最上面一层的插入层23,或是每一层的插入层23。请参考图4,于一实施例中,电子捕捉元素221是掺杂于缓冲层20的每一层沉积层,例如起始层21、氮化镓磊晶层22、及插入层23。
借由上述结构,掺杂于缓冲层20的电子捕捉元素221可以捕捉电子而降低电子迁移率,于是不想要的二维电子气就不会在氮化镓磊晶层22及其上的插入层23之间的介面产生,而漏电流也在缓冲层20被抑制,因此半导体装置的性能也就被提升。
请参照图1及图5。于一实施例中,本发明提供一种半导体装置的制造方法。在步骤S51,首先提供一基板10,例如一硅基板、一碳化硅基板、或一蓝宝石基板。其次,在步骤S52,形成一缓冲层20于基板10上。如前所述,缓冲层20包括一初始层21,及多个以交错的方式沉积的氮化镓磊晶层22和插入层23。于一实施例中,氮化铝(AlN)层被形成而做为初始层21。初始层21是以一晶体成长方法形成,例如以一有机金属气相磊晶法(Metal Organic VaporPhase Epitaxy,MOVPE),配合一铝元素源气体(如三甲基铝(trimethylaluminum,TMA)气体)及一氮元素源气体(如阿摩尼亚(NH3)气体)的混合气体,形成初始层21。有机金属气相磊晶法,配合一镓元素源气体(如三甲基镓(trimethylgallium,TMG)气体)及一氮元素源气体(如阿摩尼亚(NH3)气体)的混合气体,亦可用于形成氮化镓磊晶层22。可以理解的是:在成长氮化镓磊晶层22时,使氮化镓磊晶层22通过电子捕捉元素221,可将电子捕捉元素221掺杂入氮化镓磊晶层22。于一实施例中,以二(环戊二烯)亚鐡(cyclopentadienyl iron,ferrocene,Cp2Fe)做为铁元素来源。插入层23形成的方法与初始层21相同。最后,在步骤S53,形成一装置层30于缓冲层20上,而完成如图1所示的半导体装置。装置层30的制造可由已知技术完成,在此不再赘述。
综上所述,本发明的半导体装置及其制造方法,利用掺杂电子捕捉元素于基板及装置层之间的缓冲层,以捕捉在氮化镓磊晶层的电子,而使电子迁移率降低。换言之,不想要的二维电子气不会在氮化镓磊晶层及其上插入层间的介面形成,亦即没有二维电子气可做为漏电流的路径。于是半导体装置的效能就被提升。
本发明已借由实施例详述于上。然而,习于此项技术者应当理解:本发明尚有各种替代、修改、等效的实施例。是故,本发明并不受限于本说明书所使用的实施例,而仅受限于所附的申请专利范围。

Claims (22)

1.一半导体装置,其特征在于,其包含:
一基板;
一缓冲层,沉积于该基板上,且包括至少一氮化镓磊晶层及沉积于该氮化镓磊晶层上的至少一插入层,其中一电子捕捉元素被掺杂入该氮化镓磊晶层的一区域,该区域是邻近该氮化镓磊晶层及其上的该插入层之间的一介面;及
一装置层,形成于该缓冲层之上。
2.如权利要求1的半导体装置,其特征在于,该电子捕捉元素被掺杂入该插入层的一区域,该区域是邻近该插入层及其下的该氮化镓磊晶层之间的一介面。
3.如权利要求1的半导体装置,其特征在于,该缓冲层包括多个该氮化镓磊晶层、及多个该插入层,且其中多个该插入层及多个该氮化镓磊晶层以交错的方式沉积,且其中该电子捕捉元素被掺杂入每一该氮化镓磊晶层的一区域,该区域是邻近该氮化镓磊晶层及其上的该插入层之间的一介面。
4.如权利要求1的半导体装置,其特征在于,该缓冲层包括以交错的方式沉积的多个该氮化镓磊晶层及多个该插入层,且其中该电子捕捉元素被掺杂入每一该插入层的一区域,该区域是邻近该插入层及其下的该氮化镓磊晶层之间的一介面。
5.如权利要求1的半导体装置,其特征在于,该缓冲层包括多个沉积层,该多个沉积层更包括多个该氮化镓磊晶层及多个该插入层,且其中该电子捕捉元素被掺杂入每一该沉积层。
6.如权利要求1的半导体装置,其特征在于,掺杂有该电子捕捉元素的该氮化镓磊晶层的厚度大于5nm。
7.如权利要求1的半导体装置,其特征在于,该电子捕捉元素包含铁(Fe)、碳(C)、及镁(Mg)的至少其中之一。
8.如权利要求1的半导体装置,其特征在于,该插入层包含氮化铝(AlN)或氮化铝镓(AlGaN)。
9.如权利要求1的半导体装置,其特征在于,该缓冲层更包括沉积于该基板上的一初始层,且该氮化镓磊晶层沉积于该初始层上。
10.如权利要求9的半导体装置,其特征在于,该初始层包含氮化铝(AlN)。
11.如权利要求1的半导体装置,其特征在于,该基板为一硅(Si)基板、一碳化硅(SiC)基板、或一蓝宝石(sapphire)基板。
12.一种半导体装置的制造方法,其特征在于,其包含:
提供一基板;
形成一缓冲层于该基板上,其中该缓冲层包括至少一氮化镓磊晶层及沉积于该氮化镓磊晶层上的至少一插入层,且其中一电子捕捉元素被掺杂入该氮化镓磊晶层的一区域,该区域是邻近该氮化镓磊晶层及其上的该插入层之间的一介面;及
形成一装置层于该缓冲层上。
13.如权利要求12的半导体装置的制造方法,其特征在于,该电子捕捉元素被掺杂入该插入层的一区域,该区域是邻近该插入层及其下的该氮化镓磊晶层之间的一介面。
14.如权利要求12的半导体装置的制造方法,其特征在于,该缓冲层包括以交错的方式沉积的多个该氮化镓磊晶层及多个该插入层,且其中该电子捕捉元素被掺杂入每一该氮化镓磊晶层的一区域,该区域是邻近该氮化镓磊晶层及其上的该插入层之间的一介面。
15.如权利要求12的半导体装置的制造方法,其特征在于,该缓冲层包括以交错的方式沉积的多个该氮化镓磊晶层及多个该插入层,且其中该电子捕捉元素被掺杂入每一该插入层的一区域,该区域是邻近该插入层及其下的该氮化镓磊晶层之间的一介面。
16.如权利要求12的半导体装置的制造方法,其特征在于,该缓冲层包括多个沉积层,该多个沉积层更包含多个该氮化镓磊晶层及多个该插入层,且其中该电子捕捉元素被掺杂入每一该沉积层。
17.如权利要求12的半导体装置的制造方法,其特征在于,掺杂有该电子捕捉元素的该氮化镓磊晶层的厚度大于5nm。
18.如权利要求12的半导体装置的制造方法,其特征在于,该电子捕捉元素包含铁(Fe)、碳(C)、及镁(Mg)的至少其中之一。
19.如权利要求12的半导体装置的制造方法,其特征在于,该插入层包含氮化铝(AlN)或氮化铝镓(AlGaN)。
20.如权利要求12的半导体装置的制造方法,其特征在于,该缓冲层更包含沉积于该基板上的一初始层,且该氮化镓磊晶层沉积于该初始层上。
21.如权利要求20的半导体装置的制造方法,其特征在于,该初始层包含氮化铝(AlN)。
22.如权利要求12的半导体装置的制造方法,其特征在于,该基板为一硅(Si)基板、一碳化硅(SiC)基板、或一蓝宝石(sapphire)基板。
CN201610149806.6A 2015-03-17 2016-03-16 半导体装置及其制造方法 Pending CN105990419A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/660,494 US20160276472A1 (en) 2015-03-17 2015-03-17 Semiconductor Device and Manufacturing Method Thereof
US14/660,494 2015-03-17

Publications (1)

Publication Number Publication Date
CN105990419A true CN105990419A (zh) 2016-10-05

Family

ID=56853351

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610149806.6A Pending CN105990419A (zh) 2015-03-17 2016-03-16 半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US20160276472A1 (zh)
JP (1) JP2016174153A (zh)
CN (1) CN105990419A (zh)
DE (1) DE102016103208A1 (zh)
TW (1) TW201707052A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847672A (zh) * 2017-03-03 2017-06-13 上海新傲科技股份有限公司 高击穿电压氮化镓功率材料的外延方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6812333B2 (ja) * 2017-12-08 2021-01-13 エア・ウォーター株式会社 化合物半導体基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007221001A (ja) * 2006-02-17 2007-08-30 Furukawa Electric Co Ltd:The 半導体素子
US20090236634A1 (en) * 2008-03-18 2009-09-24 Hitachi Cable, Ltd. Nitride semiconductor epitaxial wafer and nitride semiconductor device
CN103715245A (zh) * 2012-09-28 2014-04-09 富士通株式会社 半导体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014072429A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007221001A (ja) * 2006-02-17 2007-08-30 Furukawa Electric Co Ltd:The 半導体素子
US20090236634A1 (en) * 2008-03-18 2009-09-24 Hitachi Cable, Ltd. Nitride semiconductor epitaxial wafer and nitride semiconductor device
CN103715245A (zh) * 2012-09-28 2014-04-09 富士通株式会社 半导体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847672A (zh) * 2017-03-03 2017-06-13 上海新傲科技股份有限公司 高击穿电压氮化镓功率材料的外延方法

Also Published As

Publication number Publication date
JP2016174153A (ja) 2016-09-29
TW201707052A (zh) 2017-02-16
DE102016103208A1 (de) 2016-09-22
US20160276472A1 (en) 2016-09-22

Similar Documents

Publication Publication Date Title
Pu et al. Review of recent progress on vertical GaN-based PN diodes
JP5546514B2 (ja) 窒化物半導体素子及び製造方法
US9893188B2 (en) Semiconductor structure with template for transition metal dichalcogenides channel material growth
CN106233440B (zh) 半导体基板和半导体元件
JP2012033575A (ja) 半導体装置
JP6950185B2 (ja) 高電子移動度トランジスタの製造方法、高電子移動度トランジスタ
CN108140561A (zh) 半导体元件用外延基板、半导体元件和半导体元件用外延基板的制造方法
TW200937634A (en) Group iii nitride electronic device and group iii nitride semiconductor epitaxial substrate
JP2009049121A (ja) ヘテロ接合型電界効果トランジスタ及びその製造方法
JP2010232297A (ja) 半導体装置
JP5883331B2 (ja) 窒化物半導体エピタキシャルウェハの製造方法及び電界効果型窒化物トランジスタの製造方法
JP2012033645A (ja) 半導体装置
CN108807499A (zh) 半导体异质结构及其形成方法
US8637902B2 (en) Semiconductor device and method of manufacturing the same
CN105047695A (zh) 用于高电子迁移率晶体管的高阻衬底以及生长方法
JP6730301B2 (ja) 半導体素子用エピタキシャル基板の製造方法
CN105990419A (zh) 半导体装置及其制造方法
JP6811472B2 (ja) Iii族窒化物半導体素子の製造方法
JP2015185809A (ja) 半導体基板の製造方法及び半導体装置
TWI572036B (zh) Nitride crystal structure
JP6601938B2 (ja) Iii族窒化物半導体素子の製造方法
JP2012033708A (ja) 半導体装置の製造方法
JP2010045416A (ja) Iii族窒化物電子デバイス
JP5664262B2 (ja) 電界効果型トランジスタ及び電界効果型トランジスタ用エピタキシャルウエハ
JP6516483B2 (ja) Iii族窒化物半導体素子とその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20161005