CN105990338A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105990338A
CN105990338A CN201510555759.0A CN201510555759A CN105990338A CN 105990338 A CN105990338 A CN 105990338A CN 201510555759 A CN201510555759 A CN 201510555759A CN 105990338 A CN105990338 A CN 105990338A
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河野洋志
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Toshiba Corp
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Abstract

本发明提供一种能够抑制误触发的半导体装置。实施方式的半导体装置包括单元区域、栅极配线区域、及设置在单元区域与栅极配线区域之间的米勒箝位电路区域，且米勒箝位电路区域具有：SiC基板，具备第一面与第二面；n型第一源极区域，设置在SiC基板内的第一面；n型第一漏极区域；第一栅极绝缘膜；第一栅电极；p型第二源极区域，设置在SiC基板内的第一面，且电连接于第一源极区域；p型第二漏极区域；第二栅极绝缘膜；以及第二栅电极，与第一栅电极电连接；单元区域具有：n型第一SiC区域，设置在SiC基板内的第一面，且电连接于第二漏极区域；p型第二SiC区域；n型第三SiC区域；第三栅极绝缘膜；以及第三栅电极，电连接于第一源极区域及第二源极区域。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2015-52278号(申请日：2015年3月16日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
作为下一代半导体元件用的材料，期待SiC(碳化硅)。SiC与Si(硅)相比，具有带隙为3倍、击穿电场强度约为10倍、及导热率约为3倍的优异物性。如果有效利用该特性，那么能够实现低损耗且能进行高温动作的半导体元件。
例如，使用SiC的MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)与使用Si的双极性元件相比，能够实现低的接通电阻、快的开关速度。因此，例如作为倒相电路的开关元件而发挥优异的性能。
倒相电路中存在误触发这一问题，误触发是因dV/dt变大而导致断开侧的开关元件的栅极电位上升，从而开关元件意外地进行接通动作。为了抑制误触发，有如下方法：使用米勒箝位电路(Miller Clamp Circuit)，在开关元件断开时使栅极与源极间短路，从而抑制栅极电位上升。
发明内容
本发明提供一种能够抑制误触发的半导体装置。
实施方式的半导体装置包括单元区域、栅极配线区域、以及设置在所述单元区域与所述栅极配线区域之间的米勒箝位电路区域，且所述米勒箝位电路区域具有：SiC衬底，具备第一面与第二面；n型第一源极区域，设置在所述SiC衬底内的所述第一面；n型第一漏极区域，设置在所述SiC衬底内的所述第一面；第一栅极绝缘膜，设置在所述第一源极区域与所述第一漏极区域之间的所述第一面上；第一栅电极，设置在所述第一栅极绝缘膜上；p型第二源极区域，设置在所述SiC衬底内的所述第一面，且电连接于所述第一源极区域；p型第二漏极区域，设置在所述SiC衬底内的所述第一面；第二栅极绝缘膜，设置在所述第二源极区域与所述第二漏极区域之间的所述第一面上；以及第二栅电极，设置在所述第二栅极绝缘膜上，且与所述第一栅电极电连接；所述单元区域具有：n型第一SiC区域，设置在所述SiC衬底内的所述第一面，且电连接于所述第二漏极区域；p型第二SiC区域，设置在所述第一SiC区域与所述第二面之间；n型第三SiC区域，设置在所述第二SiC区域与所述第二面之间；第三栅极绝缘膜，设置在所述第二SiC区域上；以及第三栅电极，设置在所述第三栅极绝缘膜上，且电连接于所述第一源极区域及所述第二源极区域。
附图说明
图1是实施方式的半导体装置的布局图。
图2是实施方式的半导体装置的电路图。
图3是实施方式的半导体装置的示意剖视图。
具体实施方式
以下，一边参照附图，一边对本发明的实施方式进行说明。此外，在以下的说明中，对相同的部件标注相同的符号，对于已经说明过一次的部件等，适当省略其说明。
而且，在以下的说明中，n+、n、n-及p+、p、p-的表述表示各导电型中的杂质浓度的相对高低。也就是说n+表示n型杂质浓度较n相对较高，n-表示n型杂质浓度较n相对较低。而且，p+表示p型杂质浓度较p相对较高，p-表示p型杂质浓度较p相对较低。此外，也存在将n+型、n-型简记作n型，将p+型、p-型简记作p型的情况。
杂质浓度例如能够通过SIMS(Secondary Ion Mass Spectrometry，二次离子质谱法)来测定。而且，杂质浓度的相对高低例如也能够根据以SCM(Scanning CapacitanceMicroscopy，扫描电容显微术)求出的载子浓度的高低来判断。
本说明书中，所谓“SiC衬底”，是也包含例如通过外延生长而形成在衬底上的SiC层的概念。
本实施方式的半导体装置包括单元区域、栅极配线区域、以及设置在单元区域与栅极配线区域之间的米勒箝位电路区域，且米勒箝位电路区域具有：SiC衬底，具备第一面与第二面；n型第一源极区域，设置在SiC衬底内的第一面；n型第一漏极区域，设置在SiC衬底内的第一面；第一栅极绝缘膜，设置在第一源极区域与第一漏极区域之间的第一面上；第一栅电极，设置在第一栅极绝缘膜上；p型第二源极区域，设置在SiC衬底内的第一面，且电连接于第一源极区域；p型第二漏极区域，设置在SiC衬底内的第一面；第二栅极绝缘膜，设置在第二源极区域与第二漏极区域之间的第一面上；以及第二栅电极，设置在第二栅极绝缘膜上，且与第一栅电极电连接；单元区域具有：n型第一SiC区域，设置在SiC衬底内的第一面，且电连接于第二漏极区域；p型第二SiC区域，设置在第一SiC区域与第二面之间；n型第三SiC区域，设置在第二SiC区域与第二面之间；第三栅极绝缘膜，设置在第二SiC区域上；以及第三栅电极，设置在第三栅极绝缘膜上，且电连接于第一源极区域及第二源极区域。
图1是本实施方式的半导体装置的布局图。本实施方式的半导体装置是使用SiC的纵型MOSFET。
图1是从上表面观察本实施方式的MOSFET100时的布局图。MOSFET100是使用SiC衬底10而形成。MOSFET100包括单元区域100a、栅极配线区域100b、米勒箝位电路区域100c、基准配线区域100d、以及终端区域100e。
单元区域100a是供纵型MOSFET的多个单元有规则地排列的区域。各单元的形状、配置并无特别限定。
栅极配线区域100b具备传输栅极信号的栅极信号配线(第一栅极配线)1及传输栅极电压的高电平的栅极电压配线(第二栅极配线)2。
米勒箝位电路区域100c设置在单元区域100a与栅极配线区域100b之间。在米勒箝位电路区域100c中，使用n型MOSFET与p型MOSFET构成米勒箝位电路。
基准配线区域100d是与米勒箝位电路区域100c之间隔着单元区域100a而设置。基准配线区域100d中具备基准配线3，该基准配线3用来撷取连接至MOSFET100外的栅极驱动电路的脉冲产生器的基准电位。
在MOSFET100的上表面具备源极电极(第一电极)4、栅极信号垫(第二电极)5、栅极电压垫(第三电极)6、以及基准电位垫(第四电极)7。在SiC衬底10上具备源极电极(第一电极)4、栅极信号垫(第二电极)5、栅极电压垫(第三电极)6、以及基准电位垫(第四电极)7。而且，在MOSFET100的下表面设置着未图示的漏极电极(第五电极)。
对源极电极4施加源极电压。对栅极信号垫5输入栅极信号。对栅极电压垫6施加栅极电压的高电平。从基准电位垫7输出安装在外部的栅极驱动电路的脉冲产生器的基准电位。对漏极电极施加漏极电压。
栅极信号垫5连接于栅极信号配线1。栅极电压垫6连接于栅极电压配线2。基准电位垫7连接于基准配线3。
终端区域100e设置在SiC衬底10的最外周部。沿着终端区域100e的内侧设置源极电极4。
图2是本实施方式的半导体装置的电路图。MOSFET100是在同一SiC衬底10上形成着SiC的纵型MOSFET(以下记作SiC-MOS)、与SiC的p型MOSFET(以下记作PMOS)及n型MOSFET(以下记作NMOS)。
SiC-MOS形成在单元区域100a。PMOS与NMOS形成在米勒箝位电路区域100c。
MOSFET100具备5个端子。5个端子为源极电极(Source：第一电极)4、栅极信号垫(Gate Signal：第二电极)5、栅极电压垫(Gate Voltage：第三电极)6、基准电位垫(Reference：第四电极)7、以及漏极电极(第五电极)8。源极电极4、栅极信号垫5、栅极电压垫6、基准电位垫7、漏极电极8为金属。
PMOS与NMOS是以各自的源极连接的方式直接连接。在PMOS与NMOS的双方的栅极连接栅极信号垫5。PMOS与NMOS的源极连接于SiC-MOS的栅极。SiC-MOS的栅极连接于基准电位垫7。
PMOS的漏极与SiC-MOS的源极连接于源极电极4。NMOS的漏极连接于栅极电压垫6。SiC-MOS的漏极连接于漏极电极8。
如果对栅极信号垫5施加高电平，那么NMOS将进行接通动作，PMOS进行断开动作。对SiC-MOS的栅极施加栅极电压的高电平而使SiC-MOS进行接通动作。
另一方面，如果对栅极信号垫5施加低电平，那么NMOS将进行断开动作，PMOS进行接通动作。SiC-MOS的栅极经由PMOS而与源极短路，从而SiC-MOS进行断开动作。
从基准电位垫7输出成为脉冲产生器的基准电位的SiC-MOS的栅极的栅极电位。
图3是本实施方式的半导体装置的示意剖视图。
MOSFET100是使用SiC衬底10而形成。MOSFET100是在同一SiC衬底10形成单元区域100a、栅极配线区域100b、米勒箝位电路区域100c、以及基准配线区域100d。
SiC衬底10具备第一面与第二面。图3中，第一面是SiC衬底10的上侧的面。而且，图3中，第二面是SiC衬底10的下侧的面。
MOSFET100在米勒箝位电路区域100c包括n型第一源极区域12、n型第一漏极区域14、第一栅极绝缘膜16、第一栅电极18、p型第二源极区域20、p型第二漏极区域22、第二栅极绝缘膜24、第二栅电极26、p型第一井区域28、及n型第二井区域30。
MOSFET100在单元区域包括n+型源极区域(第一SiC区域)32、p型基底区域(第二SiC区域)34、n-型漂移区域(第三SiC区域)36、n+型漏极区域(第四SiC区域)38、第三栅极绝缘膜40、及第三栅电极42。
通过未图示的欧姆接点对p型第一井区域28及p型基底区域34施加电位。欧姆接点设置在未图示的p+区域上。通过未图示的欧姆接点对n型第二井区域30施加电位。欧姆接点设置在未图示的n+区域上。
MOSFET100在栅极配线区域100b具备栅极信号配线(第一栅极配线)1、栅极电压配线(第二栅极配线)2、及场氧化膜44。在栅极配线区域100b设置p型第一井区域28。
MOSFET100在基准配线区域100d具备基准配线3及场氧化膜46。在基准配线区域100d设置p型第一井区域28。
MOSFET100在第一面侧具备源极电极(Source：第一电极)4、栅极信号垫(GateSignal：第二电极)5、栅极电压垫(Gate Voltage：第三电极)6、以及基准电位垫(Reference：第四电极)7。而且，具备与第二面相接的漏极电极(第五电极)8。
第一源极区域12、第一漏极区域14设置在第一面。第一栅极绝缘膜16设置在第一源极区域12与第一漏极区域14之间的第一面上。第一栅电极18设置在第一栅极绝缘膜16上。第一源极区域12、第一漏极区域14、及第一栅电极18成为NMOS的构成要素。
第一栅极绝缘膜16设置在第一井区域28上。第一井区域28设置在第一栅电极18与漂移区域36之间。第一井区域28连接于基底区域34。
第二源极区域20、第二漏极区域22设置在第一面。第二栅极绝缘膜24设置在第二源极区域20与第二漏极区域22之间的第一面上。第二栅电极26设置在第二栅极绝缘膜24上。第二源极区域20、第二漏极区域22、及第二栅电极26成为PMOS的构成要素。
第二栅极绝缘膜24设置在第二井区域30上。第二井区域30设置在第二栅电极26与第一井区域28之间。
就抑制米勒箝位电路中的锁定的观点而言，较理想的是单元区域的基底区域34的深度比第一井区域28的深度深。单元区域的耐受电压下降，从而抑制锁定。而且，就抑制锁定的观点而言，优选为满足米勒箝位电路区域的第一井区域28的深度≦栅极配线区域的第一井区域28的深度≦基准配线区域的第一井区域28的深度﹤单元区域的基底区域34的深度的关系。
第二源极区域20电连接于第一源极区域12。而且，第二栅电极26电连接于第一栅电极18。
源极区域32设置在第一面。基底区域34设置在源极区域32与第二面之间。漂移区域36设置在基底区域34与第二面之间。漏极区域38设置在第二面。第三栅极绝缘膜40设置在基底区域34上。第三栅电极42设置在第三栅极绝缘膜40上。源极区域32、基底区域34、漂移区域36、漏极区域38、第三栅极绝缘膜40、及第三栅电极42成为SiC-MOS的构成要素。
源极区域32电连接于第二漏极区域22。源极区域32及第二漏极区域22连接于源极电极4。第三栅电极42电连接于第一源极区域12及第二源极区域20。
栅极信号配线1及栅极电压配线2设置在场氧化膜44上。栅极信号配线1及栅极电压配线2例如为金属。
栅极信号配线1将栅极信号垫5与第一栅电极18及第二栅电极26电连接。栅极电压配线2将栅极电压垫6与第一漏极区域14电连接。
基准配线3设置在场氧化膜46上。基准配线3将基准电位垫7与第三栅电极42电连接。
关于用于NMOS、PMOS、SiC-MOS、栅极信号配线1、栅极电压配线2、基准配线3各自之间的电连接的构造，省略了图示。各自之间的电连接能够通过使用层间绝缘膜的多层配线而实现。例如，能够使用利用了金属或硅化物的接点构造与金属配线层、多晶硅配线层、硅化物层而实现。层间绝缘膜例如可使用氧化膜或低介电常数材料。
接下来，对本实施方式的作用及效果进行说明。
例如，在将MOSFET用作倒相电路的开关元件的情况下，存在为了抑制误触发而将具备米勒箝位电路的元件连接在栅极驱动电路与MOSFET之间的情况。通过使用米勒箝位电路而在MOSFET断开时使栅极与源极间短路，能够抑制误触发。
然而，如果在MOSFET的外部设置米勒箝位电路，那么会存在如下问题：例如，因MOSFET与米勒箝位电路间的配线电阻或配线寄生电感、MOSFET内的配线电阻或配线寄生电感的影响而导致栅极与源极间的短路产生延迟，从而无法使开关速度足够快。换句话说，存在无法增大倒相电路中的dV/dt的问题。特别是在根据材料特性而理论上能够实现较快的开关速度的SiC元件中，该问题出现更明显。
在本实施方式的MOSFET100中，将米勒箝位电路100c与构成单元区域100a的纵型MOSFET设置在同一SiC衬底10上。进而将米勒箝位电路100c设置在单元区域100a与栅极配线区域100b之间的单元附近。因此，因MOSFET与米勒箝位电路间的配线电阻或配线寄生电感、MOSFET内的配线电阻或配线寄生电感的影响而导致的遅延被抑制。由此，在用作倒相电路的开关元件的情况下，能够实现如下一种MOSFET100：能够缩短MOSFET断开时的栅极与源极间的短路时间，从而能抑制误触发。
在实施方式中，以MOSFET为例进行了说明，但本发明也能应用于IGBT(InsulatedGate Bipolar Transistor，绝缘栅双极型晶体管)。在应用于IGBT的情况下，作为元件的构造，只要将MOSFET100的n+型漏极区域(第四SiC区域)38替换为p+型集极区域即可。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些新颖的实施方式能以其他各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。例如，也可以将一实施方式的构成要素与其他实施方式的构成要素进行替换或变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 栅极信号配线(第一栅极配线)
2 栅极电压配线(第二栅极配线)
3 基准配线
4 源极电极(第一电极)
5 栅极信号垫(第二电极)
6 栅极电压垫(第三电极)
7 基准电位垫(第四电极)
8 漏极电极(第五电极)
10 SiC衬底
12 n型第一源极区域
14 n型第一漏极区域
16 第一栅极绝缘膜
18 第一栅电极
20 p型第二源极区域
22 p型第二漏极区域
24 第二栅极绝缘膜
26 第二栅电极
28 p型第一井区域
30 n型第二井区域
32 n+型源极区域(第一SiC区域)
34 p型基底区域(第二SiC区域)
36 n-型漂移区域(第三SiC区域)
38 n+型漏极区域(第四SiC区域)
40 第三栅极绝缘膜
42 第三栅电极
100 MOSFET(半导体装置)

Claims (6)

1.一种半导体装置，其特征在于具备单元区域、栅极配线区域、以及设置在所述单元区域与所述栅极配线区域之间的米勒箝位电路区域，並且
所述米勒箝位电路区域具有：
SiC衬底，具备第一面与第二面；
n型第一源极区域，设置在所述SiC衬底内的所述第一面；
n型第一漏极区域，设置在所述SiC衬底内的所述第一面；
第一栅极绝缘膜，设置在所述第一源极区域与所述第一漏极区域之间的所述第一面上；
第一栅极电极，设置在所述第一栅极绝缘膜上；
p型第二源极区域，设置在所述SiC衬底内的所述第一面，且电连接于所述第一源极区域；
p型第二漏极区域，设置在所述SiC衬底内的所述第一面；
第二栅极绝缘膜，设置在所述第二源极区域与所述第二漏极区域之间的所述第一面上；以及
第二栅极电极，设置在所述第二栅极绝缘膜上，且与所述第一栅极电极电连接；
所述单元区域具有：
n型第一SiC区域，设置在所述SiC衬底内的所述第一面，且电连接于所述第二漏极区域；
p型第二SiC区域，设置在所述第一SiC区域与所述第二面之间；
n型第三SiC区域，设置在所述第二SiC区域与所述第二面之间；
第三栅极绝缘膜，设置在所述第二SiC区域上；以及
第三栅极电极，设置在所述第三栅极绝缘膜上，且电连接于所述第一源极区域及所述第二源极区域。
2.根据权利要求1所述的半导体装置，其特征在于进而具备：
第一电极，设置在所述第一面上，且电连接于所述第二漏极区域及所述第一SiC区域；
第二电极，设置在所述第一面上，且电连接于所述第一栅极电极及所述第二栅极电极；
第三电极，设置在所述第一面上，且电连接于所述第一漏极区域；
第四电极，设置在所述第一面上，且连接于所述第三栅极电极；以及
第五电极，与所述第二面相接而设置。
3.根据权利要求2所述的半导体装置，其特征在于进而具备：
第一栅极电极配线，设置在所述栅极配线区域，且将所述第二电极、所述第一栅极电极及所述第二栅极电极电连接；以及
第二栅极电极配线，设置在所述栅极配线区域，且将所述第三电极与所述第一漏极区域电连接。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于在所述第一栅极电极与所述第三SiC区域之间设置着连接于所述第二SiC区域的p型第一井区域。
5.根据权利要求4所述的半导体装置，其特征在于在所述第二栅极电极与所述第一井区域之间进而具备n型第二井区域。
6.根据权利要求1至3中任一项所述的半导体装置，其特征在于在所述SiC衬底的所述第二面进而具备n型杂质浓度高于所述第三SiC区域的第四SiC区域。
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