CN105957885A - 一种具有低导通电阻特性的槽栅mosfet器件 - Google Patents
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
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- 239000000377 silicon dioxide Substances 0.000 claims description 2
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- 230000015556 catabolic process Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 2
- 210000003850 cellular structure Anatomy 0.000 abstract 1
- 230000005611 electricity Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 7
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- 239000012535 impurity Substances 0.000 description 3
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- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical group [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
本发明涉及功率半导体器件技术领域，具体涉及到一种具有低导通电阻特性的槽栅MOSFET器件。其元胞结构相比于传统的槽栅型MOSFET器件的区别主要为，本发明的MOSFET器件在槽型栅电极底部具有厚绝缘介质层，且在厚绝缘介质层中引入正电荷，所述正电荷由Cs或其他具有正电性的材料通过淀积或离子注入的方式在厚绝缘介质层中形成。本发明提供的槽栅型MOSFET器件通过厚绝缘介质层中正电荷的引入，在保证相同击穿电压的基础上，大大减小了漂移区电阻，进而减小了器件导通电阻。
Description
技术领域
本发明涉及功率半导体器件技术领域，具体涉及到一种具有低导通电阻特性的槽栅MOSFET器件。
背景技术
功率MOSFET(Metal Oxide Semiconductor Field-Effect Transistor)的两个关键参数是击穿电压BV和导通电阻Ron。由于MOSFET器件属于单级型器件，其击穿电压与漂移区厚度和漂移区掺杂浓度有关，高的击穿电压需要厚的漂移区和低的漂移区掺杂浓度，这会使得其导通电阻Ron增加。导通电阻Ron和耐压BV之间存在关系：Ron∝BV2.3～2.6，即硅极限。因此，随着器件耐压增加，导通电阻成指数增长趋势，功耗大大增加。特别地，在典型的高压MOSFET器件中，器件的导通电阻主要由漂移区电阻决定。因此，在保持器件击穿电压性能的同时，降低漂移区电阻进而降低导通电阻具有重要的意义。
因此，在传统MOSFET结构的基础上，出现了一些改进结构。目前比较流行的方法是采用类似超结的结构，这种结构可从两个方面减小漂移区电阻。一方面，将承担阻断电压的空间电荷区从单一的垂直方向改变为垂直与水平两个方向，减小外延层厚度；另一方面，在保证超结MOSFET器件截止时空间电荷区多数载流子能耗尽的情况下，尽量提高漂移区载流子浓度，从而降低漂移区电阻率，减小导通电阻。但是，目前超结结构的制造工艺仍存在一定技术难度。
发明内容
本发明针对上述问题，提出一种具有低导通电阻特性的槽栅MOSFET器件。
本发明所采用的技术方案：一种具有低导通电阻特性的槽栅MOSFET器件，包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3、P型体区4和金属化源极13；所述P型体区4上层具有N+重掺杂源区5和P+接触区6，所述N+重掺杂源区5位于P+接触区6之间；其特征在于，还包括沟槽14，所述沟槽14从N+重掺杂源区5上表面中部，垂直向下依次贯穿N+重掺杂源区5和P型体区4延伸入N-漂移区3中；所述沟槽14的下部中填充有厚绝缘介质层10，沟槽14的上部中填充有栅氧化层8，所述厚绝缘介质层10与栅氧化层8之间通过隔离介质层9隔离；所述厚绝缘介质层10中具有正电荷区11，所述栅氧化层8中具有栅电极7；所述栅电极7的上表面及部分N+重掺杂源区5的上表面通过隔离介质12与金属化源极13隔离；P+接触区6的上表面与部分N+重掺杂源区5的上表面与金属化源极13接触。
进一步地，所述栅电极7可以是多晶硅或其他导电材料；所述绝缘介质层可以是二氧化硅或其他绝缘介质材料。所述正电荷11可由Cs或其他具有正电性的材料通过淀积或离子注入的方式在厚绝缘介质层10中形成。
本发明的有益效果为，本发明提供的槽栅MOSFET器件通过厚绝缘介质层中正电荷的引入，在保证相同击穿电压的基础上，大大减小了漂移区电阻，进而减小了器件导通电阻。
附图说明
图1是本发明的具有低导通电阻特性的槽栅MOSFET器件的元胞结构示意图；
图2是本发明的具有低导通电阻特性的槽栅MOSFET器件正向导通时电流路径示意图；
图3-图6是本发明的具有低导通电阻特性的槽栅MOSFET器件的制造工艺步骤示意图。
具体实施方式
下面结合附图，详细描述本发明的技术方案：
如图1所示，本发明的一种具有低导通电阻特性的槽栅MOSFET器件，包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N-漂移区3、P型体区4和金属化源极13；所述P型体区4上层具有N+重掺杂源区5和P+接触区6，所述N+重掺杂源区5位于P+接触区6之间；其特征在于，还包括沟槽14，所述沟槽14从N+重掺杂源区5上表面中部，垂直向下依次贯穿N+重掺杂源区5和P型体区4延伸入N-漂移区3中；所述沟槽14的下部中填充有厚绝缘介质层10，沟槽14的上部中填充有栅氧化层8，所述厚绝缘介质层10与栅氧化层8之间通过隔离介质层9隔离；所述厚绝缘介质层10中具有正电荷区11，所述栅氧化层8中具有栅电极7；所述栅电极7的上表面及部分N+重掺杂源区5的上表面通过隔离介质12与金属化源极13隔离；P+接触区6的上表面与部分N+重掺杂源区5的上表面与金属化源极13接触。
本发明的工作原理为：
(1)器件的正向导通
本发明所提供的具有低导通电阻特性的槽栅MOSFET器件，其正向导通时的电极连接方式为：栅电极7接正电位，金属化漏极1接正电位，金属化源极13接零电位。
当栅电极7施加的正偏电压达到阈值电压时，在P型体区4中靠近栅氧化层8的一侧形成反型沟道；此外，由于正电荷11的作用，在N-漂移区3中靠近厚绝缘介质层10的一侧形成一个垂直的电子积累区。此时，在漏极1的正向偏压下，电子作为载流子从N+重掺杂源区5经过P型体区4中的反型沟道，注入N-漂移区3，并到达漏极1形成正向电流，MOSFET器件导通，如图2所示。由于N-漂移区3中电子积累区的形成，为MOSFET器件中多子电流的流动提供了一条低阻通路，减小了导通电阻。
与传统沟槽型MOSFET器件相比，本发明中由于正电荷11产生的N-漂移区3中电子积累区，为MOSFET器件中多子电流的流动提供了一条低阻通路，漂移区电阻大大减小，进而减小了导通电阻。
(2)器件的阻断
本发明所提供的具有低导通电阻特性的槽栅MOSFET器件，其处于阻断状态时的电极连接方式为：栅电极7和金属化源极13短接且接零电位，金属化漏极1接正电位。
厚绝缘介质层10中引入的正电荷11的电荷密度需适当选择，以保证其电荷密度与N-漂移区3的施主杂质浓度基本相等，从而可以保证器件在阻断状态时的击穿电压。器件处于阻断状态时，漏极1施加正偏压，N-漂移区开始耗尽。由于耗尽层中的电离后的施主杂质与厚绝缘介质层10中的电荷均带正电且电荷密度相当，耗尽线均匀扩展，器件的击穿电压性能较好。
本发明提供的具有低导通电阻特性的槽栅MOSFET器件可用以下方法制备得到，主要工艺步骤为：
1、单晶硅准备。采用N型重掺杂单晶硅作为N+衬底2，晶向为<100>。
2、外延生长。采用气相外延VPE等方法生长一定厚度和掺杂浓度的外延N-漂移区3。
3、深槽刻蚀，形成沟槽14。沟槽14延伸至靠近N-漂移区3底部，如图3。
4、淀积介质层和具有正电性的材料。在沟槽14中通过化学气相淀积CVD等方法形成一定厚度的介质层10，如SiO2；然后在该介质层10表面淀积Cs或其他具有正电性的材料以提供正电荷11，如图4。
5、利用各向同性湿法刻蚀，刻蚀掉沟槽14上部的介质层和正电性材料，并在顶部淀积起隔离作用的隔离介质层9，如图5。
6、制备栅结构。热生长栅氧化层8，淀积多晶硅栅电极7。
7、P型杂质注入与推阱，形成P型基区4。
8、N型重掺杂注入，形成N+重掺杂源区5。
9、P型重掺杂注入，形成P+接触区6，如图6。
9、正面源极金属化。在整个器件表面溅射一层金属铝，形成金属化源极13。
10、背面减薄、金属化，形成漏极1。
Claims (2)
1.一种具有低导通电阻特性的槽栅MOSFET器件，包括从下至上依次层叠设置的金属化漏极(1)、N+衬底(2)、N-漂移区(3)、P型体区(4)和金属化源极(13)；所述P型体区(4)上层具有N+重掺杂源区(5)和P+接触区(6)，所述N+重掺杂源区(5)位于P+接触区(6)之间；其特征在于，还包括沟槽(14)，所述沟槽(14)从N+重掺杂源区(5)上表面中部，垂直向下依次贯穿N+重掺杂源区(5)和P型体区(4)延伸入N-漂移区(3)中；所述沟槽(14)的下部中填充有厚绝缘介质层(10)，沟槽(14)的上部中填充有栅氧化层(8)，所述厚绝缘介质层(10)与栅氧化层(8)之间通过隔离介质层(9)隔离；所述厚绝缘介质层(10)中具有正电荷区(11)，所述栅氧化层(8)中具有栅电极(7)；所述栅电极(7)的上表面及部分N+重掺杂源区(5)的上表面通过隔离介质(12)与金属化源极(13)隔离；P+接触区(6)的上表面与部分N+重掺杂源区(5)的上表面与金属化源极(13)接触。
2.根据权利要求1所述的一种具有低导通电阻特性的槽栅MOSFET器件，所述栅电极(7)为多晶硅，所述绝缘介质层(9)为二氧化硅。
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107180874A (zh) * | 2017-07-18 | 2017-09-19 | 电子科技大学 | 一种积累型的深槽超结dmos器件 |
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| CN107316905A (zh) * | 2017-08-21 | 2017-11-03 | 电子科技大学 | 一种深槽dmos器件 |
| CN107316905B (zh) * | 2017-08-21 | 2020-09-29 | 电子科技大学 | 一种深槽dmos器件 |
| CN109103259A (zh) * | 2018-08-21 | 2018-12-28 | 电子科技大学 | 一种积累型dmos器件 |
| CN109585564A (zh) * | 2018-12-26 | 2019-04-05 | 芜湖启迪半导体有限公司 | 一种碳化硅mosfet器件及其制备方法 |
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