CN105938820A - 电子装置及其电子封装 - Google Patents
电子装置及其电子封装 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 148
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- 230000017525 heat dissipation Effects 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims description 60
- 238000004100 electronic packaging Methods 0.000 claims description 38
- 239000010410 layer Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000009434 installation Methods 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
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- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
本发明公开了一种电子装置及其电子封装,电子封装包括一基板以及一半导体芯片。基板具有多个基板电极。半导体芯片设于该基板之上,其中,该半导体芯片包括多个芯片电极,各自电性连接该基板的多个所述基板电极。多个所述基板电极以及多个所述芯片电极均为梯形。本发明的电子封装,芯片电极充分接触基板电极。该半导体芯片的热量被传导至该基板,沿一散热路径而传导,且该散热的主要路径为一直线。因此散热路径被简化,且电子封装的散热效率被改善。
Description
技术领域
本发明涉及一种电子封装,尤其涉及一种具有半导体芯片的电子封装。本发明还涉及一种电子装置。
背景技术
在现有的电子封装中,半导体芯片具有多个小尺寸的芯片电极。在现有概念中,半导体芯片必须连接至集成电路承载架之上,该集成电路承载架的底面被连接至印刷电路板。半导体芯片所产生的热量,从该半导体芯片经过该集成电路承载架至该印刷电路板。现有电子封装中的散热路径十分迂回,因此现有电子封装中的散热效率不佳。
发明内容
本发明的一个目的是为了欲解决现有技术的问题而提供的一种散热效率高的电子封装。
本发明的另一目的在于提供一种具有该电子封装的电子装置。
为了达到上述目的,本发明的电子封装包括一基板以及一半导体芯片。基板具有多个基板电极。半导体芯片设于该基板之上,其中,该半导体芯片包括多个芯片电极,各自电性连接该基板的多个所述基板电极。
在一实施例中,多个所述基板电极以及多个所述芯片电极均为梯形。
在一实施例中,该半导体芯片还包括多个主动元件,电性连接多个所述芯片电极。
在一实施例中,该主动元件包括多个功率转换器、多个走线以及通道。
在一实施例中,该基板还包括多个热介层孔,连接多个所述基板电极。
在一实施例中,每一个该基板电极连接有至少一个该热介层孔。
在一实施例中,每一个该基板电极包括一宽边以及一窄边,该窄边相对于该宽边。
在一实施例中,多个所述基板电极中至少一者具有一宽边邻接多个所述基板电极中另一者的窄边。
在一实施例中,该热介层孔邻接该基板电极于一位置,其邻近该宽边。
在一实施例中,该半导体芯片的热量经由该芯片电极、该基板电极以及该热介层孔,沿一散热路径被传导至该基板,且主散热路径为一直线。
在一实施例中,该基板包括多个走线,多个所述走线垂直于多个所述热介层孔。
在一实施例中,该半导体芯片包括一底面,多个所述芯片电极突出于该底面。
在一实施例中,该底面包括绝缘材料。
在一实施例中,该底面包括二氧化硅或氮化硅。
在一实施例中,该基板电极的形状相同于相对应的芯片电极的形状。
在一实施例中,该基板电极的尺寸相似于相对应的芯片电极的尺寸。
在一实施例中,该基板包括一印刷电路板或一中介层。
在一实施例中,多个所述芯片电极的厚度大于5μm。
在一实施例中,该半导体芯片于一上侧以及一下侧的多个所述电极的热量,被传递至多个所述基板电极,以由多个热介层孔进行散热。
本发明的电子装置,包括一基板,具有多个基板电极,其中,该基板包括一印刷电路板;以及一半导体芯片,设于该基板之上,其中,该半导体芯片包括多个芯片电极,各自电性连接该基板的多个所述基板电极,多个所述基板电极以及多个所述芯片电极均为梯形。
在一实施例中,该半导体芯片还包括多个主动元件,电性连接多个所述芯片电极。
在一实施例中,该主动元件包括多个功率转换器。
在一实施例中,该基板还包括多个热介层孔,连接多个所述基板电极。
在一实施例中,每一个该基板电极连接有至少一个该热介层孔。
在一实施例中,每一个该基板电极包括一宽边以及一窄边,该窄边相对于该宽边。
在一实施例中,多个所述基板电极中至少一者具有一宽边邻接多个所述基板电极中另一者的窄边。
在一实施例中,该热介层孔邻接该基板电极于一位置,其邻近该宽边。
在一实施例中,该半导体芯片的热量经由该芯片电极、该基板电极以及该热介层孔,沿一散热路径被传导至该基板,且主散热路径为一直线。
在一实施例中,该基板包括多个走线,多个所述走线垂直于多个所述热介层孔。
在一实施例中,该半导体芯片包括一底面,多个所述芯片电极突出于该底面。
在一实施例中,该底面包括绝缘材料。
在一实施例中,该底面包括二氧化硅或氮化硅。
在一实施例中,该基板电极的形状相同于相对应的芯片电极的形状。
在一实施例中,该基板电极的尺寸相似于相对应的芯片电极的尺寸。
在一实施例中,多个所述芯片电极的厚度大于5μm。
本发明具有至少如下有益效果:
本发明的电子封装,芯片电极充分接触基板电极。该半导体芯片的热量被传导至该基板,沿一散热路径而传导,且该散热的主要路径为一直线。因此散热路径被简化,且电子封装的散热效率被改善。
附图说明
图1为显示本发明第一实施例的电子封装。
图2为显示本发明第一实施例的基板的细部结构。
图3为显示本发明第一实施例的半导体芯片的细部结构。
图4为显示本发明第一实施例的半导体芯片组成示意图。
图5为显示本发明第二实施例的电子封装
图6为显示本发明第二实施例的基板的细部结构。
图7为显示本发明第二实施例的半导体芯片的细部结构。
图8为显示本发明第二实施例的半导体芯片组成示意图。
图9为显示本发明实施例半导体芯片的源极走线和汲极走线示意图。
图10为显示图9所示的实施例的俯视平面图。
图11是图9实施例的俯视平面图,其示出了第一互连层,第二互连层和第三互连层中形成的源极电极。
图12是图9实施例的俯视平面图,其示出了第一互连层,第二互连层和第三互连层中形成的汲极电极。
图13显示每一源极电极以及汲极电极被制造为”条状”,并彼此交错。
【符号说明】
1、1’~电子封装
101、102~基板
110~基板电极
111~宽边
112~窄边
120~热介层孔
130~走线
201、202~半导体芯片
210~芯片电极
230~主动元件
G~闸极电极
D~汲极电极
S~源极电极
H~热量
300~半导体芯片
310~源极
320~汲极
330~闸极
332、334~分隔件
340~源极走线
342~介层孔
350~汲极走线
352~介层孔
360~源极走线
362~介层孔
370~汲极走线
372~介层孔
380~源极电极
382~介层孔
384~焊料凸点
390~汲极电极
392~介层孔
410~源极电极
420~汲极电极
具体实施方式
图1是显示本发明第一实施例的电子封装。参照图1,该电子封装1,包括一基板101以及一半导体芯片201。基板101具有多个基板电极110。半导体芯片201设于该基板101之上,其中,该半导体芯片201包括多个芯片电极210,各自电性连接该基板101对应的多个所述基板电极110。在一实施例中,该基板101包括一印刷电路板或一中介层。
图2为显示本发明第一实施例的基板的细部结构。图3为显示本发明第一实施例的半导体芯片的细部结构。参照第2、3图,多个所述基板电极110以及多个所述芯片电极210均为梯形(trapezoidal)。
图4为显示本发明第一实施例的半导体芯片组成示意图。参照图4,在一实施例中,该半导体芯片201还包括多个主动元件230,电性连接多个所述芯片电极210。在一实施例中,该主动元件包括多个功率转换器。参照图3,该芯片电极210包括闸极电极G、源极电极S以及汲极电极D。在一实施例中,多个所述源极电极S以及多个所述汲极电极D彼此交错排列。在一实施例中,多个所述芯片电极210的厚度大于5μm。
参照图2,该基板101还包括多个热介层孔120,连接多个所述基板电极110。在一实施例中,每一个基板电极110连接至少一个该热介层孔120。
参照图2,每一个该基板电极110包括一宽边111以及一窄边112,该窄边112相对于该宽边111配置。须说明此所谓”宽”与”窄”是边长比较的概念。多个所述基板电极110中的至少一者具有一宽边111,该宽边111邻接多个所述基板电极110中的另一者的窄边112。在一实施例中,该宽边111的宽度大于150μm。在一实施例中,该宽边111平行于该窄边112。
参照图2,在一实施例中,该热介层孔120邻接该基板电极110于一位置,其邻近该宽边111。
参照图1,应用本发明的第一实施例,该半导体芯片201所产生的热量H被传导至该基板101,该热量H是经由该芯片电极210、该基板电极110以及该热介层孔120,沿一散热路径而传递,且该散热的主要路径为一直线。
参照第1、2图,该基板101包括多个走线130,多个所述走线130大致垂直于多个所述热介层孔120。
参照第1、2图,在一实施例中,多个所述基板电极110通过电镀形成于该基板101。
参照图1,在一实施例中,该半导体芯片201包括一底面220,多个所述芯片电极210突出于该底面220。在一实施例中,该底面220包括绝缘材料。在一实施例中,该底面包括二氧化硅(SiO2)或氮化硅(SiNX)。
参照第2、3图,该基板电极110的形状大致相同于相对应的芯片电极210的形状。在一实施例中,该基板电极110的尺寸相似于相对应的芯片电极210的尺寸。
图5为显示本发明第二实施例的电子封装。参照图5,该电子封装1’,包括一基板102以及一半导体芯片202。基板102具有多个基板电极110。半导体芯片202设于该基板102之上,其中,该半导体芯片202包括多个芯片电极210,各自电性连接该基板102对应的多个所述基板电极110。在一实施例中,该基板102包括一印刷电路板或一中介层。
图6为显示本发明第二实施例的基板的细部结构。图7为显示本发明第二实施例的半导体芯片的细部结构。参照第6、7图,多个所述基板电极110以及多个所述芯片电极210均为梯形(trapezoidal)。
图8为显示本发明第二实施例的半导体芯片组成示意图。参照图8,在一实施例中,该半导体芯片202还包括多个主动元件230,电性连接多个所述芯片电极210。在一实施例中,该主动元件包括多个功率转换器。参照图7,该芯片电极210包括闸极电极G、源极电极S以及汲极电极D。在一实施例中,多个所述源极电极S以及多个所述汲极电极D彼此交错排列。在一实施例中,多个所述芯片电极210的厚度大于5μm。
参照图6,该基板102还包括多个热介层孔120,连接多个所述基板电极110。在一实施例中,每一个基板电极110连接至少一个该热介层孔120。
参照图6,每一个该基板电极110包括一宽边111以及一窄边112,该窄边112相对于该宽边111配置,须说明此所谓”宽”与”窄”是边长比较的概念。多个所述基板电极110中的至少一者具有一宽边111,该宽边111邻接多个所述基板电极110中的另一者的窄边112。在一实施例中,该宽边111的宽度大于150μm。在一实施例中,该宽边111平行于该窄边112。
参照图6,在一实施例中,该热介层孔120邻接该基板电极110于一位置,其邻近该宽边111。
参照图5,应用本发明的第二实施例,该半导体芯片202所产生的热量H被传导至该基板102,该热量H是经由该芯片电极210、该基板电极110以及该热介层孔120,沿一散热路径而传递,且该散热的主要路径为一直线。
参照第5、6图,该基板102包括多个走线130,多个所述走线130大致垂直于多个所述热介层孔120。
参照第5、6图,在一实施例中,多个所述基板电极110通过电镀形成于该基板102。
参照图5,在一实施例中,该半导体芯片201包括一底面220,多个所述芯片电极210突出于该底面220。在一实施例中,该底面220包括绝缘材料。在一实施例中,该底面包括二氧化硅(SiO2)或氮化硅(SiNX)。
参照第6、7图,该基板电极110的形状大致相同于相对应的芯片电极210的形状。在一实施例中,该基板电极110的尺寸相似于相对应的芯片电极的尺寸。其中,具有大尺寸的芯片电极的半导体芯片的细部结构则详述如下。
图9为显示半导体芯片的源极走线和汲极走线示意图。参照图9,一部份的半导体芯片300具有两源极310以及一汲极320。在一实施例中,该半导体芯片装置300则以P基板305显示。在另一实施例中,P基板305沈积于另一P基板(未显示)之上。源极310以及汲极320较佳以n型掺杂植入于P基板305。
如图9所显示的,闸极330包括多个多晶硅闸极于二氧化硅(SiO2)或氮化硅(Si3N4)的绝缘层(未显示),且置于源极310和汲极320之间。邻近闸极330的是分隔件332以及334,较佳包括二氧化硅或氮化硅,并部分延伸覆盖源极310以及汲极320。源极走线340和汲极走线350上形成一第一互连层,并且最好由金属制成。当然,也可以使用其它导电材料。特别是,多个源极310通过介层孔342连接源极走线340。在一实施例中,源极走线340较佳大致正交于源极310和汲极320。
图9显示源极走线360和汲极走线370形成于第二互连层,较佳由金属制成。当然,也可以使用其它导电材料。源极走线360通过介层孔362连接源极走线340。在一实施例中,源极走线360较佳大致平行于源极310。
汲极走线350通过介层孔372连接汲极走线370。较佳的,汲极走线370大致平行于汲极320。
类似于第一互连层中,只有一个源极走线360和一个汲极走线370分别被标示,但在较佳的实施方案中,多个源极走线360和多个汲极走线370将被使用,并且,较佳的,多个所述源极走线360及多个所述汲极走线370彼此交错。
图9显示源极电极380形成于第三互连层,较佳地,其由金属制成。当然,也可以使用其它导电材料。源极电极380通过介层孔382连接源极走线360。焊料凸点384形成于源极电极380,这些焊料凸点384提供源级310、汲极320以与门极330与外部电路之间的电性连接。
在一较佳实施例中,介层孔(例如,上述介层孔342、介层孔352、介层孔362、介层孔372、介层孔382)形成导电连接,并较佳包括钨。当然,也可以使用其它导电材料。
图10为显示图9所示的实施例的俯视平面图。参照图10,其显示了额外的源极310,汲极320和第一层互连源极走线340和汲极走线350。源极310及汲极320具有大致垂直的方位,而源极走线340和汲极走线350具有大致水平的方位。介层孔342和352分别将源极走线340和汲极走线350连接至源极310及汲极320。应当指出的是,虽然图10,举例来说,示出了在一个点连接使用两个介层孔,然而,单一介层孔也可以被使用,如图11所示。或者,多于两个介孔层,如图9显示的介层孔382。
图11是图9实施例的俯视平面图,其示出了第一互连层,第二互连层和第三互连层中形成的源极电极。详细言之,第一互连层形成源极走线340和汲极走线350,第二互连层形成源极走线360和汲极走线370,第三互连层中形成源极电极380(轮廓形式)。
源极走线340和汲极走线350在基本上是以水平方向布置的。源极走线360覆盖源极走线340,彼此并使用介层孔362相互连接。汲极走线370覆盖汲极走线350,彼此并使用介层孔372相互连接。图11的源极电极380覆盖源极走线360和汲极走线370,然而,仅通过介层孔382连接至源极走线360。
图12是图9实施例的俯视平面图,其示出了第一互连层,第二互连层和第三互连层中形成的汲极电极。详细言之,第一互连层形成源极走线340和汲极走线350,第二互连层形成源极走线360和汲极走线370,第三互连层中形成汲极电极390(轮廓形式)。
源极走线340和汲极走线350在基本上是以水平方向布置的。源极走线360覆盖源极走线340,彼此并使用介层孔362相互连接。汲极走线370覆盖汲极走线350,彼此并使用介层孔372相互连接。汲极电极390覆盖源极走线360和汲极走线370,然而,仅通过介层孔392连接至汲极走线370。
图13显示每一源极电极以及汲极电极被制造为”条状”,并彼此交错。在一较佳实施例中,闸极电极430被设于缩短的源极电极410或缩短的汲极电极420。
应用本发明实施例的电子封装,芯片电极充分接触基板电极。该半导体芯片的热量被传导至该基板,该热量经由该芯片电极、该基板电极以及该热介层孔,沿一散热路径而传导,且该散热的主要路径为一直线。因此散热路径被简化,且电子封装的散热效率被改善。
虽然本发明已以具体的较佳实施例公开如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,仍可作些许的更动与润饰,因此本发明的保护范围当视后附的权利要求所界定的为准。
Claims (35)
1.一种电子封装,包括:
一基板,具有多个基板电极;以及
一半导体芯片,设于该基板之上,其中,该半导体芯片包括多个芯片电极,各自电性连接该基板的多个所述基板电极。
2.如权利要求1所述的电子封装,其中,多个所述基板电极以及多个所述芯片电极均为梯形。
3.如权利要求1所述的电子封装,其中,该半导体芯片还包括多个主动元件,多个所述主动元件电性连接多个所述芯片电极。
4.如权利要求3所述的电子封装,其中,该主动元件包括多个功率转换器。
5.如权利要求1所述的电子封装,其中,该基板还包括多个热介层孔,多个所述热介层孔连接多个所述基板电极。
6.如权利要求5所述的电子封装,其中,每一个该基板电极连接有至少一个该热介层孔。
7.如权利要求5所述的电子封装,其中,每一个该基板电极包括一宽边以及一窄边,该窄边相对于该宽边。
8.如权利要求7所述的电子封装,其中,多个所述基板电极中至少一者具有一宽边邻接多个所述基板电极中另一者的窄边。
9.如权利要求7所述的电子封装,其中,该热介层孔邻接该基板电极于一位置,其邻近该宽边。
10.如权利要求5所述的电子封装,其中,该半导体芯片的热量经由该芯片电极、该基板电极以及该热介层孔,沿一散热路径被传导至该基板,且主散热路径为一直线。
11.如权利要求10所述的电子封装,其中,该基板包括多个走线,多个所述走线垂直于多个所述热介层孔。
12.如权利要求1所述的电子封装,其中,该半导体芯片包括一底面,多个所述芯片电极突出于该底面。
13.如权利要求12所述的电子封装,其中,该底面包括绝缘材料。
14.如权利要求12所述的电子封装,其中,该底面包括二氧化硅或氮化硅。
15.如权利要求1所述的电子封装,其中,该基板电极的形状相同于相对应的芯片电极的形状。
16.如权利要求15所述的电子封装,其中,该基板电极的尺寸相似于相对应的芯片电极的尺寸。
17.如权利要求1所述的电子封装,其中,该基板包括一印刷电路板或一中介层。
18.如权利要求1所述的电子封装,其中,多个所述芯片电极的厚度大于5μm。
19.如权利要求1所述的电子封装,其中,该半导体芯片于一上侧以及一下侧的多个所述电极的热量,被传递至多个所述基板电极,以由多个热介层孔进行散热。
20.一种电子装置,包括:
一基板,具有多个基板电极,其中,该基板包括一印刷电路板;以及
一半导体芯片,设于该基板之上,其中,该半导体芯片包括多个芯片电极,各自电性连接该基板的多个所述基板电极,多个所述基板电极以及多个所述芯片电极均为梯形。
21.如权利要求20所述的电子装置,其中,该半导体芯片还包括多个主动元件,电性连接多个所述芯片电极。
22.如权利要求21所述的电子装置,其中,该主动元件包括多个功率转换器。
23.如权利要求20所述的电子装置,其中,该基板还包括多个热介层孔,连接多个所述基板电极。
24.如权利要求23所述的电子装置,其中,每一个该基板电极连接有至少一个该热介层孔。
25.如权利要求23所述的电子装置,其中,每一个该基板电极包括一宽边以及一窄边,该窄边相对于该宽边。
26.如权利要求25所述的电子装置,其中,多个所述基板电极中至少一者具有一宽边邻接多个所述基板电极中另一者的窄边。
27.如权利要求25所述的电子装置,其中,该热介层孔邻接该基板电极于一位置,其邻近该宽边。
28.如权利要求23所述的电子装置,其中,该半导体芯片的热量经由该芯片电极、该基板电极以及该热介层孔,沿一散热路径被传导至该基板,且主散热路径为一直线。
29.如权利要求28所述的电子装置,其中,该基板包括多个走线,多个所述走线垂直于多个所述热介层孔。
30.如权利要求20所述的电子装置,其中,该半导体芯片包括一底面,多个所述芯片电极突出于该底面。
31.如权利要求30所述的电子装置,其中,该底面包括绝缘材料。
32.如权利要求30所述的电子装置,其中,该底面包括二氧化硅或氮化硅。
33.如权利要求20所述的电子装置,其中,该基板电极的形状相同于相对应的芯片电极的形状。
34.如权利要求33所述的电子装置,其中,该基板电极的尺寸相似于相对应的芯片电极的尺寸。
35.如权利要求20所述的电子装置,其中,多个所述芯片电极的厚度大于5μm。
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US14/638,440 US20160260660A1 (en) | 2015-03-04 | 2015-03-04 | Electronic device and electronic package thereof |
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EP (1) | EP3065171A3 (zh) |
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CN110793562A (zh) * | 2019-11-07 | 2020-02-14 | 山东浪潮人工智能研究院有限公司 | 一种金刚石传感器测试用探测器模块封装结构及方法 |
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US10083894B2 (en) * | 2015-12-17 | 2018-09-25 | International Business Machines Corporation | Integrated die paddle structures for bottom terminated components |
TWI760711B (zh) * | 2020-03-17 | 2022-04-11 | 瑞昱半導體股份有限公司 | 積體電路裝置 |
CN113451264B (zh) * | 2020-03-24 | 2024-05-31 | 瑞昱半导体股份有限公司 | 集成电路装置 |
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- 2015-03-18 EP EP15159632.7A patent/EP3065171A3/en not_active Ceased
- 2015-11-09 TW TW104136798A patent/TWI584427B/zh active
- 2015-11-09 CN CN201510755430.9A patent/CN105938820B/zh active Active
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TWI584427B (zh) | 2017-05-21 |
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EP3065171A3 (en) | 2016-12-21 |
EP3065171A2 (en) | 2016-09-07 |
US20160260660A1 (en) | 2016-09-08 |
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