CN105934813A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN105934813A
CN105934813A CN201580005967.1A CN201580005967A CN105934813A CN 105934813 A CN105934813 A CN 105934813A CN 201580005967 A CN201580005967 A CN 201580005967A CN 105934813 A CN105934813 A CN 105934813A
Authority
CN
China
Prior art keywords
film
electrode
semiconductor device
oxidation
organic resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201580005967.1A
Other languages
English (en)
Other versions
CN105934813B (zh
Inventor
吉田基
远藤加寿代
藤田淳
冈部博明
须贺原和之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN105934813A publication Critical patent/CN105934813A/zh
Application granted granted Critical
Publication of CN105934813B publication Critical patent/CN105934813B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明的目的在于提供在高温动作中也抑制Cu布线的氧化的半导体装置。本发明的半导体装置具备：基板(1)，具有主面；Cu电极(8)，选择性地形成于基板(1)的主面一侧；氧化防止膜(14)，形成于Cu电极(8)的上表面的除其端部以外的区域；有机树脂膜(10)，形成于基板(1)的主面上，遮覆Cu电极(8)的侧面以及上表面的端部；以及扩散防止膜(11)，在有机树脂膜(10)与基板(1)的主面之间，与两者相接而形成，并在有机树脂膜(10)与Cu电极(8)的侧面以及上表面的端部之间，与两者相接而形成。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别涉及防止Cu布线电极氧化的技术。
背景技术
以往，作为在功率用途等中使用的半导体装置的布线材料，使用Al(铝)系材料。以往，半导体装置在小于200℃的温度下动作，但伴随要求在超过200℃的高温下动作，使用宽带隙半导体的半导体装置得到重视。其一个例子是使用碳化硅半导体元件的半导体装置。但是，存在如下问题：在超过200℃的高温动作中，由于Al系布线材料与半导体元件的电极的相互反应、Al系布线材料的形状变化等，碳化硅半导体装置的可靠性下降。因此，作为代替Al的布线材料，能够在200℃以上的高温下使用的Cu(铜)得到重视(参照例如专利文献1)。
专利文献1：国际公开第2007－108439号
发明内容
当使将Cu用于布线材料的半导体装置在200℃以上的温度下动作时，Cu布线电极的表面被氧化。针对该问题，通常为了应对大气中的静电等而利用有机树脂膜覆盖半导体装置，而以往，从有机树脂膜的开口部通过非电解镀层在Cu布线上形成Ni层，从而抑制Cu布线电极的氧化。但是，存在如下问题：在有机树脂膜与Ni层的界面处由于密合力不足而生成空孔，氧或者水分从该空孔侵入到Cu布线电极。
本发明是为了解决上述课题而完成的，其目的在于提供在高温动作中也抑制Cu布线的氧化的半导体装置。
本发明涉及半导体装置，具备：半导体基板，具有主面；Cu电极，选择性地形成于半导体基板的主面一侧；氧化防止膜，形成于Cu电极的上表面的除其端部以外的区域；有机树脂膜，形成于半导体基板的主面上，遮覆Cu电极的侧面以及上表面的该端部；以及无机膜，在有机树脂膜与所述半导体基板的所述主面之间，与两者相接而形成，并在所述有机树脂膜与所述Cu电极的所述侧面及所述上表面的所述端部之间，与两者相接而形成。
本发明的半导体装置具备：半导体基板，具有主面；Cu电极，选择性地形成于半导体基板的主面一侧；氧化防止膜，形成于Cu电极的上表面的除其端部以外的区域；有机树脂膜，形成于半导体基板的主面上，遮覆Cu电极的侧面以及上表面的该端部；以及无机膜，在有机树脂膜与所述半导体基板的所述主面之间，与两者相接而形成，并在所述有机树脂膜与所述Cu电极的所述侧面及所述上表面的所述端部之间，与两者相接而形成。因此，形成于Cu电极的上表面的氧化防止膜与无机膜的密合力大，所以能够通过无机膜和氧化防止膜来抑制从有机树脂膜与氧化防止膜的界面侵入的水、氧到达Cu电极的表面。因此，即使使半导体装置高温动作也能够抑制Cu电极的氧化，半导体装置的可靠性提高。
附图说明
图1是示出本发明的实施方式1的半导体装置的构造的剖面图。
图2是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图3是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图4是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图5是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图6是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图7是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图8是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图9是示出本发明的实施方式1的半导体装置的制造工序的剖面图。
图10是示出本发明的实施方式2的半导体装置的构造的剖面图。
图11是示出本发明的实施方式3的半导体装置的构造的剖面图。
图12是示出本发明的实施方式3的半导体模块的构造的剖面图。
图13是示出使扩散防止膜的膜厚变化时的Cu电极的氧化抗性的图。
符号说明
1：基板；5：肖特基电极(Schottky electrode)；6：势垒金属层(Barrier metal layer)；7：金属层；8：Cu电极；8a：第一Cu层；8b：第二Cu层；10：有机树脂膜；11：扩散防止膜；13：背面外部输出电极；14：氧化防止膜；14a：第一氧化防止膜；14b：第二氧化防止膜；15：蚀刻掩模(Etching mask)；16：抗蚀剂掩模(Resistmask)；21、23、25：导电板；22：半导体芯片；24：绝缘性陶瓷；27：冷却器；28：树脂；100、101、102：碳化硅半导体装置。
具体实施方式
<A.实施方式1>
<A－1.结构>
说明本发明的实施方式1的半导体装置的结构。以下，在本说明书中，作为该半导体装置的一个例子，说明将n型的碳化硅肖特基势垒二极管(SBD：Schottky diode)作为碳化硅半导体元件而包括的碳化硅半导体装置。
图1是示出该碳化硅半导体装置100的结构的、与基板的主面垂直的方向的剖面图。另外，在图1中，仅示出了碳化硅半导体装置100的剖面图的左边一半。即，碳化硅半导体装置100的实际的剖面图是将图1所示的剖面图以其右端为轴左右对称地设置而得到的图。另外，关于碳化硅半导体装置100的平面图，省略图示，在与基板的主面垂直的方向的任意的剖面图中，都是图1所示那样。
碳化硅半导体装置100具备作为包含n型的碳化硅的半导体基板(碳化硅基板)的基板1、肖特基电极5、势垒金属层6、金属层7、Cu电极8、氧化防止膜14、扩散防止膜11、有机树脂膜10以及背面外部输出电极13。
虽然在图1中未示出，但基板1的主面侧的表层是漂移层。肖特基电极5形成于基板1的主面，其厚度是100nm以上且500nm以下。势垒金属层6以及金属层7依次层叠于肖特基电极5的上表面。
势垒金属层6的厚度是10nm以上且200nm以下。在金属层7的上表面，形成作为布线电极的Cu电极8。Cu电极8包括形成于金属层7的上表面的下层的第一Cu层8a和上层的第二Cu层8b。第一Cu层8a是用于形成第二Cu层8b的种子层(seed layer)，第二Cu层8b是表面外部输出电极。
氧化防止膜14包括下层的第一氧化防止膜14a和上层的第二氧化防止膜14b。第一氧化防止膜14a图案形成于Cu电极8的第二Cu层8b的上表面，特别形成于该上表面的除端部以外的区域。第一氧化防止膜14a由Ni、Ag、Sn、Al、Au或者包含它们的合金、或者它们的层叠构造形成。另外，从防止Cu电极8氧化的观点来看，其膜厚是10nm以上且小于10μm。
第二氧化防止膜14b形成于第一氧化防止膜14a的上表面的除其端部以外的区域。从防止Cu电极8氧化的观点来看，其膜厚设为10nm以上且小于100μm。第二氧化防止膜14b的材料也可以与第一氧化防止膜14a的材料不同，但代表性的材料是Ni、Ag、Sn、Al、Au或者包含它们的合金、或者它们的层叠构造。
基板1的漂移层、肖特基电极5、势垒金属层6、金属层7、Cu电极8以及第一氧化防止膜14a的露出面被扩散防止膜11覆盖。即，基板1的漂移层表面、肖特基电极5、势垒金属层6、金属层7、Cu电极8以及第一氧化防止膜14a的侧面被扩散防止膜11覆盖。进而，金属层7形成于势垒金属层6的上表面的除其端部以外的区域(参照图1)，所以势垒金属层6的上表面的该端部也被扩散防止膜11覆盖。即，金属层7形成于势垒金属层6的上表面的中心侧，在端部区域形成扩散防止膜11。另外，Cu电极8的上表面的不形成第一氧化防止膜14a的端部也被扩散防止膜11覆盖。即，在Cu电极8的上表面，在中心侧形成第一氧化防止膜14a，在端部区域形成扩散防止膜11。另外，第一氧化防止膜14a的上表面的不形成第二氧化防止膜14b的区域的扩散防止膜11覆盖。即，在第一氧化防止膜14a的上表面，在中心侧形成第二氧化防止膜14b，在端部区域形成扩散防止膜11。扩散防止膜11是SiN、SiON或者Si3N4等无机膜。另外，为了阻止氧或者水分侵入到Cu电极8，其膜厚设为至少100nm以上。
图13示出使扩散防止膜11的膜厚变化时的Cu电极8的氧化抗性。使包含SiN的扩散防止膜11的膜厚按10、30、50、100、300、500nm变化，针对各个，在200℃下进行1000小时的高温保管试验。然后，评价此时的Cu电极8的氧化膜厚，如果未形成氧化膜，则用○表示，如果形成有氧化膜，则用×表示。
根据图13可知，如果扩散防止膜11的膜厚是30nm以上，则能够确保Cu电极8的氧化抗性。但是，被推测为将来在实现了扩散防止膜11的形成方法、膜质的高致密化时，能够将扩散防止膜11极端地减小至例如1nm左右。另外，通过将扩散防止膜11设为10μm以下的膜厚，从而能够抑制由于在扩散防止膜11自身中产生的应力而产生裂纹。
扩散防止膜11也可以设为折射率是2.4以上且小于2.7的半绝缘性的SiN。
扩散防止膜11被有机树脂膜10覆盖。有机树脂膜10是聚酰亚胺，其膜厚设为3μm以上且100μm以下。扩散防止膜11不仅起到防止上述Cu电极8氧化的作用，而且还起到防止Cu从Cu电极8向有机树脂膜10扩散的作用。
在基板1的背面、即与形成肖特基电极5的主面相反的一侧的面，形成背面外部输出电极13。以上，说明了图1所示的碳化硅半导体装置100的结构。碳化硅半导体装置100中的、基板1、肖特基电极5以及势垒金属层6构成碳化硅肖特基势垒二极管。
在这样的碳化硅半导体装置100的结构中，由于有机树脂膜10与氧化防止膜14的密合力不足，在两者的界面处产生空孔。通过该空孔，水分或者氧侵入到该界面。但是，作为无机膜的扩散防止膜11针对氧化防止膜14的密合性比有机树脂膜10的高，在扩散防止膜11与有机树脂膜10的界面处不易产生空孔，所以能够通过扩散防止膜11抑制该水分或者氧到达至Cu电极8。因此，在高温动作时，抑制Cu电极8的氧化，碳化硅半导体装置100的可靠性提高。
<A－2.制造方法>
接下来，按照图2至9，说明图1所示的碳化硅半导体装置100的制造方法。图2至9是示出碳化硅半导体装置100的制造工序的剖面图。另外，在图2至9中，与图1同样地，仅示出了碳化硅半导体装置100的左侧一半的剖面。
首先，准备包含具有高浓度的杂质浓度的n型(n+型)的碳化硅的基板1。然后，在基板1的主面，使用Ti、Mo、Ni等靶材，通过例如溅射法，使膜厚是100nm以上且500nm以下的肖特基电极5成膜。肖特基电极5成膜于基板1的漂移层的表面整体。进而，在肖特基电极5的表面整体，通过例如溅射法将TiN制作成膜，形成势垒金属层6。如果Cu从Cu电极8扩散到肖特基电极5，则导致漏电流的增加等碳化硅半导体装置的电特性的劣化，所以以防止这一情况为目的而设置有势垒金属层6。从该观点来看，势垒金属层6的膜厚优选设为10nm以上且200nm以下。
接下来，为了从基板1的周边部(图2的左侧)去除势垒金属层6，将包含利用照相制版的抗蚀剂图案的蚀刻掩模15仅形成于基板1的中央部(图2的右侧)。然后，使用蚀刻掩模15对势垒金属层6进行蚀刻。在势垒金属层6是例如TiN的情况下，对势垒金属层6进行湿蚀刻。
接着，使用蚀刻掩模15来进行肖特基电极5的蚀刻。在肖特基电极5的金属是例如Ti的情况下，用稀释氢氟酸而得到的溶液进行湿蚀刻(参照图2)。之后，蚀刻掩模15通过使用有机溶剂的湿蚀刻或者使用氧等离子体的灰化被去除。这样，作为实施方式1的碳化硅半导体元件的碳化硅肖特基势垒二极管完成。
接下来，在整个面、即势垒金属层6以及基板1的漂移层表面，使例如Ti成膜，形成金属层7。通过在势垒金属层6上形成金属层7，从而改善在后工序中形成的Cu电极8与势垒金属层6的密合性。另外，通过在基板1的漂移层表面形成金属层7，从而在后工序中Cu电极8的第一Cu层8a不直接形成于漂移层，所以金属层7作为与Cu有关的势垒金属发挥功能，能够抑制Cu从第一Cu层8a向漂移层扩散。
接下来，在金属层7的上表面，形成作为第二Cu层8b的基底的第一Cu层8a。第一Cu层8a是Cu膜或者Cu合金膜，通过例如PVD(Physical Vapor Deposition，物理气相沉积)法、热蒸镀、电子束蒸镀、溅射、使用了有机金属等的气体的金属CVD(Chemical VaporDeposition，化学气相沉积)法等制作成膜。第一Cu层8a的厚度设为100nm以上且1000nm以下。此处，在势垒金属层6的上表面隔着金属层7使第一Cu层8a成膜，所以能够得到如上所述密合性高的Cu电极8。
接下来，通过对抗蚀剂进行涂覆、曝光、显影，从而在第一Cu层8a的上表面的、不想使第二Cu层8b成膜的区域形成抗蚀剂掩模16(参照图3)。即，为了使第二Cu层8b成膜于基板1的中央侧(图3的右侧)而不成膜于周边侧(图3的左侧)，以使隔着金属层7而形成于势垒金属层6上的第一Cu层8a的上表面开口的方式，对抗蚀剂掩模16进行构图。
接下来，使用抗蚀剂掩模16，通过镀层法使第二Cu层8b成膜。第二Cu层8b在第一Cu层8a的上表面中的、未形成抗蚀剂掩模16的区域，沿着抗蚀剂掩模16的侧壁而形成。第二Cu层8b的厚度是例如6μm以上且小于100μm即可，作为Cu电极8整体的厚度，是7μm以上且小于100μm即可。这样，形成图3所示的结构。
接下来，通过使用有机溶剂的湿蚀刻或者使用氧等离子体的灰化来去除抗蚀剂掩模16(图4)。
进而，对隔着金属层7而形成于漂移层的表面的第一Cu层8a全部进行湿蚀刻。另外，在对第一Cu层8a进行湿蚀刻时，势垒金属层6的上表面的Cu电极8(第一Cu层8a以及第二Cu层8b)的露出区域也被暴露于湿蚀刻液。因此，该暴露的部位的Cu电极8也以某种程度被蚀刻。
接下来，掩蔽第一Cu层8a以及第二Cu层8b，利用氢氟酸去除形成于漂移层上的金属层7。经由以上的工序，得到图5的构造。
接下来，在整个面形成第一氧化防止膜14a，使用蚀刻掩模15，以在第二Cu层8b的上表面的除端部以外的区域使第一氧化防止膜14a残留的方式，从其它区域去除第一氧化防止膜14a。
之后，用扩散防止膜11覆盖肖特基电极5、势垒金属层6、金属层7、Cu电极8、第一氧化防止膜14a以及漂移层的露出面。扩散防止膜11是SiN、SiON、Si3N4等无机膜，通过例如CVD法形成。使扩散防止膜11的膜厚至少为30nm。在侧壁部、特别是下部，扩散防止膜11的膜厚变薄，所以使该部分的膜厚为30nm以上。另外，膜厚为100nm以上是更加优选的。
关于将扩散防止膜11的膜厚设为30nm以上的理由，如上述说明，是因为图13的高温保管试验结果。另外，还有以下的理由。一般，碳化硅半导体装置设想在200℃以上的高温下动作。因此，相比于未设想在高温下使用的Si半导体装置，由于热而产生的应力更大。另外，热所致的Cu的扩散速度更大。在将覆盖扩散防止膜11的有机树脂膜10的膜厚设为3μm以上且100μm以下的情况下，如果扩散防止膜11的膜厚比30nm薄，则由于有机树脂膜10的应力而在扩散防止膜11中产生裂纹，产生Cu原子在裂纹中扩散这样的问题。因此，将扩散防止膜11的膜厚设为30nm以上。
接下来，通过将利用照相制版的抗蚀剂图案作为掩模，利用RIE(Reactive Ion Etching，反应离子刻蚀)等对扩散防止膜11进行蚀刻，使第一氧化防止膜14a的上表面的除端部以外的区域露出(图7)。
接下来，以覆盖扩散防止膜11以及所露出的第一氧化防止膜14a的上表面的方式，通过旋涂法等形成有机树脂膜10。有机树脂膜10的膜厚设为3μm以上且100μm以下。
接着，将利用照相制版的抗蚀剂图案作为掩模，对有机树脂膜10进行蚀刻，使第一氧化防止膜14a的上表面的除端部以外的区域露出(图8)。
接下来，在有机树脂膜10的开口部，通过例如非电解镀层法形成第二氧化防止膜14b。第二氧化防止膜14b通过例如非电解镀层法形成。进而，在基板1的背面、即与形成肖特基电极5的主面相反的一侧的面，形成背面外部输出电极13。通过以上的工序，能够得到实施方式1的半导体装置(图9：图1的再次示出)。
另外，在上述说明中，分别进行了扩散防止膜11的蚀刻和有机树脂膜10的蚀刻。但是，也可以接着扩散防止膜11的成膜而使有机树脂膜10成膜，对扩散防止膜11和有机树脂膜10同时进行蚀刻，使第一氧化防止膜14a的上表面的一部分露出。由此，能够将蚀刻工序数量削减1个工序。
另外，根据本实施方式，使扩散防止膜11和有机树脂膜10分别通过1次成膜工序和1次蚀刻工序形成，所以能够通过简单的制造工艺且低成本的方法来得到可靠性高的半导体装置。
<A－3.变形例>
另外，上述碳化硅半导体装置的制造方法是一个例子，本实施方式的半导体装置的制造方法不限于此。只要最终能够得到图1所示的构造，则也可以使用在本实施方式的说明中叙述的制造方法以外的制造方法。
另外，在本实施方式中，将半导体元件设为n型的碳化硅肖特基势垒二极管，但也可以是p型，这是不言而喻的。另外，作为半导体材料，除了碳化硅以外，还可以使用能够进行高温动作的宽带隙半导体。
另外，在碳化硅半导体装置中，要求在高耐压下动作，所以如果Cu电极8的表面氧化，则招致与和Cu电极接合的模块部件的密合力下降，成为可靠性的下降、不稳定化或者模块损坏、不稳定的动作的一个原因。为了使用碳化硅来实现稳定的高耐压动作，本实施方式中的碳化硅半导体装置是有效的。
另外，在本实施方式中，作为半导体元件，使用了肖特基势垒二极管，但也可以是JBS(Junction Barrier Schottky，肖特基势垒)、MOSFET(Metal Oxide Field Effect Transistor，金属氧化物场效应晶体管)、JFET(Junction Field Effect Transistor，结场效应晶体管)、IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)、PN二极管等其它器件。只要是将Cu用作布线电极材料，用有机树脂膜10覆盖半导体元件的构造，则能够将本实施方式应用于所有的半导体元件。
<A－4.效果>
作为实施方式1的半导体装置的一个例子的碳化硅半导体装置100具备：Cu电极8，选择性地形成于基板1的主面一侧；氧化防止膜14，形成于Cu电极8的上表面的除其端部以外的区域；有机树脂膜10，形成于基板1的主面上，遮覆Cu电极8的侧面以及上表面的所述端部；以及无机膜的扩散防止膜11，在有机树脂膜10与基板1的主面之间，与两者相接而形成，并在有机树脂膜10与Cu电极8的侧面及上表面的端部之间，与两者相接而形成。即，对Cu电极8的侧面和氧化防止膜14的侧面设置台阶，在与该台阶相关的Cu电极8的侧面以及上表面的端部，在与有机树脂膜10之间设置有扩散防止膜11。扩散防止膜11与氧化防止膜14的密合力比有机树脂膜10与氧化防止膜14的密合力强，所以能够通过氧化防止膜14和扩散防止膜11切断从有机树脂膜10和氧化防止膜14的界面侵入的水分或者氧，抑制Cu电极8氧化。
另外，氧化防止膜14具备：第一氧化防止膜14a，形成于Cu电极8上；以及第二氧化防止膜14b，形成于第一氧化防止膜14a的上表面的除其端部以外的区域，扩散防止膜11在有机树脂膜10与第一氧化防止膜14a的侧面以及上表面的端部之间，与两者相接而形成。即，不仅对Cu电极8的侧面和第一氧化防止膜14a的侧面设置台阶，而且对第一氧化防止膜14a的侧面和第二氧化防止膜14b的侧面也设置台阶，在与该台阶相关的第一氧化防止膜14a的侧面以及上表面的端部，在与有机树脂膜10之间设置有扩散防止膜11。由此，沿着第一氧化防止膜14a与扩散防止膜11的界面到达Cu电极8的距离变长，所以能够通过扩散防止膜11切断从有机树脂膜10与第二氧化防止膜14b的界面侵入的水分或者氧，进一步抑制Cu电极8的氧化。
另外，碳化硅半导体装置100还具备形成于基板1与Cu电极8之间的势垒金属层6，扩散防止膜11在势垒金属层6的侧面与有机树脂膜10之间也与两者相接而形成，所以能够通过扩散防止膜11切断从有机树脂膜10与扩散防止膜11的界面侵入的水分或者氧，抑制Cu电极8的氧化。
另外，Cu电极8形成于势垒金属层6的上表面的除其端部以外的区域，扩散防止膜11在有机树脂膜10与势垒金属层6的侧面以及上表面的端部之间，与两者相接而形成。在这样的构造中，也能够通过扩散防止膜11切断从有机树脂膜10与扩散防止膜11的界面侵入的水分或者氧，抑制Cu电极8的氧化。
另外，在本实施方式中，在Cu电极8的侧面也设置有扩散防止膜11，这在Cu电极8的侧面与有机树脂膜10之间设置有扩散防止膜11的情况下，能够得到抑制有机树脂膜10中的水分、氧扩散到Cu电极8而与Cu反应的效果。
在本实施方式中，在基板1上也形成有扩散防止膜11，但也可以在基板1上不形成。但是，如果在基板1的主面上未形成扩散防止膜11，则有时在基板1的主面上生成Cu与水分的反应物，产生半导体装置的绝缘性、可靠性下降的问题。如本实施方式的图1所示，只要从基板1与有机树脂膜10之间起至扩散防止膜11的上表面和有机树脂膜10的上表面连续地设置，则即使Cu从Cu电极8沿着扩散防止膜11扩散至基板1的主面上，由于在与有机树脂膜10之间设置有扩散防止膜11，所以仍能够抑制有机树脂膜10中的水分、氧与Cu反应。
<B.实施方式2>
<B－1.结构>
在实施方式1的碳化硅半导体装置100中，将氧化防止膜14设为第一氧化防止膜14a和第二氧化防止膜14b的2层构造，通过第一氧化防止膜14a阻止从由于有机树脂膜10的侧面与第二氧化防止膜14b的密合力不足而产生的空孔侵入的氧、水分。但是，在图10所示的实施方式2的碳化硅半导体装置101中，将氧化防止膜14设为单层构造，将其厚度设为10nm以上且小于100μm。
关于碳化硅半导体装置101，除了将氧化防止膜14设为单层构造以外，与碳化硅半导体装置100的结构相同。即使是这样的构造，扩散防止膜11与氧化防止膜14的密合力仍被确保，所以只要能够将扩散防止膜11的膜厚确保为30nm以上，就能够阻止氧或者水分侵入到Cu电极8。
<B－2.制造方法>
关于碳化硅半导体装置101的制造方法，直至Cu电极8的形成为止，与碳化硅半导体装置100的制造方法相同。在金属层7上形成Cu电极8之后，将扩散防止膜11以及有机树脂膜10依次层叠于整个面。然后，对扩散防止膜11以及有机树脂膜10进行蚀刻而形成开口部，以使Cu电极8的上表面的除端部以外的区域露出。然后，从该开口部使氧化防止膜14形成于Cu电极8上。
<B－3.效果>
关于碳化硅半导体装置101，在碳化硅半导体装置100的结构中，将氧化防止膜14设为单层构造，将其厚度设为10nm以上且100μm以下。即使是这样的构造，扩散防止膜11与氧化防止膜14的密合力仍被确保，所以只要能够将扩散防止膜11的膜厚确保为30nm以上，就能够阻止氧或者水分侵入到Cu电极8。
另外，碳化硅半导体装置101的制造方法具备：(a)在基板1上形成Cu电极8的工序；(b)用作为无机膜的扩散防止膜11遮覆基板1以及Cu电极8的工序；(c)用有机树脂膜10覆盖扩散防止膜11的工序；(d)对有机树脂膜10以及扩散防止膜11进行蚀刻而形成开口部，从该开口部使Cu电极8露出的工序；以及(e)在开口部处在Cu电极8上形成氧化防止膜14的工序。相比于碳化硅半导体装置100的制造方法，氧化防止膜14是单层，所以能够得到削减制造工序这样的效果。
<C.实施方式3>
图11是示出实施方式3的碳化硅半导体装置102的结构的剖面图。碳化硅半导体装置102是在实施方式2的碳化硅半导体装置101中氧化防止膜14搭在扩散防止膜11的一部分上的结构。其它结构与图10所示的实施方式2的碳化硅半导体装置101相同，所以省略说明。
在实施方式2的碳化硅半导体装置101中，将氧化防止膜14设为单层构造，并与扩散防止膜11邻接，从而阻止从由于有机树脂膜10与氧化防止膜14的密合力不足而产生的空孔侵入的氧、水分。
但是，在图11所示的实施方式3中，使氧化防止膜14与扩散防止膜11邻接，进而还配置在扩散防止膜11上。因此，能够通过扩散防止膜11以及氧化防止膜14的界面来阻止从由于有机树脂膜10与氧化防止膜14的密合力不足而产生的空孔侵入的氧、水分。另外，扩散防止膜11的侧面以及上表面与氧化防止膜14紧贴，所以两者的密合区域比实施方式2大。因此，上述阻止的效果比实施方式2大，可靠性提高。
<D.实施方式4>
图12是示出实施方式4的碳化硅半导体模块的结构的剖面图。该碳化硅半导体模块具备半导体芯片22、导电板21、23、25、绝缘陶瓷24、冷却器27、树脂28。
在绝缘陶瓷24的上表面和下表面，分别接合导电板23、25。导电板25通过接合材料26而与冷却器27接合。导电板23通过管芯焊接材料30而与半导体芯片22的下表面接合。
对半导体芯片22使用在实施方式1～3中说明的碳化硅半导体装置101～103中的任意的装置。半导体芯片22的上表面通过接合材料29而与导电板21接合。导电板21、半导体芯片22、导电板23、绝缘陶瓷24以及导电板25被树脂28密封。
这样，图12所示的碳化硅半导体模块是半导体芯片22经由绝缘陶瓷24而与冷却器27接合的结构。
另外，冷却器27不仅可以如图12所示设置于半导体芯片22的下侧，而且还可以设置于半导体芯片22的上侧或者上侧下侧这两方。
半导体芯片22能够在200℃以上的温度下动作。因此，通过使用抑制半导体芯片22－冷却器27之间的热阻的构造，从而能够使碳化硅半导体模块小型化。例如，能够使用其而使逆变器小型化。
另外，本发明能够在其发明的范围内，自由地组合各实施方式或者对各实施方式适当地进行变形、省略。

Claims (13)

1.一种半导体装置，具备：
半导体基板，具有主面；
Cu电极，选择性地形成于所述半导体基板的所述主面一侧；
氧化防止膜，形成于所述Cu电极的上表面的除其端部以外的区域；
有机树脂膜，形成于所述半导体基板的所述主面上，遮覆所述Cu电极的侧面以及所述上表面的所述端部；以及
无机膜，在所述有机树脂膜与所述半导体基板的所述主面之间，与两者相接而形成，并在所述有机树脂膜与所述Cu电极的所述侧面及所述上表面的所述端部之间，与两者相接而形成。
2.根据权利要求1所述的半导体装置，其特征在于，
所述氧化防止膜具备：
第一氧化防止膜，形成于所述Cu电极上；以及
第二氧化防止膜，形成于所述第一氧化防止膜的上表面的除其端部以外的区域，
所述无机膜形成为在所述有机树脂膜与所述第一氧化防止膜的侧面以及所述上表面的所述端部之间与两者相接。
3.根据权利要求1或者2所述的半导体装置，其特征在于，
还具备势垒金属层，该势垒金属层形成于所述半导体基板与所述Cu电极之间，
所述无机膜形成为在所述势垒金属层的侧面与所述有机树脂膜之间，也与两者相接。
4.根据权利要求3所述的半导体装置，其特征在于，
所述Cu电极形成于所述势垒金属层的上表面的除其端部以外的区域，
所述无机膜形成为在所述有机树脂膜与所述势垒金属层的侧面以及所述上表面的所述端部之间，与两者相接。
5.根据权利要求1所述的半导体装置，其特征在于，
所述氧化防止膜含有：Ni、Ag、Sn、Al、Au或者包含它们的合金，所述氧化防止膜的厚度是10nm以上且小于100μm。
6.根据权利要求2所述的半导体装置，其特征在于，
所述第一氧化防止膜含有：Ni、Ag、Sn、Al、Au或者包含它们的合金，所述第一氧化防止膜的厚度是10nm以上且小于10μm。
7.根据权利要求2所述的半导体装置，其特征在于，
所述第二氧化防止膜含有：Ni、Ag、Sn、Al、Au或者包含它们的合金，所述第二氧化防止膜的厚度是10nm以上且小于100μm。
8.根据权利要求1至7中的任意一项所述的半导体装置，其特征在于，
所述无机膜包含SiON，厚度是30nm以上且小于10μm。
9.根据权利要求1至7中的任意一项所述的半导体装置，其特征在于，
所述无机膜包含SiN，厚度是30nm以上且小于10μm。
10.根据权利要求9所述的半导体装置，其特征在于，
所述无机膜包含折射率为2.4以上且小于2.7的半绝缘性的SiN。
11.根据权利要求1至9中的任意一项所述的半导体装置，其特征在于，
所述有机树脂膜的厚度是3μm以上且小于100μm。
12.根据权利要求1至11中的任意一项所述的半导体装置，其特征在于，
所述Cu电极的厚度是7μm以上且小于100μm。
13.根据权利要求1至12中的任意一项所述的半导体装置，其特征在于，
所述半导体基板是碳化硅基板。
CN201580005967.1A 2014-04-16 2015-02-16 半导体装置 Active CN105934813B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014084736 2014-04-16
JP2014-084736 2014-04-16
PCT/JP2015/054123 WO2015159579A1 (ja) 2014-04-16 2015-02-16 半導体装置

Publications (2)

Publication Number Publication Date
CN105934813A true CN105934813A (zh) 2016-09-07
CN105934813B CN105934813B (zh) 2019-03-22

Family

ID=54323797

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580005967.1A Active CN105934813B (zh) 2014-04-16 2015-02-16 半导体装置

Country Status (5)

Country Link
US (1) US9721915B2 (zh)
JP (1) JP5847363B1 (zh)
CN (1) CN105934813B (zh)
DE (1) DE112015001850T5 (zh)
WO (1) WO2015159579A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7472435B2 (ja) * 2019-05-13 2024-04-23 富士電機株式会社 半導体モジュールの製造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010008311A1 (en) * 2000-01-12 2001-07-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for fabricating the same and apparatus for chemical mechanical polishing and method of chemical mechanical polishing
JP2005079116A (ja) * 2003-08-29 2005-03-24 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
JP2006108233A (ja) * 2004-10-01 2006-04-20 Denso Corp 半導体装置の製造方法
US20080150623A1 (en) * 2006-12-26 2008-06-26 Megica Corporation Voltage Regulator Integrated with Semiconductor Chip
US20110186962A1 (en) * 2010-01-15 2011-08-04 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
CN102640292A (zh) * 2009-11-27 2012-08-15 株式会社半导体能源研究所 半导体装置和及其制造方法
JP2012186366A (ja) * 2011-03-07 2012-09-27 Panasonic Corp 半導体装置及びその製造方法
WO2013129253A1 (ja) * 2012-02-27 2013-09-06 日鉄住金マイクロメタル株式会社 パワー半導体装置及びその製造方法並びにボンディングワイヤ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3379575B2 (ja) 1998-11-19 2003-02-24 日本電気株式会社 Ｃｕ配線形成方法
JP3515449B2 (ja) 1999-10-13 2004-04-05 三洋電機株式会社 半導体装置の製造方法
JP2005243845A (ja) 2004-02-25 2005-09-08 Ebara Corp 基板処理方法及び基板処理装置
WO2007108439A1 (ja) 2006-03-22 2007-09-27 Mitsubishi Electric Corporation 電力用半導体装置
JP5273920B2 (ja) 2006-12-22 2013-08-28 ローム株式会社 半導体装置
JP2008258499A (ja) 2007-04-06 2008-10-23 Sanyo Electric Co Ltd 電極構造及び半導体装置
JP2010092895A (ja) 2008-10-03 2010-04-22 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010008311A1 (en) * 2000-01-12 2001-07-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for fabricating the same and apparatus for chemical mechanical polishing and method of chemical mechanical polishing
JP2005079116A (ja) * 2003-08-29 2005-03-24 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
JP2006108233A (ja) * 2004-10-01 2006-04-20 Denso Corp 半導体装置の製造方法
US20080150623A1 (en) * 2006-12-26 2008-06-26 Megica Corporation Voltage Regulator Integrated with Semiconductor Chip
CN102640292A (zh) * 2009-11-27 2012-08-15 株式会社半导体能源研究所 半导体装置和及其制造方法
US20110186962A1 (en) * 2010-01-15 2011-08-04 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
JP2012186366A (ja) * 2011-03-07 2012-09-27 Panasonic Corp 半導体装置及びその製造方法
WO2013129253A1 (ja) * 2012-02-27 2013-09-06 日鉄住金マイクロメタル株式会社 パワー半導体装置及びその製造方法並びにボンディングワイヤ

Also Published As

Publication number Publication date
US9721915B2 (en) 2017-08-01
CN105934813B (zh) 2019-03-22
US20160358874A1 (en) 2016-12-08
JPWO2015159579A1 (ja) 2017-04-13
WO2015159579A1 (ja) 2015-10-22
DE112015001850T5 (de) 2016-12-29
JP5847363B1 (ja) 2016-01-20

Similar Documents

Publication Publication Date Title
US11854926B2 (en) Semiconductor device with a passivation layer and method for producing thereof
US11043448B2 (en) Semiconductor device with vertically separated openings and manufacturing method thereof
TWI497644B (zh) 以石墨烯為基底的元件及其製造方法
CN104103684A (zh) 半导体器件和制造方法
KR20120022719A (ko) 반도체 장치 및 그 제조 방법
US20140084472A1 (en) Compound dielectric anti-copper-diffusion barrier layer for copper connection and manufacturing method thereof
JP2017073500A (ja) 窒化物半導体装置およびその製造方法
CN106601665A (zh) 半导体结构及其形成方法
TWI557944B (zh) 光電半導體晶片
CN114759089A (zh) 增强栅控能力的p型氮化镓器件及其制作方法
US10403747B2 (en) Gallium nitride/ aluminum gallium nitride semiconductor device and method of making a gallium nitride/ aluminum gallium nitride semiconductor device
CN105934813A (zh) 半导体装置
US20180254239A1 (en) FORMING METAL CAP LAYER OVER THROUGH-GLASS-VIAS (TGVs)
CN114639641A (zh) 用于提供水分和质子阻挡部的集成电路器件的钝化层
US8841210B1 (en) Semiconductor device manufacturing method and semiconductor device
KR20180037878A (ko) 반도체 소자 및 이의 제조 방법
KR101422387B1 (ko) 차세대 cmos 이미지센서 제조방법
CN110767650B (zh) 一种提高抗击穿能力的smim电容结构及制作方法
KR20090056045A (ko) 반도체 장치의 금속 배선 및 그 형성 방법
CN111293171A (zh) 一种igbt芯片的设计结构、产品结构及其制造方法
US11183443B2 (en) Semiconductor structure and method for manufacturing the same
CN217062066U (zh) 一种晶体三极管芯片和电子器件
CN107408531A (zh) 用于制造半导体本体的方法
CN112259607A (zh) 氮化镓半导体器件及其制备方法
CN110676380A (zh) 一种提高抗击穿能力的mim电容结构及制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant