CN105897254A - Exclusive-OR gate logical circuit based on memristors and MOS (Metal Oxide Semiconductor) transistors and implementation method thereof - Google Patents

Exclusive-OR gate logical circuit based on memristors and MOS (Metal Oxide Semiconductor) transistors and implementation method thereof Download PDF

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CN105897254A
CN105897254A CN201610325873.9A CN201610325873A CN105897254A CN 105897254 A CN105897254 A CN 105897254A CN 201610325873 A CN201610325873 A CN 201610325873A CN 105897254 A CN105897254 A CN 105897254A
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memristor
pmos
nmos tube
resistance
input
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CN105897254B (en
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魏榕山
李睿
王珏
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Fuzhou University
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Fuzhou University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

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  • Engineering & Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to an exclusive-OR gate logical circuit based on memristors and MOS (Metal Oxide Semiconductor) transistors. The exclusive-OR gate logical circuit comprises a first memristor M1, a second memristor M2, a first NMOS (N-channel Metal Oxide Semiconductor) transistor N1 and a second NMOS transistor N2, wherein a negative end of the first memristor M1 is taken as a first input end V1 which is connected with a source electrode of a first PMOS (P-channel Metal Oxide Semiconductor) transistor P1; a negative end of the second memristor M2 is taken as a second input end V2 which is connected with a source electrode of a second PMOS transistor P2; a positive end of the first memristor M1, a positive end of the second memristor M2, a grid electrode of the first PMOS transistor P1, a grid electrode of the second PMOS transistor P2, a grid electrode of the first NMOS transistor N1 and a grid electrode of the second NMOS transistor N2 are connected with one another; a drain electrode of the first PMOS transistor P1, a drain electrode of the second PMOS transistor P2, a drain electrode of the first NMOS transistor N1 and a drain electrode of the second NMOS transistor are connected with one another, and taken as output ends Vout; and a source electrode of the first NMOS transistor N1 and a source electrode of the second NMOS transistor N2 are connected with each other, and grounded. The invention also relates to an implementation method of the exclusive-OR gate logical circuit based on the memristors and the MOS transistors. Through adoption of the exclusive-OR gate logical circuit and the implementation method thereof, a novel thought is provided in order that the memristors can play roles in logical operations.

Description

A kind of XOR gate logic circuit based on memristor and metal-oxide-semiconductor and its implementation
Technical field
The present invention relates to a kind of XOR gate logic circuit based on memristor and metal-oxide-semiconductor and its implementation.
Background technology
XOR gate (XOR) is a kind of elementary logic circuit in digital circuit.When input is different, it is output as height Level；When inputting identical, output low level.XOR gate logic circuit in digital display circuit with other logic phase In conjunction with, jointly complete complexity logical operations function, as utilize XOR and non-or non-combined complete certain compile Decoding function etc..Traditional XOR gate logic circuit is mainly combined by multiple metal-oxide-semiconductors, and area is bigger.With Time, along with Moore's Law will terminate, metal-oxide-semiconductor size is difficult to reduce again, the area of conventional CMOS logic circuit Can not continue to diminish accordingly.Along with the appearance of novel microelectronic device, utilize Performances of Novel Nano-Porous meter level device and tradition MOS device combines research and development high performance logic circuits becomes an important research direction of current microelectric technique development.
Summary of the invention
In view of this, it is an object of the invention to provide a kind of XOR gate logic electricity based on memristor with metal-oxide-semiconductor Road and its implementation, the effect that can play in logical operations for memristor provides a kind of new thinking.
For achieving the above object, the present invention adopts the following technical scheme that a kind of based on memristor and metal-oxide-semiconductor different Or gate logic, it is characterised in that: include the first memristor M1 and the second memristor M2, described first memristor The negative terminal of device M1 connects as the source electrode of first input end V1 and the first PMOS P1, described second memristor The negative terminal of M2 connects as the source electrode of the second input V2 and the second PMOS P2；Also include the first NMOS tube N1 and the second NMOS tube N2, the anode of the first memristor M1, the anode of the second memristor M2, a PMOS The grid of pipe P1, the grid of the second PMOS P2, the grid of the first NMOS tube N1 and the second NMOS tube N2 Grid interconnect；The drain electrode of the first PMOS P1, the drain electrode of the second PMOS P2, the first NMOS tube The drain electrode of N1 interconnects and as output end vo ut, a described NMOS with the drain electrode of the second NMOS tube N2 The source electrode of pipe N1 and the source electrode of the second NMOS tube N2 interconnect and ground connection.
A kind of implementation method based on memristor Yu the XOR gate logic circuit of metal-oxide-semiconductor, it is characterised in that:
When first input end V1 is high level, and the second input V2 is low level, the electric current reverse flow of generation Crossing described first memristor M1, forward flows through described second memristor M2, so that the electricity of the first memristor M1 Resistance is gradually increased to resistance Roff during off state, when the resistance of the second memristor M2 is gradually decrease to opening Resistance Ron, positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is low level, a PMOS Pipe P1 turns on, the first NMOS tube N1, the second NMOS tube N2 and the cut-off of the second PMOS P2, output end vo ut For high level；
When first input end V1 is low level, and the second input V2 is high level, the electric current forward stream of generation Cross described first memristor M1, flow counterflow through described second memristor M2, so that the electricity of the first memristor M1 Resistance is gradually decrease to resistance Ron during opening, when the resistance of the second memristor M2 is gradually increased to off state Resistance Roff, positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is low level, the 2nd PMOS Pipe P2 turns on, the first NMOS tube N1, the second NMOS tube N2 and the cut-off of the first PMOS P1, output end vo ut For high level；
When first input end V1 and the second input V2 is all high level, no current flows through described first memristor Device M1 and the second memristor M2, the first NMOS tube N1 and the conducting of the second NMOS tube N2, the first PMOS P1 With the second PMOS P2 cut-off, output end vo ut is low level；
When first input end V1 and the second input V2 is all low level, the first NMOS tube N1, the 2nd NMOS Pipe N2, the first PMOS P1 and the second PMOS P2 are turned off, and output end vo ut is low level.
Further, positive terminal voltage V3 of described first memristor M1 and the second memristor M2 is
Wherein, V3 is the first memristor M1 and the positive terminal voltage of the second memristor M2, Ron be the first memristor M1 with Resistance during the second memristor M2 opening, Roff is the first memristor M1 and the second memristor M2 off state Time resistance.
Further, the computing the resistor value of described first memristor M1 and the second memristor M2 is as follows:
X (t)=∫ ki (t) f (x) dt
k = u v R o n D 2
Rmem(t)=Ronx+Roff(1-x)
Wherein, i (t) is the electric current that t flows through memristor；F (x) is window function；uvFor TiO in alloy i.e. memristor2-n Mobility；RonAnd RoffIt is respectively memristor and is all TiO at opening i.e. oxide2-nWith off state i.e. oxygen Compound is all TiO2Time resistance；D is doped layer TiO in memristor2-nWith non-doped layer TiO2Gross thickness；X (t) is Doped region and the position on undoped region border in t memristor.
The present invention compared with prior art has the advantages that the present invention utilizes the resistive rule of memristor, Build circuit in conjunction with metal-oxide-semiconductor and be successfully realized XOR function；The XOR circuit of the present invention and conventional MOS Pipe XOR circuit is compared, and has the advantages such as circuit is simple, area is little, low in energy consumption.The present invention is memristor The effect that can play in logical operations provides a kind of new thinking, and idea is novel, and thinking is feasible.
Accompanying drawing explanation
Fig. 1 is memristor model schematic.
Fig. 2 is the change in resistance curve chart of memristor model.
Fig. 3 is the XOR circuit figure of the present invention.
Fig. 4 is the XOR simulating, verifying figure of one embodiment of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment the present invention will be further described.
The resistance in memristor moment is current related with flow through before, and internal structure shows as doped region and mixes with non- The ratio in miscellaneous district determines current resistance, concrete resistance RmemComputing formula is as follows:
Rmem(t)=Ronx+Roff(1-x)
x = w D ∈ [ 0 , 1 ]
Wherein, RmemFor the resistance of memristor, x is doped region and the position on undoped region border in t memristor, As it is shown in figure 1, w is doped layer TiO in doped layer i.e. memristor2-nThickness, D is doped layer TiO in memristor2-n With non-doped layer TiO2Gross thickness, RonAnd RoffIt is respectively memristor and is all alloy at opening i.e. oxide TiO2-nIt is all undoped thing TiO with off state i.e. oxide2Time resistance.
In memristor, doped layer further relates to be therefore may be used with the electric current flow through with the Boundary Moving speed of non-doped layer Separately it is expressed as:
X (t)=∫ ki (t) f (x) dt
k = u v R o n D 2
Wherein: i (t) is the electric current that t flows through memristor；F (x) is window function；uvFor alloy i.e. memristor adulterate Thing TiO2-nMobility.
The Memorability of memristor passes through TiO2With TiO2-nBetween conversion embody.Recalling when electric current forward flows through During resistance device, oxygen atom is by TiO2-nLayer drifts to TiO2Layer so that certain thickness TiO2It is changed to TiO2-n.At this Under the change of sample, the electric conductivity of memristor constantly strengthens, and resistance reduces therewith.When electric current negative sense flows through memristor Time, oxygen atom is by TiO2Drift to TiO2-n, certain thickness TiO2-nIt is changed to TiO2, the electric conductivity of memristor is not Breaking and weaken, resistance increases the most therewith.The change in resistance characteristic of memristor refer to Fig. 2, applies to memristor anode One excitation Vin=5sin (10t) (unit: V), figure respectively illustrates excitation, flow through memristor electric current, The change procedure of three variablees of memristor resistance.
Refer to Fig. 3, the present invention provides a kind of XOR gate logic circuit based on memristor Yu metal-oxide-semiconductor: include One memristor M1 and the second memristor M2, the negative terminal of described first memristor M1 is as first input end V1 and The source electrode of one PMOS P1 connects, and the negative terminal of described second memristor M2 is as the second input V2 and second The source electrode of PMOS P2 connects；Also include the first NMOS tube N1 and the second NMOS tube N2, the first memristor M1 Anode, the anode of the second memristor M2, the grid of the first PMOS P1, the grid of the second PMOS P2, The grid of the first NMOS tube N1 and the grid of the second NMOS tube N2 interconnect, i.e. V3 end in figure；First The drain electrode of PMOS P1, the drain electrode of the second PMOS P2, drain electrode and the 2nd NMOS of the first NMOS tube N1 The drain electrode of pipe N2 interconnects and as output end vo ut, the source electrode of described first NMOS tube N1 and the 2nd NMOS The source electrode of pipe N2 interconnects and ground connection.
The present invention also provides for a kind of implementation method based on memristor Yu the XOR gate logic circuit of metal-oxide-semiconductor:
When first input end V1 is high level, and the second input V2 is low level, the electric current reverse flow of generation Crossing described first memristor M1, forward flows through described second memristor M2, so that the electricity of the first memristor M1 Resistance is gradually increased to resistance Roff during off state, when the resistance of the second memristor M2 is gradually decrease to opening Resistance Ron, positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is low level, a PMOS Pipe P1 turns on, the first NMOS tube N1, the second NMOS tube N2 and the cut-off of the second PMOS P2, output end vo ut For high level；
When first input end V1 is low level, and the second input V2 is high level, the electric current forward stream of generation Cross described first memristor M1, flow counterflow through described second memristor M2, so that the electricity of the first memristor M1 Resistance is gradually decrease to resistance Ron during opening, when the resistance of the second memristor M2 is gradually increased to off state Resistance Roff, positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is low level, the 2nd PMOS Pipe P2 turns on, the first NMOS tube N1, the second NMOS tube N2 and the cut-off of the first PMOS P1, output end vo ut For high level；
When first input end V1 and the second input V2 is all high level, no current flows through described first memristor Device M1 and the second memristor M2, the first NMOS tube N1 and the conducting of the second NMOS tube N2, the first PMOS P1 With the second PMOS P2 cut-off, output end vo ut is low level；
When first input end V1 and the second input V2 is all low level, the first NMOS tube N1, the 2nd NMOS Pipe N2, the first PMOS P1 and the second PMOS P2 are turned off, and output end vo ut is low level.
Further, positive terminal voltage V3 of described first memristor M1 and the second memristor M2 is
Wherein, V3 is the first memristor M1 and the positive terminal voltage of the second memristor M2, Ron be the first memristor M1 with Resistance during the second memristor M2 opening, Roff is the first memristor M1 and the second memristor M2 off state Time resistance.
For proving the correctness of circuit realiration logic XOR further, the present invention have input two impulse waveform emulation Demonstrating the function of circuit realiration XOR, waveform changes as shown in Figure 4, first input end V1, second defeated Enter to hold V2 to be Vpp=5V, T=100ms, the square wave of dutycycle 50%, it can be seen that when first is defeated When entering to hold V1, the second input V2 level identical, output Vout is low level, when first input end V1, During two input V2 level differences, output Vout is high level, circuit realiration XOR.The present invention patrols The output conversion speed of volume circuit is relevant with memristor ionic mobility and oxidated layer thickness, ionic mobility is the biggest, Oxidated layer thickness is the least, and conversion speed is the biggest.
Table 1 below show duty and the input results of each device:
Input M1 M2 N1 P1 N2 P2 Vout
V1V2=" 00 " Resistance is constant Resistance is constant Cut-off Cut-off Cut-off Cut-off 0
V1V2=" 01 " Low-resistance High resistant Cut-off Cut-off Cut-off Conducting 1
V1V2=" 10 " High resistant Low-resistance Cut-off Conducting Cut-off Cut-off 1
V1V2=" 11 " Resistance is constant Resistance is constant Conducting Cut-off Conducting Cut-off 0
Table 2 below show this enforcement simulation parameter:
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent Change and modify, all should belong to the covering scope of the present invention.

Claims (4)

1. an XOR gate logic circuit based on memristor Yu metal-oxide-semiconductor, it is characterised in that: include the first memristor Device M1 and the second memristor M2, the negative terminal of described first memristor M1 is as a first input end V1 and PMOS The source electrode of pipe P1 connects, and the negative terminal of described second memristor M2 is as the second input V2 and the second PMOS The source electrode of P2 connects；Also include the first NMOS tube N1 and the second NMOS tube N2, the anode of the first memristor M1, The anode of the second memristor M2, the grid of the first PMOS P1, the grid of the second PMOS P2, a NMOS The grid of pipe N1 and the grid of the second NMOS tube N2 interconnect；The drain electrode of the first PMOS P1, the 2nd PMOS The drain electrode of pipe P2, the drain electrode of the first NMOS tube N1 interconnect and as defeated with the drain electrode of the second NMOS tube N2 Going out and hold Vout, the source electrode of described first NMOS tube N1 and the source electrode of the second NMOS tube N2 interconnect and ground connection.
2. a realization based on memristor Yu the XOR gate logic circuit of metal-oxide-semiconductor according to claim 1 Method, it is characterised in that:
When first input end V1 is high level, and the second input V2 is low level, the electric current reverse flow of generation Crossing described first memristor M1, forward flows through described second memristor M2, so that the electricity of the first memristor M1 Resistance is gradually increased to resistance Roff during off state, when the resistance of the second memristor M2 is gradually decrease to opening Resistance Ron, positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is low level, a PMOS Pipe P1 turns on, the first NMOS tube N1, the second NMOS tube N2 and the cut-off of the second PMOS P2, output end vo ut For high level；
When first input end V1 is low level, and the second input V2 is high level, the electric current forward stream of generation Cross described first memristor M1, flow counterflow through described second memristor M2, so that the electricity of the first memristor M1 Resistance is gradually decrease to resistance Ron during opening, when the resistance of the second memristor M2 is gradually increased to off state Resistance Roff, positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is low level, the 2nd PMOS Pipe P2 turns on, the first NMOS tube N1, the second NMOS tube N2 and the cut-off of the first PMOS P1, output end vo ut For high level；
When first input end V1 and the second input V2 is all high level, no current flows through described first memristor Device M1 and the second memristor M2, the first NMOS tube N1 and the conducting of the second NMOS tube N2, the first PMOS P1 With the second PMOS P2 cut-off, output end vo ut is low level；
When first input end V1 and the second input V2 is all low level, the first NMOS tube N1, the 2nd NMOS Pipe N2, the first PMOS P1 and the second PMOS P2 are turned off, and output end vo ut is low level.
Realization side based on memristor Yu the XOR gate logic circuit of metal-oxide-semiconductor the most according to claim 2 Method, it is characterised in that: positive terminal voltage V3 of described first memristor M1 and the second memristor M2 is
Wherein, V3 is the first memristor M1 and the positive terminal voltage of the second memristor M2, Ron be the first memristor M1 with Resistance during the second memristor M2 opening, Roff is the first memristor M1 and the second memristor M2 off state Time resistance.
Realization side based on memristor Yu the XOR gate logic circuit of metal-oxide-semiconductor the most according to claim 2 Method, it is characterised in that: the computing the resistor value of described first memristor M1 and the second memristor M2 is as follows:
X (t)=∫ ki (t) f (x) dt
k = u v R on D 2
Rmem(t)=Ronx+Roff(1-x)
Wherein, i (t) is the electric current that t flows through memristor；F (x) is window function；uvFor TiO in alloy i.e. memristor2-n Mobility；RonAnd RoffIt is respectively memristor and is all TiO at opening i.e. oxide2-nWith off state i.e. oxygen Compound is all TiO2Time resistance；D is the gross thickness of oxide；X (t) is that in t memristor, doped region is mixed with non- The position on Za Qu border.
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CN109994139A (en) * 2019-03-15 2019-07-09 北京大学 A kind of complete non-volatile logic implementation method and its application based on unipolarity memristor
CN113098491A (en) * 2021-03-15 2021-07-09 杭州电子科技大学 Three-value logic circuit based on threshold type memristor
CN114204936A (en) * 2022-02-18 2022-03-18 苏州浪潮智能科技有限公司 Electronic equipment and logic gate circuit based on memristor thereof
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CN117595859A (en) * 2024-01-19 2024-02-23 山东云海国创云计算装备产业创新中心有限公司 Memristor-based logic circuit, output method and electronic equipment

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Cited By (10)

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Publication number Priority date Publication date Assignee Title
CN106941350A (en) * 2017-03-15 2017-07-11 东南大学 It is a kind of based on the NOR gate circuit and designing and manufacturing method of recalling group device
CN106941350B (en) * 2017-03-15 2020-04-14 东南大学 Memristor-based exclusive-OR gate circuit and design and manufacturing method
CN108449080A (en) * 2018-04-20 2018-08-24 西南大学 The full power-up road constituted based on CMOS inverter and memristor
CN109994139A (en) * 2019-03-15 2019-07-09 北京大学 A kind of complete non-volatile logic implementation method and its application based on unipolarity memristor
CN113098491A (en) * 2021-03-15 2021-07-09 杭州电子科技大学 Three-value logic circuit based on threshold type memristor
CN114204936A (en) * 2022-02-18 2022-03-18 苏州浪潮智能科技有限公司 Electronic equipment and logic gate circuit based on memristor thereof
CN114204936B (en) * 2022-02-18 2022-05-24 苏州浪潮智能科技有限公司 Electronic equipment and logic gate circuit based on memristor thereof
CN116488636A (en) * 2023-04-25 2023-07-25 南京邮电大学 Universal logic circuit based on memristor design
CN117595859A (en) * 2024-01-19 2024-02-23 山东云海国创云计算装备产业创新中心有限公司 Memristor-based logic circuit, output method and electronic equipment
CN117595859B (en) * 2024-01-19 2024-05-14 山东云海国创云计算装备产业创新中心有限公司 Memristor-based logic circuit, output method and electronic equipment

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