CN105897254B - A kind of exclusive or gate logic and its implementation method based on memristor and metal-oxide-semiconductor - Google Patents
A kind of exclusive or gate logic and its implementation method based on memristor and metal-oxide-semiconductor Download PDFInfo
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- CN105897254B CN105897254B CN201610325873.9A CN201610325873A CN105897254B CN 105897254 B CN105897254 B CN 105897254B CN 201610325873 A CN201610325873 A CN 201610325873A CN 105897254 B CN105897254 B CN 105897254B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
Abstract
The present invention relates to a kind of exclusive or gate logic based on memristor and metal-oxide-semiconductor, including the first memristor M1 and the second memristor M2, the negative terminal of first memristor M1 is connect as first input end V1 with the source electrode of the first PMOS tube P1, and the negative terminal of the second memristor M2 is connect as the second input terminal V2 with the source electrode of the second PMOS tube P2；Further include the first NMOS tube N1 and the second NMOS tube N2, the grid interconnection of the anode of the first memristor M1, the anode of the second memristor M2, the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2；The drain electrode of first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1 and the second NMOS tube N2 interconnect and as output end vo ut, and the source electrode of the source electrode of the first NMOS tube N1 and the second NMOS tube N2 interconnect and ground connection；The invention further relates to a kind of implementation methods of the exclusive or gate logic based on memristor and metal-oxide-semiconductor.The present invention provides a kind of new thinking for the effect that memristor can play in logical operation.
Description
Technical field
The present invention relates to a kind of exclusive or gate logic and its implementation method based on memristor and metal-oxide-semiconductor.
Background technology
XOR gate (XOR) is a kind of elementary logic circuit in digital circuit.When inputting different, export as high level；
When the input phase simultaneously, export low level.Exclusive or gate logic is combined in digital display circuit with other logics, common to complete again
Miscellaneous logical operation function, such as utilize exclusive or and non-or non-combined certain codec functions of completion.Traditional XOR gate is patrolled
It collects circuit to be mainly composed of multiple metal-oxide-semiconductors, area is larger.Meanwhile as Moore's Law will terminate, metal-oxide-semiconductor size is very
Difficult reduction, the area of conventional CMOS logic circuit cannot continue to become smaller accordingly.With the appearance of novel microelectronic device, profit
Research and development high performance logic circuits are combined to become the one of the development of current microelectric technique with Performances of Novel Nano-Porous meter level device and conventional MOS device
A important research direction.
Invention content
In view of this, the purpose of the present invention is to provide a kind of exclusive or gate logic based on memristor and metal-oxide-semiconductor and
Its implementation provides a kind of new thinking for the effect that memristor can play in logical operation.
To achieve the above object, the present invention adopts the following technical scheme that：A kind of XOR gate based on memristor and metal-oxide-semiconductor is patrolled
Collect circuit, it is characterised in that：Negative terminal including the first memristor M1 and the second memristor M2, the first memristor M1 is as
One input terminal V1 is connect with the source electrode of the first PMOS tube P1, and the negative terminal of the second memristor M2 is as the second input terminal V2 and
The source electrode of two PMOS tube P2 connects；Further include the first NMOS tube N1 and the second NMOS tube N2, the anode of the first memristor M1, second
The grid and second of the anode of memristor M2, the grid of the first PMOS tube P1, the grid of the second PMOS tube P2, the first NMOS tube N1
The grid of NMOS tube N2 interconnects；The drain electrode of first PMOS tube P1, the drain electrode of the second PMOS tube P2, the leakage of the first NMOS tube N1
Pole and the drain electrode of the second NMOS tube N2 interconnect and as output end vo ut, the source electrode and second of the first NMOS tube N1
The source electrode of NMOS tube N2 is interconnected and is grounded.
A kind of implementation method of the exclusive or gate logic based on memristor and metal-oxide-semiconductor, it is characterised in that：
When first input end V1 is high level, and the second input terminal V2 is low level, the electric current of generation flows counterflow through described
First memristor M1, forward direction flow through the second memristor M2, to make the resistance of the first memristor M1 gradually increase to shutdown
The resistance of resistance Roff when state, the second memristor M2 are gradually decrease to resistance Ron when open state, the first memristor M1 and
The positive terminal voltage V3 of two memristor M2 is low level, the first PMOS tube P1 conducting, the first NMOS tube N1, the second NMOS tube N2 and the
Two PMOS tube P2 cut-offs, output end vo ut is high level；
When first input end V1 is low level, and the second input terminal V2 is high level, the electric current forward direction of generation flows through described
First memristor M1 flows counterflow through the second memristor M2, to make the resistance of the first memristor M1 be gradually decrease to open
Resistance Roff when the resistance of resistance Ron when state, the second memristor M2 gradually increase to off state, the first memristor M1 and
The positive terminal voltage V3 of two memristor M2 is low level, the second PMOS tube P2 conducting, the first NMOS tube N1, the second NMOS tube N2 and the
One PMOS tube P1 cut-offs, output end vo ut is high level；
When first input end V1 and the second input terminal V2 are all high level, no current flow through the first memristor M1 with
Second memristor M2, the first NMOS tube N1 are connected with the second NMOS tube N2, and the first PMOS tube P1 and the second PMOS tube P2 end, defeated
Outlet Vout is low level；
When first input end V1 and the second input terminal V2 are all low level, the first NMOS tube N1, the second NMOS tube N2,
One PMOS tube P1 is turned off with the second PMOS tube P2, and output end vo ut is low level.
Further, the positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is
Wherein, V3 is the positive terminal voltage of the first memristor M1 and the second memristor M2, and Ron is the first memristor M1 and second
Resistance when memristor M2 open states, resistance when Roff is the first memristor M1 and the second memristor M2 off states.
Further, the computing the resistor value of the first memristor M1 and the second memristor M2 are as follows：
X (t)=∫ ki (t) f (x) dt
Rmem(t)=Ronx+Roff(1-x)
Wherein, i (t) is the electric current that t moment flows through memristor；F (x) is window function；uvFor in dopant, that is, memristor
TiO2-nMobility；RonAnd RoffRespectively memristor is all TiO in open state, that is, oxide2-nIt is aoxidized with off state
Object is all TiO2When resistance；D is doped layer TiO in memristor2-nWith non-doped layer TiO2Overall thickness；X (t) recalls for t moment
Hinder the position of doped region and undoped region boundary in device.
The present invention has the advantages that compared with prior art：The present invention utilizes the resistive rule of memristor, in conjunction with
Metal-oxide-semiconductor builds circuit and is successfully realized XOR logic function；The XOR circuit of the present invention and conventional MOS pipe XOR logic electricity
Road is compared, and has many advantages, such as that circuit is simple, area is small, low in energy consumption.The present invention is the work that memristor can play in logical operation
With a kind of new thinking is provided, idea is novel, and thinking is feasible.
Description of the drawings
Fig. 1 is memristor model schematic.
Fig. 2 is the change in resistance curve graph of memristor model.
Fig. 3 is the XOR circuit figure of the present invention.
Fig. 4 is the XOR logic simulating, verifying figure of one embodiment of the invention.
Specific implementation mode
The present invention will be further described with reference to the accompanying drawings and embodiments.
The resistance at memristor moment with flow through before current related, internal structure shows as doped region and undoped region
Ratio determine current resistance value, specific resistance value RmemCalculation formula is as follows：
Rmem(t)=Ronx+Roff(1-x)
Wherein, RmemFor the resistance value of memristor, x is the position of doped region and undoped region boundary in t moment memristor, such as
Shown in Fig. 1, w is doped layer TiO in doped layer, that is, memristor2-nThickness, D be memristor in doped layer TiO2-nWith non-doped layer
TiO2Overall thickness, RonAnd RoffRespectively memristor is all dopant TiO in open state, that is, oxide2-nIt is with off state
Oxide is all undoped object TiO2When resistance.
In memristor the Boundary Moving speed of doped layer and non-doped layer further related to the electric current flowed through be, therefore can another table
It is shown as：
X (t)=∫ ki (t) f (x) dt
Wherein：I (t) is the electric current that t moment flows through memristor；F (x) is window function；uvTo be mixed in dopant, that is, memristor
Sundries TiO2-nMobility.
The Memorability of memristor passes through TiO2With TiO2-nBetween conversion embody.Memristor is being flowed through when electric current forward direction
When device, oxygen atom is by TiO2-nLayer drifts to TiO2Layer so that certain thickness TiO2Variation is TiO2-n.Under such variation,
The electric conductivity of memristor constantly enhances, and resistance reduces therewith.When electric current negative sense flows through memristor, oxygen atom is by TiO2It drifts to
TiO2-n, certain thickness TiO2-nVariation is TiO2, the electric conductivity of memristor constantly weakens, and resistance also increases therewith.Memristor
Change in resistance characteristic please refer to Fig. 2, to memristor anode apply one excitation Vin=5sin (10t) (unit：V), in figure respectively
Show excitation, three electric current for flowing through memristor, memristor resistance variables change procedure.
Fig. 3 is please referred to, the present invention provides a kind of exclusive or gate logic based on memristor and metal-oxide-semiconductor：Recall including first
Hinder source of the negative terminal of device M1 and the second memristor M2, the first memristor M1 as first input end V1 and the first PMOS tube P1
Pole connects, and the negative terminal of the second memristor M2 is connect as the second input terminal V2 with the source electrode of the second PMOS tube P2；Further include
First NMOS tube N1 and the second NMOS tube N2, the anode of the first memristor M1, the anode of the second memristor M2, the first PMOS tube P1
Grid, the grid of the second PMOS tube P2, the grid of the first NMOS tube N1 and the second NMOS tube N2 grid interconnect, that is, scheme
In the ends V3；The drain electrode of first PMOS tube P1, the drain electrode of the second PMOS tube P2, the drain electrode of the first NMOS tube N1 and the second NMOS tube
The drain electrode of N2 interconnects and as output end vo ut, and the source electrode of the source electrode and the second NMOS tube N2 of the first NMOS tube N1 is mutual
It is connected and is grounded.
The present invention also provides a kind of implementation methods of the exclusive or gate logic based on memristor and metal-oxide-semiconductor：
When first input end V1 is high level, and the second input terminal V2 is low level, the electric current of generation flows counterflow through described
First memristor M1, forward direction flow through the second memristor M2, to make the resistance of the first memristor M1 gradually increase to shutdown
The resistance of resistance Roff when state, the second memristor M2 are gradually decrease to resistance Ron when open state, the first memristor M1 and
The positive terminal voltage V3 of two memristor M2 is low level, the first PMOS tube P1 conducting, the first NMOS tube N1, the second NMOS tube N2 and the
Two PMOS tube P2 cut-offs, output end vo ut is high level；
When first input end V1 is low level, and the second input terminal V2 is high level, the electric current forward direction of generation flows through described
First memristor M1 flows counterflow through the second memristor M2, to make the resistance of the first memristor M1 be gradually decrease to open
Resistance Roff when the resistance of resistance Ron when state, the second memristor M2 gradually increase to off state, the first memristor M1 and
The positive terminal voltage V3 of two memristor M2 is low level, the second PMOS tube P2 conducting, the first NMOS tube N1, the second NMOS tube N2 and the
One PMOS tube P1 cut-offs, output end vo ut is high level；
When first input end V1 and the second input terminal V2 are all high level, no current flow through the first memristor M1 with
Second memristor M2, the first NMOS tube N1 are connected with the second NMOS tube N2, and the first PMOS tube P1 and the second PMOS tube P2 end, defeated
Outlet Vout is low level；
When first input end V1 and the second input terminal V2 are all low level, the first NMOS tube N1, the second NMOS tube N2,
One PMOS tube P1 is turned off with the second PMOS tube P2, and output end vo ut is low level.
Further, the positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is
Wherein, V3 is the positive terminal voltage of the first memristor M1 and the second memristor M2, and Ron is the first memristor M1 and second
Resistance when memristor M2 open states, resistance when Roff is the first memristor M1 and the second memristor M2 off states.
Further to prove that circuit realizes that the correctness of logic exclusive or, the present invention have input two impulse waveform simulating, verifyings
Circuit realizes that the function of XOR logic, waveform change as shown in figure 4, first input end V1, the second input terminal V2 are Vpp=
The square wave of 5V, T=100ms, duty ratio 50%, it can be seen from the figure that when first input end V1, the second input terminal V2 level phases
Meanwhile it is low level to export Vout, when first input end V1, the second input terminal V2 level differences, output Vout is high level,
Circuit realizes XOR logic.The output conversion speed of the logic circuit of the present invention and memristor ionic mobility and oxidated layer thickness
Related, ionic mobility is bigger, oxidated layer thickness is smaller, and conversion speed is bigger.
The following table 1 show the working condition and input results of each device：
| Input | M1 | M2 | N1 | P1 | N2 | P2 | Vout |
| V1V2=" 00 " | Resistance value is constant | Resistance value is constant | Cut-off | Cut-off | Cut-off | Cut-off | 0 |
| V1V2=" 01 " | Low-resistance | High resistant | Cut-off | Cut-off | Cut-off | Conducting | 1 |
| V1V2=" 10 " | High resistant | Low-resistance | Cut-off | Conducting | Cut-off | Cut-off | 1 |
| V1V2=" 11 " | Resistance value is constant | Resistance value is constant | Conducting | Cut-off | Conducting | Cut-off | 0 |
The following table 2 show this implementation simulation parameter：
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent with
Modification should all belong to the covering scope of the present invention.
Claims (4)
1. a kind of exclusive or gate logic based on memristor and metal-oxide-semiconductor, it is characterised in that：Including the first memristor M1 and second
The negative terminal of memristor M2, the first memristor M1 are connect as first input end V1 with the source electrode of the first PMOS tube P1, described
The negative terminal of second memristor M2 is connect as the second input terminal V2 with the source electrode of the second PMOS tube P2；Further include the first NMOS tube N1
With the second NMOS tube N2, the anode of the first memristor M1, the anode of the second memristor M2, the grid of the first PMOS tube P1, second
The grid of the grid of PMOS tube P2, the grid of the first NMOS tube N1 and the second NMOS tube N2 interconnects；First PMOS tube P1's
The drain electrode interconnection and conduct of drain electrode, the drain electrode of the second PMOS tube P2, the drain electrode of the first NMOS tube N1 with the second NMOS tube N2
The source electrode of output end vo ut, the first NMOS tube N1 and the source electrode of the second NMOS tube N2 are interconnected and are grounded.
2. a kind of implementation method of the exclusive or gate logic according to claim 1 based on memristor and metal-oxide-semiconductor, special
Sign is：
When first input end V1 is high level, and the second input terminal V2 is low level, the electric current of generation flows counterflow through described first
Memristor M1, forward direction flow through the second memristor M2, to make the resistance of the first memristor M1 gradually increase to off state
When resistance Roff, the second memristor M2 resistance be gradually decrease to resistance Ron when open state, the first memristor M1 recalls with second
The positive terminal voltage V3 for hindering device M2 is low level, the first PMOS tube P1 conductings, the first NMOS tube N1, the second NMOS tube N2 and second
PMOS tube P2 cut-offs, output end vo ut are high level；
When first input end V1 is low level, and the second input terminal V2 is high level, the electric current forward direction of generation flows through described first
Memristor M1 flows counterflow through the second memristor M2, to make the resistance of the first memristor M1 be gradually decrease to open state
When resistance Ron, resistance Roff when the resistance of the second memristor M2 gradually increases to off state, the first memristor M1 recall with second
The positive terminal voltage V3 for hindering device M2 is low level, the second PMOS tube P2 conductings, the first NMOS tube N1, the second NMOS tube N2 and first
PMOS tube P1 cut-offs, output end vo ut are high level；
When first input end V1 and the second input terminal V2 are all high level, no current flows through the first memristor M1 and second
Memristor M2, the first NMOS tube N1 are connected with the second NMOS tube N2, and the first PMOS tube P1 and the second PMOS tube P2 end, output end
Vout is low level；
When first input end V1 and the second input terminal V2 are all low level, the first NMOS tube N1, the second NMOS tube N2, first
PMOS tube P1 is turned off with the second PMOS tube P2, and output end vo ut is low level.
3. the implementation method of the exclusive or gate logic according to claim 2 based on memristor and metal-oxide-semiconductor, feature exist
In：The positive terminal voltage V3 of the first memristor M1 and the second memristor M2 is
Wherein, V3 is the positive terminal voltage of the first memristor M1 and the second memristor M2, and Ron is the first memristor M1 and the second memristor
Resistance when device M2 open states, resistance when Roff is the first memristor M1 and the second memristor M2 off states.
4. the implementation method of the exclusive or gate logic according to claim 2 based on memristor and metal-oxide-semiconductor, feature exist
In：The computing the resistor value of the first memristor M1 and the second memristor M2 are as follows：
Wherein,ForMoment flows through the electric current of memristor；；ForIt is adulterated in moment memristor
The position in area and undoped region boundary；For in dopant, that is, memristorMobility；WithRespectively memristor
It is all in open state, that is, oxideIt is all with off state, that is, oxideWhen resistance；For the total of oxide
Thickness；ForThe position of doped region and undoped region boundary in moment memristor.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106941350B (en) * | 2017-03-15 | 2020-04-14 | 东南大学 | Memristor-based exclusive-OR gate circuit and design and manufacturing method |
| CN108449080B (en) * | 2018-04-20 | 2020-06-05 | 西南大学 | Full-adding circuit formed based on CMOS inverter and memristor |
| CN109994139B (en) * | 2019-03-15 | 2020-11-03 | 北京大学 | Complete non-volatile logic implementation method based on unipolar memristor and application thereof |
| CN113098491A (en) * | 2021-03-15 | 2021-07-09 | 杭州电子科技大学 | Three-value logic circuit based on threshold type memristor |
| CN114204936B (en) * | 2022-02-18 | 2022-05-24 | 苏州浪潮智能科技有限公司 | Electronic equipment and logic gate circuit based on memristor thereof |
| CN116488636A (en) * | 2023-04-25 | 2023-07-25 | 南京邮电大学 | Universal logic circuit based on memristor design |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902857B1 (en) * | 2010-04-08 | 2011-03-08 | The United States Of America As Represented By The Secretary Of The Air Force | Reconfigurable electronic circuit |
| CN102811051A (en) * | 2012-07-09 | 2012-12-05 | 华中科技大学 | Memristor-based logical gate circuit |
| CN205622621U (en) * | 2016-05-17 | 2016-10-05 | 福州大学 | Anticoincidence gate logic circuit based on recall and hinder ware and MOS pipe |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8274312B2 (en) * | 2011-02-25 | 2012-09-25 | The United States Of America As Represented By The Secretary Of The Air Force | Self-reconfigurable memristor-based analog resonant computer |
-
2016
- 2016-05-17 CN CN201610325873.9A patent/CN105897254B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902857B1 (en) * | 2010-04-08 | 2011-03-08 | The United States Of America As Represented By The Secretary Of The Air Force | Reconfigurable electronic circuit |
| CN102811051A (en) * | 2012-07-09 | 2012-12-05 | 华中科技大学 | Memristor-based logical gate circuit |
| CN205622621U (en) * | 2016-05-17 | 2016-10-05 | 福州大学 | Anticoincidence gate logic circuit based on recall and hinder ware and MOS pipe |
Non-Patent Citations (1)
| Title |
|---|
| "A hybrid memristor-CMOS XOR gate for nonvolatile logic computation";yaxiong zhou;《Phys. Status Solidi A》;20151209;第1051页第3段，图2a * |
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