CN209514542U - A kind of reset circuit - Google Patents
A kind of reset circuit Download PDFInfo
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- CN209514542U CN209514542U CN201920365365.2U CN201920365365U CN209514542U CN 209514542 U CN209514542 U CN 209514542U CN 201920365365 U CN201920365365 U CN 201920365365U CN 209514542 U CN209514542 U CN 209514542U
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- 239000004065 semiconductor Substances 0.000 claims description 169
- 239000003990 capacitor Substances 0.000 claims description 22
- 230000005611 electricity Effects 0.000 claims description 7
- 230000000739 chaotic effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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Abstract
The utility model discloses a kind of reset circuits, including delay circuit and comparison circuit, delay circuit can make chip power on enough delay times from power-down state to guarantee that system enters original state, it works to receive various instructions at any time, comparison circuit, wherein comprising being monitored to reference voltage value, it can start chaotic situation to avoid when mains fluctuations are larger and drop to certain value chip logic, chip can be resetted in time, so that chip returns on correct logical road.The utility model is improved for the easily chaotic problem of logic caused by existing chip reset inaccuracy.The utility model has many advantages, such as that reseting performance is excellent, circuit structure is simple and at low cost.
Description
Technical field
The utility model relates to a kind of battery management system technical field more particularly to a kind of reset circuits.
Background technique
At present on the research and development road of electric car, the research of power battery and its management system is in occupation of very
Important position, how is the performance of electric car, and depending on the performance of its power battery, wherein the charge-discharge performance of battery is to close
Key factor, the principal element for influencing electric car popularization and application includes the safety and use cost problem of power battery, is extended
The service life of battery is to reduce one of the effective way of use cost, with the rapid development of new and high technology, to ensure battery
It is functional, extend battery, more and more occasions carry out rationally effective management to battery using integrated chip
And control, but for integrated chip, when reset one of vital function, reset can be such that circuit initializes, and make
Circuit can be executed according to the thought sequence of designer.If reset circuit does not design, may when powering on or
Circuit is set to enter unknown state when power-supply fluctuation, work will be chaotic.For this purpose, preferably executing reset function is the utility model
Problem to be solved, to guarantee that reseting performance is excellent, circuit structure is simple and at low cost.
Utility model content
The purpose of the utility model is to overcome the deficiencies in the prior art, provide a kind of reset circuit, existing to solve
The technical problem of the easy confusion of chip logic caused by reset inaccuracy in technology etc..
The utility model is achieved through the following technical solutions: the utility model discloses a kind of reset circuits, including
Delay circuit and comparison circuit:
Delay circuit includes the first phase inverter, the second phase inverter, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, first
Capacitor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, first resistor and second resistance, the input terminal of the first phase inverter are postpones signal input
End, the output end of the first phase inverter connect with the grid of the first metal-oxide-semiconductor, the drain electrode of the first metal-oxide-semiconductor, the second metal-oxide-semiconductor grid and
The gate connected in parallel of 4th metal-oxide-semiconductor connects and is set as bias current inputs, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and third metal-oxide-semiconductor
Source grounding, connect with the source electrode of the 4th metal-oxide-semiconductor after the drain series first resistor of the second metal-oxide-semiconductor, the 3rd MOS pipe
It is connect after drain series second resistance with the source electrode of the 5th metal-oxide-semiconductor, the gate connected in parallel of the grid of third metal-oxide-semiconductor and the 5th metal-oxide-semiconductor
It being connect afterwards with the source electrode of the 4th metal-oxide-semiconductor, the drain electrode of the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is in parallel and is set as operating voltage input terminal,
The gate connected in parallel of 4th metal-oxide-semiconductor is connected with first capacitor, another pin ground connection of first capacitor, the input terminal of the second phase inverter with
The drain electrode of third metal-oxide-semiconductor connects, and the output end of the second phase inverter is postpones signal output end；
It is powered on for the first time after power-off, postpones signal input terminal input low level off-position, while chip is defeated from bigoted electric current
Enter end and provide the conducting voltage of metal-oxide-semiconductor for delay circuit, the first metal-oxide-semiconductor only in postpones signal input terminal input low level into
Row conducting, first capacitor is equivalent to short circuit at this time, and the grid of the 4th metal-oxide-semiconductor is in low level so ending, when first capacitor is filled
Electricity terminates, and the grid of the 4th metal-oxide-semiconductor becomes high level and simultaneously turns on, and the setting of first resistor and second resistance is to guarantee
3rd MOS pipe and the 5th metal-oxide-semiconductor are at while conducting and determine that the drain electrode of the 5th metal-oxide-semiconductor always exports low level, thus
So that postpones signal output end always exports high level, to start comparison circuit.
Comparison circuit includes comparator, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth MOS
Pipe, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and the second capacitor, the grid of the 6th metal-oxide-semiconductor with prolong
Slow signal output end connection, the drain electrode of the 6th metal-oxide-semiconductor are reference voltage input terminal, the source electrode and 3rd resistor string of the 6th metal-oxide-semiconductor
The positive input terminal of comparator is connected after connection, the negative input end of comparator is benchmark comparison voltage input terminal, the positive input of comparator
End is also connected with the 4th resistance, and with being followed by, the grid of the 7th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is simultaneously for the 4th resistance and the series connection of the 5th resistance
It is connect after connection connection with the output end of comparator, the drain electrode of the 7th metal-oxide-semiconductor is connect with operating voltage input terminal, the 7th metal-oxide-semiconductor
Sources connected in parallel is connected with the grid of the 6th resistance and the tenth metal-oxide-semiconductor, and the drain electrode of the 9th metal-oxide-semiconductor is connected in parallel to the 8th metal-oxide-semiconductor
Grid and the 6th resistance, the drain electrode of the 8th metal-oxide-semiconductor are connected to the junction of the 4th resistance and the 5th resistance, the source of the 8th metal-oxide-semiconductor
Pole, the source electrode of the 9th metal-oxide-semiconductor and the tenth metal-oxide-semiconductor source grounding, the drain electrode of the tenth metal-oxide-semiconductor be connected in parallel to the 7th resistance and
Another pin of second capacitor, the 7th resistance is connect with reference voltage input terminal, another pin ground connection of the second capacitor, and the tenth
The drain electrode of metal-oxide-semiconductor is reset signal output end.
The high level of postpones signal output end output guarantees that the 6th metal-oxide-semiconductor is in the conductive state, when powering on for the first time, referring to electricity
Pressure gives the second capacitor charging by the 7th resistance, and the second capacitor is equivalent to short circuit at this time, i.e. reset signal output end exports low electricity
Flat, at the end of the second capacitor charging, just extremely high potential, i.e. chip reset terminate.Wherein comparator, the 6th metal-oxide-semiconductor, the 7th
MOS pipe, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, 3rd resistor, the 4th resistance, the 5th resistance and the 6th resistance composition
One reference voltage observation circuit, when the voltage of reference voltage input terminal be less than certain value when, reference voltage observation circuit it is defeated
It is out the drain electrode output low level of the tenth metal-oxide-semiconductor, i.e. chip starts to reset again, when the voltage of reference voltage input terminal is greater than one
When definite value, chip reset terminates.
Preferably, for the signal flow in preferably control circuit, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and third metal-oxide-semiconductor
It is depletion type NMOS tube；4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor are depletion type PMOS tube.
Preferably, in order to formed can preferably in control circuit while current mirror provides stabling current signal
Outflow, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor and the tenth metal-oxide-semiconductor are enhanced metal-oxide-semiconductor.
The utility model discloses a kind of reset circuits, compared with prior art: the utility model include delay circuit and
Comparison circuit, delay circuit can make chip power on enough delay times from power-down state to guarantee that system enters initial shape
State works to receive various instructions at any time, comparison circuit, wherein can keep away comprising being monitored to reference voltage value
Exempt to start chaotic situation when mains fluctuations are larger and drop to certain value chip logic, chip can be answered in time
Position, so that chip returns on correct logical road.The utility model is excellent with reseting performance, circuit structure is simple
With equal advantage at low cost.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model；
Fig. 2 is the structural schematic diagram of delay circuit；
Fig. 3 is the structural schematic diagram of comparison circuit.
Specific embodiment
It elaborates below to the embodiments of the present invention, the present embodiment before being with technical solutions of the utility model
It puts and is implemented, the detailed implementation method and specific operation process are given, but the protection scope of the utility model is unlimited
In following embodiments.
Embodiment 1
Embodiment 1 discloses a kind of reset circuit, as shown in Figure 1, including delay circuit 1 and comparison circuit 2:
As shown in Fig. 2, delay circuit 1 includes the first phase inverter 101, the second phase inverter 102, the first metal-oxide-semiconductor 103, second
Metal-oxide-semiconductor 104, third metal-oxide-semiconductor 105, first capacitor 106, the 4th metal-oxide-semiconductor 107, the 5th metal-oxide-semiconductor 108, first resistor 109 and
The resistance value of two resistance 110, first resistor 109 and second resistance 110 is disposed as 500K Ω.The input terminal of first phase inverter 101
For postpones signal input terminal 112, the output end of the first phase inverter 101 is connect with the grid of the first metal-oxide-semiconductor 103, the first metal-oxide-semiconductor
The gate connected in parallel of 103 drain electrode, the grid of the second metal-oxide-semiconductor 104 and the 4th metal-oxide-semiconductor 107 connects and is set as bias current input
End 111, the source grounding of the first metal-oxide-semiconductor 103, the second metal-oxide-semiconductor 104 and third metal-oxide-semiconductor 105, the drain electrode of the second metal-oxide-semiconductor 104
It is connect after series connection first resistor 109 with the source electrode of the 4th metal-oxide-semiconductor 107, after the drain series second resistance 110 of third metal-oxide-semiconductor 105
It is connect with the source electrode of the 5th metal-oxide-semiconductor 108, with the 4th after the gate connected in parallel of the grid of third metal-oxide-semiconductor 105 and the 5th MOS pipe 108
The source electrode of metal-oxide-semiconductor 107 connects, and the drain electrode of the 4th metal-oxide-semiconductor 107 and the 5th metal-oxide-semiconductor 108 is in parallel and is set as operating voltage input terminal
114, the gate connected in parallel of the 4th metal-oxide-semiconductor 107 is connected with first capacitor 106, another pin ground connection of first capacitor 106, the first electricity
Hold 106 and be set as 16pF, the input terminal of the second phase inverter 102 is connect with the drain electrode of the 3rd MOS pipe 105, the second phase inverter 102
Output end be postpones signal output end 113；First metal-oxide-semiconductor 103, the second metal-oxide-semiconductor 104 and third metal-oxide-semiconductor 105 are to exhaust
Type NMOS tube；4th metal-oxide-semiconductor 107 and the 5th metal-oxide-semiconductor 108 are depletion type PMOS tube.
As shown in figure 3, comparison circuit 2 includes comparator 201, the 6th metal-oxide-semiconductor 202, the 7th metal-oxide-semiconductor 203, the 8th MOS pipe
204, the 9th metal-oxide-semiconductor 205, the tenth metal-oxide-semiconductor 206,3rd resistor 207, the 4th resistance 208, the 5th resistance 209, the 6th resistance
210, the 7th resistance 211 and the second capacitor 212, the grid of the 6th metal-oxide-semiconductor 202 are connect with postpones signal output end 113, and the 6th
The drain electrode of metal-oxide-semiconductor 202 is reference voltage input terminal 215, and the source electrode of the 6th metal-oxide-semiconductor 202 connects after connecting with 3rd resistor 207
The negative input end of the positive input terminal of comparator 201, comparator 201 is benchmark comparison voltage input terminal 213, and comparator 201 is just
Input terminal is also connected with the 4th resistance 208, is grounded after the 4th resistance 208 and the series connection of the 5th resistance 209, the 7th metal-oxide-semiconductor 211 and the
It is connect after the gate connected in parallel connection of nine metal-oxide-semiconductors 205 with the output end of comparator 201, the drain electrode of the 7th metal-oxide-semiconductor 203 and work electricity
Input terminal 114 is pressed to connect, the sources connected in parallel of the 7th metal-oxide-semiconductor 203 is connected with the grid of the 6th resistance 210 and the tenth metal-oxide-semiconductor 206,
The drain electrode of 9th metal-oxide-semiconductor 205 is connected in parallel to the grid and the 6th resistance 210 of the 8th metal-oxide-semiconductor 204, the leakage of the 8th metal-oxide-semiconductor 204
Pole is connected to the junction of the 4th resistance 208 and the 5th resistance 209, the source of the source electrode of the 8th metal-oxide-semiconductor 204, the 9th metal-oxide-semiconductor 205
The source grounding of pole and the tenth metal-oxide-semiconductor 206, the drain electrode of the tenth metal-oxide-semiconductor 206 are connected in parallel to the 7th resistance 211 and the second electricity
Hold 212, another pin of the 7th resistance 211 is connect with reference voltage input terminal 215, and another pin of the second capacitor 212 connects
Ground, the drain electrode of the tenth metal-oxide-semiconductor 206 are reset signal output end 214.6th metal-oxide-semiconductor 202, the 7th metal-oxide-semiconductor 203, the 8th metal-oxide-semiconductor
204, the 9th metal-oxide-semiconductor 205 and the tenth metal-oxide-semiconductor 206 are enhanced metal-oxide-semiconductor.
Claims (3)
1. a kind of reset circuit, which is characterized in that including delay circuit and comparison circuit:
The delay circuit includes the first phase inverter, the second phase inverter, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, first
Capacitor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, first resistor and second resistance, the input terminal of first phase inverter are postpones signal
Input terminal, the output end of first phase inverter are connect with the grid of first metal-oxide-semiconductor, the drain electrode of first metal-oxide-semiconductor,
The grid of two metal-oxide-semiconductors connects and is set as bias current inputs, the first MOS with the gate connected in parallel of the 4th metal-oxide-semiconductor
It manages, the source grounding of the second metal-oxide-semiconductor and the third metal-oxide-semiconductor, after first resistor described in the drain series of second metal-oxide-semiconductor
Connect with the source electrode of the 4th metal-oxide-semiconductor, after second resistance described in the drain series of the third metal-oxide-semiconductor with the 5th MOS
The source electrode of pipe connects, after the gate connected in parallel of the grid of the third metal-oxide-semiconductor and the 5th metal-oxide-semiconductor with the 4th metal-oxide-semiconductor
Source electrode connection, the drain electrode of the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor is in parallel to be simultaneously set as operating voltage input terminal, and described the
The gate connected in parallel of four metal-oxide-semiconductors is connected with the first capacitor, another pin ground connection of the first capacitor, second phase inverter
Input terminal connect with the drain electrode of the third metal-oxide-semiconductor, the output end of second phase inverter is postpones signal output end；
The comparison circuit include comparator, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor,
3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and the second capacitor, the grid of the 6th metal-oxide-semiconductor with
The postpones signal output end connection, the drain electrode of the 6th metal-oxide-semiconductor are reference voltage input terminal, the source of the 6th metal-oxide-semiconductor
Pole connects the positive input terminal of the comparator after connecting with the 3rd resistor, compare on the basis of the negative input end of the comparator
Voltage input end, the positive input terminal of the comparator are also connected with the 4th resistance, the 4th resistance and the 5th electricity
It is grounded after resistance series connection, the output end after the gate connected in parallel connection of the 7th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor with the comparator
Connection, the drain electrode of the 7th metal-oxide-semiconductor are connect with the operating voltage input terminal, the sources connected in parallel connection of the 7th metal-oxide-semiconductor
There is the grid of the 6th resistance and the tenth metal-oxide-semiconductor, the drain electrode of the 9th metal-oxide-semiconductor is connected in parallel to the 8th MOS
The grid of pipe and the 6th resistance, the drain electrode of the 8th metal-oxide-semiconductor are connected to the 4th resistance and the 5th resistance
Junction, source electrode, the source electrode of the 9th metal-oxide-semiconductor and the source grounding of the tenth metal-oxide-semiconductor of the 8th metal-oxide-semiconductor, described
The drain electrode of ten metal-oxide-semiconductors is connected in parallel to the 7th resistance and second capacitor, another pin of the 7th resistance and institute
The connection of reference voltage input terminal is stated, another pin ground connection of second capacitor, the drain electrode of the tenth metal-oxide-semiconductor is reset signal
Output end.
2. reset circuit as described in claim 1, which is characterized in that first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the third
Metal-oxide-semiconductor is depletion type NMOS tube；4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor are depletion type PMOS tube.
3. reset circuit as described in claim 1, which is characterized in that the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor,
9th metal-oxide-semiconductor and the tenth metal-oxide-semiconductor are enhanced metal-oxide-semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920365365.2U CN209514542U (en) | 2019-03-21 | 2019-03-21 | A kind of reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920365365.2U CN209514542U (en) | 2019-03-21 | 2019-03-21 | A kind of reset circuit |
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| Publication Number | Publication Date |
|---|---|
| CN209514542U true CN209514542U (en) | 2019-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201920365365.2U Expired - Fee Related CN209514542U (en) | 2019-03-21 | 2019-03-21 | A kind of reset circuit |
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| CN (1) | CN209514542U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117459044A (en) * | 2023-11-17 | 2024-01-26 | 无锡芯霖华科技有限公司 | Low-voltage reset circuit and reset method |
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2019
- 2019-03-21 CN CN201920365365.2U patent/CN209514542U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117459044A (en) * | 2023-11-17 | 2024-01-26 | 无锡芯霖华科技有限公司 | Low-voltage reset circuit and reset method |
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Granted publication date: 20191018 |