CN113098491A - Three-value logic circuit based on threshold type memristor - Google Patents
Three-value logic circuit based on threshold type memristor Download PDFInfo
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Abstract
The invention discloses a three-value logic circuit based on a threshold memristor, which comprises a first threshold memristor MT1Second threshold type memristor MT2And a third threshold type memristor MT3And a fourth threshold type memristor MT4And a fifth threshold type memristor MT5And a sixth threshold type memristor MT6A first PMOS transistor M1A second NMOS transistor M2A third PMOS transistor M3A fourth NMOS transistor M4The fifth PMOS transistor M5And a sixth NMOS transistor M6. The circuit mixes the threshold memristor and the CMOS to realize a three-value NAND and NOR logic function in the circuit, the circuit structure is simpler, the output logic is controllable, and a new thought is provided for the design of the memristor in a digital logic circuit.
Description
Technical Field
The invention relates to a three-value NAND/NOR logic circuit based on a threshold memristor, in particular to a mixed three-value NAND/NOR memristor logic function circuit formed based on a CMOS and the threshold memristor, and belongs to the technical field of circuit design.
Background
The concept of memristor was proposed in 1971, and is a two-terminal passive circuit element for characterizing the relationship between magnetic flux and electric charge, and the actual TiO was prepared in Hewlett packard laboratory in 20082A type memristor device. The memristor has the characteristics of small volume, nonvolatile property and the like, so that the memristor has wide attention in the fields of digital logic circuits, storage circuits, nonlinear circuits, neural networks, biological systems and the like, and the memristor is compatible with a CMOS (complementary metal oxide semiconductor) process and can be better fused with the traditional digital circuit. The application of the prior memristor in a digital circuit is mainly focused on binary logic, and the multi-valued logic can increase the information content of a single line, effectively reduce the number of devices, interconnection lines and circuit area when realizing the same function, and has wide prospect in the field of digital logic.
Therefore, the invention relates to a logic circuit design of a multivalue memristor, in particular to a digital logic circuit which has switchable NAND/NOR functions in the same circuit and is realized by utilizing the memristor and a CMOS tube.
Disclosure of Invention
Aiming at the problems in the prior art and research cost, the invention provides a three-value logic circuit based on a threshold memristor, the threshold memristor is combined with a CMOS to realize a three-value NAND or NOR memristor logic function, and the first selection terminal is used for selecting and outputting the three-value NAND or NOR function, so that a new idea is provided for the design of the threshold memristor in a digital logic circuit, particularly multivalued logic.
The technical scheme adopted by the invention for solving the technical problem is as follows: a three-value NAND/NOR logic circuit based on threshold type memristors comprises six threshold type memristors, three NMOS transistors and three PMOS transistors. Wherein the input end A is respectively connected with a first threshold memristor MT1Positive terminal, third threshold type memristor MT3A negative terminal of (a); the B input ends are respectively connected with a second threshold type memristor MT2Positive terminal, fourth threshold type memristor MT4A negative terminal of (a); first threshold type memristorMachine MT1Is connected with a second threshold type memristor MT2Negative terminal of, a first PMOS transistor M1Gate of (d), second NMOS transistor M2Grid of (2), the connection point is V1(ii) a Third threshold type memristor MT3The positive ends of the first and second memory resistors are respectively connected with a fourth threshold type memristor MT4Positive terminal of the third PMOS transistor M3Gate of (3), fourth NMOS transistor M4Grid of (2), the connection point is V2(ii) a Fifth threshold type memristor MT5Is connected with a power supply 1/2VDDFifth threshold type memristor MT5Are respectively connected with the first PMOS transistor M1Drain electrode of the first NMOS transistor M2Drain electrode of the fifth PMOS transistor M5A source electrode of (a); sixth threshold type memristor MT6Is connected with a power supply 1/2VDDSixth threshold type memristor MT6Are respectively connected with the third PMOS transistor M3Drain electrode of (1), fourth NMOS transistor M4Drain electrode of (1), sixth NMOS transistor M6A source electrode of (a); first PMOS transistor M1Is connected with a power supply VDD(ii) a Second NMOS transistor M2The source of (2) is grounded; third PMOS transistor M3Is connected with a power supply VDD(ii) a Fourth NMOS transistor M4The source of (2) is grounded; fifth PMOS transistor M5Is connected with a sixth NMOS transistor M6A gate, a first selection terminal K; fifth PMOS transistor M5Is connected to the sixth NMOS transistor M6A drain electrode of (1); output end VOUTIs a fifth PMOS transistor M5And the sixth NMOS transistor M6Is connected to the drain of the transistor.
Compared with the prior art, the invention designs the threshold-type memristor-based three-value logic circuit, and the NAND and NOR operation logic function is output in the same circuit by adjusting the first selection end. The circuit structure is simple, the output logic function is controllable, and a new idea is provided for the design of the memristor in the digital logic circuit.
Drawings
FIG. 1 is a current-voltage characteristic curve of a threshold-type memristor as required by the present invention.
Fig. 2 is a specific circuit configuration diagram of the present invention.
Detailed Description
The following describes an example of the present invention in detail with reference to the accompanying drawings.
FIG. 1 is a current-voltage characteristic curve of a threshold-type memristor required by the present invention. As can be seen from fig. 1, the threshold memristor has a relatively obvious high-low resistance switching characteristic, i.e., a switching-like characteristic. The invention designs the three-value logic circuit based on the threshold memristor by utilizing the characteristics.
Referring to fig. 2, a specific circuit structure diagram of the present invention is shown, wherein six threshold type memristors, three NMOS transistors, and three PMOS transistors are included. K is the first selection terminal, and the high and low levels are both effective. A. B is a three-valued signal input terminal, VDDIs the power supply terminal. MT1、MT2、MT3、MT4、MT5、MT6All threshold type memristor model, M1、M3、M5Are all PMOS transistors, M2、M4、M6Are all NMOS transistors. Different logic operation results completed by the same circuit are realized by controlling the high and low levels of the first selection terminal K.
In the three-valued logic circuit, a high level V is definedDDLogic "2", intermediate level 1/2VDDLogic "1" and logic "0" at low level; simultaneously, the absolute value of the conduction voltage of all the PMOS transistors is larger than the middle level, and the second NMOS transistor M is enabled2The conducting voltage is greater than the intermediate voltage, and the fourth NMOS transistor M4And a sixth NMOS transistor M6The turn-on voltage is less than the intermediate level and greater than the low level.
1. When the first selection terminal K is logic '0', the fifth PMOS transistor M5In a conducting state, the sixth NMOS transistor M6In the off state. Due to M6Cut-off, then regardless of the third threshold type memristor MT3And a fourth threshold type memristor MT4A third PMOS transistor M3A fourth NMOS transistor M4The output signal is not affected by the variation of the output signal VOUTDependent only on the fifth PMOS transistorPipe M5The source is connected to the circuit.
(1) When the input signal AB is 00, the first threshold type memristor MT1Second threshold type memristor MT2All have no current passing through, V1The terminal output logic is '0', so that the first PMOS transistor M1On, the second NMOS transistor M2Cutoff, therefore M1The value of the output voltage of the drain electrode is approximate to VDDDue to the fifth PMOS transistor M5Conducting, outputting signal VOUTIs logic "2";
(2) when the input signal AB is 11, the first threshold type memristor MT1And a second threshold type memristor MT2Negative terminal connected, first threshold type memristor MT1And a second threshold type memristor MT2Are equal in potential and no current, so that V is1The end output logic is '1', and the first PMOS transistor M1And a second NMOS transistor M2All-cutoff, fifth threshold type memristor MT5At power supply 1/2VDDIs changed into a low resistance state under the action of the magnetic field, and M is changed into a low resistance state5The source voltage is approximately 1/2VDDDue to the fifth PMOS transistor M5Conducting, outputting signal VOUTA logic '1' is judged;
(3) when the input signal AB is 22, the first threshold type memristor MT1And a second threshold type memristor MT2Is connected with the negative electrode of the first threshold value type memristor MT1And a second threshold type memristor MT2The two positive terminals are also at equal potential, no current passes through the device, so V1The terminal output logic is '2', so that the first PMOS transistor M1To, the second NMOS transistor M2On, the second NMOS transistor M2Is logic 0, since the fifth PMOS transistor M5Conducting, outputting signal VOUTIs logic "0";
(4) when the input signal AB is 02, the first threshold type memristor MT1Positive terminal and second threshold type memristor MT2Will produce a potential difference and current will flow from the B input terminal to the a input terminal, when the first threshold type memristor M is presentT1The resistance state is a low resistance state, and a second threshold value type memristor MT2The resistance state is a high resistance state, and V is obtained due to the serial voltage division of the two threshold memristors1The terminal output logic is '0', so that the first PMOS transistor M1On, the second NMOS transistor M2To that end, the first PMOS transistor M1Has a drain voltage output of approximately VDDDue to the fifth PMOS transistor M5Conducting, outputting signal VOUTIs logic "2";
(5) the working process of the input signal AB-20 is similar to that of AB-02;
(6) when the input signal AB is 01, the first threshold type memristor MT1Positive terminal and second threshold type memristor MT2Also generates a potential difference, the current flows from the B terminal to the A terminal, and the first threshold type memristor MT1The resistance state is a low resistance state, and a second threshold value type memristor MT2The resistance state is a high resistance state, and V is obtained due to the serial voltage division of the two threshold memristors1The terminal output logic is '0', so that the first PMOS transistor M1On, the second NMOS transistor M2To that end, the first PMOS transistor M1Has a drain voltage output of VDDDue to the fifth PMOS transistor M5Conducting, outputting signal VOUTIs logic "2";
(7) the working process of the input signal AB-10 is similar to AB-01;
(8) when the input signal AB is 21, the first threshold type memristor MT1Positive terminal and second threshold type memristor MT2Will generate a potential difference, a current flows from the A terminal to the B terminal, a first threshold type memristor MT1In the high-resistance state, the second threshold value type memristor MT2In a low-resistance state, V is divided by the serial voltage of two threshold memristors1The end output logic is '1', and the first PMOS transistor M1And a second NMOS transistor M2Are all turned off, so the first PMOS transistor M1The drain has no current, at this time, the fifth threshold type memristor MT5At power supply 1/2VDDA fifth PMOS transistor M in low resistance state5Is also conducted to output signal VOUTIs logic "1";
(9) the working process of the input signal AB-12 is similar to that of AB-21;
thus, the output V is only present when the input signals a and B are both logic 2OUTA logic "0" is output. When any one of the signals A, B is logic 0, the output terminal VOUTThe output logic is "2", and when AB is 12, 11 or 21, the output logic is "1". The circuit realizes the function of three-value NAND logic operation.
2. When the first selection terminal K is logic "2", the fifth PMOS transistor M5In the off state, the sixth NMOS transistor M6Is in a conducting state. Due to M5Cut-off, then regardless of the first threshold type memristor MT1Second threshold type memristor MT2A first PMOS transistor M1A second NMOS transistor M2The output signal is not affected by any change, and the output signal only depends on the sixth NMOS transistor M6The source is connected to the circuit.
(1) When the input signal AB is 00, the third threshold type memristor MT3And a fourth threshold type memristor MT4All have no current passing through, V2The end output logic is '0', and the third PMOS transistor M3On, the fourth NMOS transistor M4Off, third PMOS transistor M3The value of the output voltage of the drain electrode is approximate to VDDThe sixth NMOS transistor M6Conducting, outputting signal VOUTIs logic "2";
(2) when the input signal AB is 11, the third threshold type memristor MT3And a fourth threshold type memristor MT4Positive terminal connected, third threshold type memristor MT3And a fourth threshold type memristor MT4Has equal potential at the two negative terminals, and has no current, V2The end output logic is '1', and a third PMOS transistor M3And a fourth NMOS transistor M4All-cutoff sixth threshold type memristor MT6At power supply 1/2VDDIs changed into a low-resistance state under the action of the voltage, and the sixth NMOS transistor M is changed into a low-resistance state6The source voltage is approximately 1/2VDDDue to the sixth NMOS transistor M6Conducting, outputting signal VOUTIs logic "1";
(3) when in transfusionWhen the input signal AB is 22, the third threshold type memristor MT3And a fourth threshold type memristor MT4Positive pole connected, third threshold type memristor MT3And a fourth threshold type memristor MT4The two negative terminals are also equal in potential and have no current, so V2The end output logic is '2', and a third PMOS transistor M3Off, fourth NMOS transistor M4On, the fourth NMOS transistor M4The drain output voltage is logic '0', and the sixth NMOS transistor M6Conducting, outputting signal VOUTIs logic "0";
(4) when the input signal AB is 02, the third threshold type memristor MT3Negative terminal and fourth threshold type memristor MT4Generates a potential difference, a current flows from the B input end to the A input end, and a fourth threshold type memristor MT4The resistance state is a low resistance state, and a third threshold value type memristor MT3The resistance state is a high resistance state, and V is obtained due to the serial voltage division of the two threshold memristors2The end output logic is '2', and a third PMOS transistor M3Off, fourth NMOS transistor M4On, the fourth NMOS transistor M4The drain output voltage is logic '0', and the sixth NMOS transistor M6Is turned on, so that the signal V is outputOUTIs logic "0";
(5) the working process of the input signal AB-20 is similar to that of AB-02;
(6) when the input signal AB is 01, the third threshold type memristor MT3Negative terminal and fourth threshold type memristor MT4Generates a potential difference, a current flows from the B input end to the A input end, and a fourth threshold type memristor MT4The resistance state is a low resistance state, and a third threshold value type memristor MT3The resistance state is a high resistance state, and V is obtained due to the serial voltage division of the two threshold memristors2The end output logic is '1', and a third PMOS transistor M3And a fourth NMOS transistor M4All-cutoff sixth threshold type memristor MT6At power supply 1/2VDDIs changed into a low-resistance state under the action of the voltage, and the sixth NMOS transistor M is changed into a low-resistance state6The source voltage is approximately 1/2VDDDue to the sixth NMOS transistor M6Conducting, outputting signal VOUTIs logic "1";
(7) the working process of the input signal AB-10 is similar to AB-01;
(8) when the input signal AB is 21, the third threshold type memristor MT3Negative terminal and fourth threshold type memristor MT4Generates a potential difference, a current flows from the input end A to the input end B, and a fourth threshold type memristor MT4The resistance value is in a high resistance state, and a third threshold value type memristor MT3The resistance value is in a low resistance state, and V is obtained due to the serial voltage division of the two threshold memristors2The end output logic is '2', and a third PMOS transistor M3Off, the fourth NMOS transistor M4On, the fourth NMOS transistor M4Has a drain output voltage of 0, and a sixth NMOS transistor M6Conducting, outputting signal VOUTIs logic "0";
(9) the working process of the input signal AB-12 is similar to that of AB-21;
thus, the output terminal V is only when both input signals A and B are logic "0" sOUTThe output logic is "2", when any one of the signals A, B is logic "2", the output end VOUTThe output logic is '0', when AB is 10, 11, 01, the output end VOUTThe logic is "1". At this time, the logic operation function of the circuit conforms to the three-valued NOR definition.
The voltage drop between the source and the drain of the MOS tube is ignored in the above analysis.
In summary, as long as the high-low level of the first selection terminal K is controlled, different logic functions can be selected as the final output. When the first selection end K is logic '0', the circuit realizes the NAND function of three-value memristors; when the first selection end K is logic '2', the circuit realizes a three-value memristive 'NOR' function. By analysis, the circuit can also realize the three-value NAND or NOR logic function.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (1)
1. A three-value logic circuit based on a threshold memristor is characterized by at least comprising a first threshold memristor MT1Second threshold type memristor MT2And a third threshold type memristor MT3And a fourth threshold type memristor MT4And a fifth threshold type memristor MT5And a sixth threshold type memristor MT6A first PMOS transistor M1A second NMOS transistor M2A third PMOS transistor M3A fourth NMOS transistor M4The fifth PMOS transistor M5And a sixth NMOS transistor M6The three-value NAND and NOR logic functions of the circuit are realized through the on and off of each transistor and the resistance state characteristics of each threshold memristor;
wherein, the A input ends are respectively connected with a first threshold memristor MT1Positive terminal, third threshold type memristor MT3A negative terminal of (a); the B input ends are respectively connected with a second threshold type memristor MT2Positive terminal, fourth threshold type memristor MT4A negative terminal of (a); first threshold type memristor MT1Is respectively connected with a second threshold type memristor MT2Negative terminal of, a first PMOS transistor M1Gate of (d), second NMOS transistor M2A gate electrode of (1); third threshold type memristor MT3The positive ends of the first and second memory resistors are respectively connected with a fourth threshold type memristor MT4Positive terminal of the third PMOS transistor M3Gate of (3), fourth NMOS transistor M4A gate electrode of (1); fifth threshold type memristor MT5Is connected with a power supply 1/2VDDFifth threshold type memristor MT5Are respectively connected with the first PMOS transistor M1Drain electrode of the first NMOS transistor M2Drain electrode of the fifth PMOS transistor M5A source electrode of (a); sixth threshold type memristor MT6Is connected with a power supply 1/2VDDSixth threshold type memristor MT6Are respectively connected with the third PMOS transistor M3Drain electrode of (1), fourth NMOS transistor M4Drain electrode of (1), sixth NMOS transistor M6A source electrode of (a);
the first PMOS transistor M1Is connected with a power supply VDD(ii) a Second NMOS transistor M2The source of (2) is grounded; third PMOS transistor M3Is connected with a power supply VDD(ii) a Fourth NMOS transistor M4The source of (2) is grounded; fifth PMOS transistor M5Is connected with a sixth NMOS transistor M6A gate, a first selection terminal K; fifth PMOS transistor M5Is connected to the sixth NMOS transistor M6A drain electrode of (1);
the high and low levels of the first selection terminal K are all effective: when K is high level, the NOR logic function is realized; the NAND three-valued logic function is implemented when K is low.
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| CN115019854A (en) * | 2022-04-28 | 2022-09-06 | 深圳市金和思锐科技有限公司 | Memory and calculation integrated memory unit and memory and calculation array based on memristor |
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Application publication date: 20210709 |