CN105870076B - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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CN105870076B
CN105870076B CN201610058577.7A CN201610058577A CN105870076B CN 105870076 B CN105870076 B CN 105870076B CN 201610058577 A CN201610058577 A CN 201610058577A CN 105870076 B CN105870076 B CN 105870076B
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dielectric layer
semiconductor package
metal strip
hole
package according
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CN105870076A (zh
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陈纪翰
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明涉及半导体封装结构及其制造方法。所述半导体封装结构包括第一电介质层、裸片垫、有源组件、至少一个第一金属条、至少一个第二金属条及通孔。所述第一电介质层具有第一表面及与所述第一表面相对的第二表面。所述裸片垫定位在所述第一电介质层内。所述有源组件定位在所述第一电介质层内且安置在所述裸片垫上。所述第一金属条安置在所述第一电介质层的所述第一表面上，且电连接到所述有源组件。所述第二金属条安置在所述第一电介质层的所述第二表面上。所述通孔穿透所述第一电介质层且将所述至少一个第一金属条连接到所述至少一个第二金属条。

Description

半导体封装结构
技术领域
本发明涉及一种半导体封装结构和一种半导体制造工艺，且更确切地说，涉及一种半导体封装结构和其半导体工艺。
背景技术
半导体装置至少部分受对更小大小及增强的处理速度的需求驱使而已变得越来越复杂。同时，存在进一步小型化含有这些半导体装置的许多电子产品的需求。半导体装置通常被封装且随后可安装在包含电路的衬底(例如电路板)上。此导致空间被半导体装置封装及衬底两者占据，其中衬底上的表面积被半导体装置封装占据。另外，由于将封装、板制造及装配执行为单独的过程可引发成本。需要减少衬底上的半导体装置占据的空间，且简化及组合适用于半导体装置及衬底的封装、板制造及装配过程。
发明内容
根据本发明的实施例，一种半导体封装结构包括第一电介质层、裸片垫、有源组件、至少一个第一金属条、至少一个第二金属条及通孔。所述第一电介质层具有第一表面及与所述第一表面相对的第二表面。所述裸片垫定位在所述第一电介质层内。所述有源组件定位在所述第一电介质层内且安置在所述裸片垫上。所述第一金属条安置在所述第一电介质层的所述第一表面上，且电连接到所述有源组件。所述第二金属条安置在所述第一电介质层的所述第二表面上。所述通孔穿透所述第一电介质层且将所述至少一个第一金属条连接到所述至少一个第二金属条。
根据本发明的实施例，一种半导体封装结构包括第一电介质层、裸片及第一螺旋电感器。所述第一电介质层具有顶表面。所述裸片定位在所述第一电介质层内。所述第一螺旋电感器定位在所述第一电介质层内。所述第一螺旋电感器的至少一个端子电连接到所述裸片。所述第一螺旋电感器的中心轴大体上平行于所述第一电介质层的所述顶表面。
根据本发明的实施例，一种制造半导体封装结构的方法包括(a)提供裸片垫；(b)将有源组件放置在所述裸片垫上；(c)形成第一电介质层以囊封所述裸片垫及所述有源组件，所述第一电介质层具有第一表面及与所述第一表面相对的第二表面；(d)在所述第一电介质材料中形成多个通孔，所述多个通孔从所述第一电介质层的所述第一表面及所述第二表面暴露；(e)在所述第一电介质层的所述第一表面上形成第一组金属条以连接到所述多个通孔；及(f)在所述第一电介质层的所述第二表面上形成第二组金属条以连接到所述多个通孔。
附图说明
图1说明根据本发明的实施例的半导体封装结构；
图2说明根据本发明的实施例的半导体封装结构的横截面图；
图3说明根据本发明的实施例的半导体封装结构；
图4说明根据本发明的实施例的半导体封装结构；
图5A、图5B、图5C、图5D、图5E及图5F说明根据本发明的实施例的制造方法；及
图6A、图6B、图6C、图6D、图6E及图6F说明根据本发明的实施例的制造方法。
贯穿图式及详细描述使用共同参考数字以指示相同或类似元件。从以下结合附图作出的具体实施方式，本发明将会更显而易见。
具体实施方式
图1说明根据本发明的实施例的半导体封装结构1。半导体封装结构1包含绝缘层(例如，第一电介质层10)、裸片垫12、有源组件13(例如，裸片或集成电路(IC))、多个第一金属条14a、多个第二金属条14b、多个通孔15及多个第一金属触点16a(例如，导电垫)。
第一电介质层10可包含(但不限于)模制化合物或预浸复合纤维(例如，预浸体)。模制化合物的实例可包含(但不限于)具有分散在其中的填充剂的环氧树脂。预浸体的实例可包含(但不限于)通过堆叠或层压一定数目的预浸材料/薄片而形成的多层结构。
裸片垫12在第一电介质层10内。有源组件13在第一电介质层10内且放置在裸片垫12上。有源组件13可例如为电力IC或射频IC(RFIC)。
第一金属条14a放置在第一电介质层10的顶表面上。在一个实施例中，第一金属条14a布置在第一方向上，使得它们沿着裸片垫12的一侧大体上彼此平行。然而，此定向不具限制性。第一金属条14a的材料可包含(但不限于)铜(Cu)或另一金属或合金。
第二金属条14b放置在第一电介质层10的底表面上。在一个实施例中，第二金属条14b布置在第二方向上，使得它们沿着裸片垫12的一侧大体上彼此平行。然而，此定向不具限制性。第二金属条14b的材料可包含(但不限于)铜(Cu)或另一金属或合金。
在其中沿着裸片垫12的一侧的第一金属条14a在第一方向上大体上彼此平行地定向且沿着裸片垫12的相同侧的第二金属条14b在第二方向上大体上彼此平行地定向的实施例中，如针对图1的实施例所说明，所述第二方向不同于所述第一方向。在任何情况下，每一第二金属条14b相对于沿着裸片垫12的一侧的第一金属条14a中的对应一者或多者以一角度(或若干角度)布置。
通孔15穿透第一电介质层10。每一通孔15将第一金属条14a中的一者电连接到对应的第二金属条14b。在其中第一金属条14a在一个方向上定向(即，沿着裸片垫12的一侧相对于彼此并行)且第二金属条14b在另一方向上定向(即，沿着裸片垫12的相同侧相对于彼此并行)的实施例中，通孔15可连接第一金属条14a及第二金属条14b以沿着裸片垫12的所述侧形成三维(3D)螺线管结构。此3D螺线管结构在图1中通过实例被说明为3D螺旋电感器14。螺旋电感器14的至少一个端子电连接到有源组件13。螺旋电感器14的中心轴大体上平行于第一电介质层10的顶表面或底表面。在一个实施例中，螺旋电感器14沿着有源组件13的一个边缘布置，使得螺旋电感器14的中心轴大体上平行于有源组件13的边缘。然而，此定向不具限制性。
第一金属触点16a将有源组件13电连接到第一金属条14a、第二金属条14b、半导体封装结构内或上的其它组件、外部电路或包含电力供应器或接地接口的外部接口中的一或多者。
图2说明根据本发明的实施例的半导体封装结构2的横截面视图。图2的半导体封装结构2类似于图1的半导体封装结构1，不同之处在于图2的半导体封装结构2进一步包括第二电介质层11、多个第二金属触点18、第一保护层19a、第二保护层19b及无源元件21。
第一电介质层10具有第一表面(或顶表面)101及与第一表面101相对的第二表面(或底表面)102。裸片垫12嵌入或埋入第一电介质层10内。有源组件13放置在裸片垫12上且嵌入或埋入第一电介质层10内。第一金属触点16a在第一电介质层10的第一表面101上且通过通孔16v电连接到有源组件13。
多个导线17嵌入或埋入第一电介质层10内。导线17通过通孔17v连接到第一金属触点16a。导线17通过通孔17v'连接到安置在第一电介质层10的第二表面102上的金属触点17b。在一个实施例中，导线17及裸片垫12经组合以形成引线框结构。
裸片垫12通过通孔16v'与金属层16b连接，以便防止裸片垫12弯曲(例如翘曲)。
通孔15在第一金属条14a与第二金属条14b之间延伸。在一个实施例中，每一通孔15包括向下渐细上部部分15a及向上渐细底部部分15b。换句话说，上部部分15a及底部部分15b两者包含在相对方向上面对的漏斗形状部分，如图2中所说明。向下渐细上部部分15a的深度D1不同于向上渐细底部部分15b的深度D2。在一个实施例中，D1大于D2。在图2中所展示的实施例中，D2大于D1。在其它实施例中，D1可大体上等于D2。每一通孔15的上部部分15a埋入第一电介质层10中且电连接到第一金属条14a。每一通孔15的底部部分15b埋入第一电介质层10中且电连接到第二金属条14b。
第二电介质层11具有第一表面(或顶表面)111及与第一表面111相对的第二表面(或底表面)112。第二电介质层11安置在第一电介质层10上，且第二电介质层11的第二表面112附接到第一电介质层10的第一表面101。第二电介质层11覆盖第一金属触点16a及多个第一金属条14a。
第二电介质层11可包含(但不限于)模制化合物或预浸复合纤维(例如，预浸体)。模制化合物的实例可包含(但不限于)具有分散在其中的填充剂的环氧树脂。预浸体的实例可包含(但不限于)通过堆叠或层压一定数目的预浸材料/薄片而形成的多层结构。
多个第二金属触点18安置在第二电介质层11的第一表面111上，且可通过多个第二通孔18v电连接到第一金属触点16a。
第一保护层(例如，阻焊剂)19a安置在第二电介质层11的第一表面111上。第一保护层19a覆盖第二金属触点18及第二电介质层11的第一表面111。
第二保护层(例如，阻焊剂)19b安置在第一电介质层10的第二表面102上。第二保护层19b覆盖第二金属条14b、金属层16b的一部分，及金属触点17b中的一或多者或一或多者的部分。
在一个实施例中，无源元件21放置在第二电介质层11的第一表面111上，且电连接到第二金属触点18中的一或多者。无源元件21可例如为电容器或电阻器。
如图2中所展示，将电感器14嵌入第一电介质层10中可减小半导体封装结构2的厚度H。与其中电感器放置在电介质层的顶表面上的其它实施例相比，半导体结构2的厚度H可减小大约0.4mm到0.6mm。厚度H中的此减小可表示大约25％到40％的减小。因此，将电感器嵌入电介质层中可允许半导体封装结构2的大小的减小，其可降低制造成本。
此外，将电感器14嵌入第一电介质层10中可减小或大体上消除涡电流损耗。因此，嵌入电介质层中的电感器14与放置在电介质层的顶表面上的电感器相比可具有较高的Q因子。根据本发明而实施的嵌入式电感器的Q因子大约在50到60的范围内。
另外，如图1中所示，如果螺旋电感器14的中心轴大体上平行于有源组件13的边缘，那么由螺旋电感器14包围的芯内的磁场的方向也将大体上平行于有源组件13的边缘。换句话说，大多数磁场将被引导远离有源组件13；因此，有源组件13对电感器14的影响将减小，且电感器14将具有较高的Q因子。另外，有源组件13内的电路(例如，RF电路)可归因于电感器14的较高的Q因子而具有提高的性能，以及归因于磁场被引导远离有源组件13而具有提高的性能(即，有源组件13内的电磁干扰的减小)。
图3说明根据本发明的实施例的半导体封装结构3。图3的半导体封装结构3类似于图1的半导体封装结构1，不同之处在于在图1的半导体封装结构1中，围绕有源组件13的周边的四个螺旋电感器14被说明为互连，但在图3的半导体封装结构3中，多个螺旋电感器24a、24b、24c及24d不互连，且被说明为各自电连接到有源组件13。
螺旋电感器24a、24b、24c及24d彼此电绝缘。每一螺旋电感器可与邻近的电感器磁耦合以形成变压器。例如，螺旋电感器24a可与螺旋电感器24b及24d磁耦合以形成变压器。在一个实施例中，图3的有源组件13是RFIC。
图4说明根据本发明的实施例的半导体封装结构4。图4的半导体封装结构4类似于图1的半导体封装结构1，不同之处在于图4的半导体封装结构进一步包括磁性材料20。
磁性材料20埋入由螺旋电感器14形成或包围的中央空间(芯)内的第一电介质层10中。磁性材料20通过第一电介质层10与螺旋电感器14分离。磁性材料的使用可增加电感器14的磁化强度、磁导率及磁通量密度。因此，与不具有磁性材料的电感器相比，有源组件13具有来自电感器14的较少影响且电感器14将具有较高的Q因子。
图5A、5B、5C、5D、5E及5F说明根据本发明的实施例的制造方法。
参看图5A，提供包括裸片垫12及多个导线17的引线框。引线框优选由铜或其合金制成。在一些实施例中，引线框可由铁或铁合金、镍或镍合金或其它金属或金属合金中的一者或组合制成。在一些实施例中，引线框包覆有铜层。
参看图5B，有源组件13放置在裸片垫12上。有源组件13附接到裸片垫12的顶表面。至少一个接合线(未图示)从有源组件13接合到导线17。
参看图5C，第一电介质层10形成为掩埋或囊封裸片垫12、导线17及有源组件13。第一电介质层10具有第一表面101及与第一表面101相对的第二表面102。可通过例如将电介质粘合材料层压到引线框而形成第一电介质层10。
参看图5D，多个通孔16v、17v形成为电连接到有源组件13及导线17。在一个实施例中，通过以下步骤形成通孔16v、17v：(i)在第一电介质层10的第一表面101上钻出多个通孔；及(ii)使用导电材料及环氧树脂填充所述通孔。
另外，多个通孔16v'、17v'形成为连接到裸片垫12及导线17。形成通孔16v'、17v'的步骤类似于形成通孔16v、17v的步骤，不同之处在于通孔16v'、17v'的通孔形成于第一电介质层10的第二表面102上。
参看图5D，多个通孔15形成为穿透第一电介质层10。在一个实施例中，通孔15通过以下步骤而形成：(i)从第一电介质层10的第一表面101钻出多个向下渐细的第一开口而不穿透第一电介质层10到达第一电介质层10的底表面102；(ii)在第一开口中镀敷导电材料以形成通孔15的上部部分15a；(iii)从第一电介质层10的第二表面102形成多个向上渐细的第二开口以暴露通孔15的上部部分15a；(iv)在第二开口中镀敷导电材料以形成通孔15的底部部分15b，底部部分15b电连接到第一电介质层10中的上部部分15a以形成通孔15。在其它实施例中，所述向下渐细的第一开口及所述向上渐细的第二开口两者在镀敷导电材料之前形成，使得通孔15的上部部分15a及底部部分15b同时形成。
参看图5D，多个第一金属条14a形成于第一电介质层10的第一表面101上以电连接到从第一电介质层10的第一表面101暴露的通孔15的上部部分15a。多个第二金属条14b形成于第一电介质层10的第二表面102上以电连接到从第一电介质层10的第二表面102暴露的通孔15的底部部分15b。通孔15将第一金属条14a中的每一者电连接到对应的第二金属条14b以形成3D螺线管结构，例如3D螺旋电感器14。
在一个实施例中，3D螺线管结构沿着裸片垫12的一侧形成，且形成在3D螺线管结构中，第一金属条14a中的每一者布置在第一方向上以使得第一金属条14a大体上彼此平行，第二金属条14b中的每一者布置在第二方向上以使得第二金属条14b大体上彼此平行，且第二方向不同于第一方向。
多个第一金属触点16a形成于第一电介质层10的第一表面101上以电连接到通孔16v、17v。第二金属层16b及多个金属触点17b形成于第一电介质层10的第二表面102上以电连接到通孔16v'、17v'。
参看图5E，第二电介质层11形成于第一电介质层10的第一表面101上以囊封第一金属触点16a及多个第一金属条14a。例如，可使用模制技术(其借助于模套(未图示)使用模制化合物)形成第二电介质层11，以囊封第一金属触点16a及多个第一金属条14a。对于另一实例，可通过在第一电介质层10、第一金属触点16a及多个第一金属条14a上堆叠或层压一定数目的薄片(例如，由预浸复合纤维制成的薄片)以形成第二电介质层11，而形成第二电介质层11。
多个第二通孔18v形成于第二电介质层11内以电连接到第一金属触点16a中的一或多者。形成第二通孔18v的步骤类似于形成通孔16v的步骤。多个第二金属触点18形成于第二电介质层11的第一表面111上以电连接到所述第二通孔18v。
参看图5F，第一保护层(阻焊剂)19a可形成于第二电介质层11的第一表面111上。第一保护层19a覆盖第二金属触点18及第二电介质层11的第一表面111中的一或多者，且暴露第二金属触点18中的一或多者。无源元件21放置在第二电介质层11的第一表面111上，且电连接到一或多个暴露的第二金属触点18。
第二保护层19b形成于第一电介质层10的第二表面102上。第二保护层19b覆盖第二金属条14b、金属层16b的一部分及金属触点17b中的一或多者。
随后，执行分离过程以将半导体封装结构带划分为多个半导体封装结构。使用适当的激光或其它切割工具执行所述分离过程。
图6A、6B、6C、6D、6E及6F说明类似于参看图5A、图5B、图5C、图5D、图5E及图5F所说明及所描述的方法的根据本发明的实施例的制造方法，不同之处在于磁性材料20放置在裸片垫12及导线17之间的空间中，如图6B中所展示。
如图6D中所展示，通孔15经布置以使得它们不电连接到磁性材料。因此，磁性材料20埋入第一电介质层10中且定位在3D螺线管结构(例如螺旋电感器14)的中央空间(芯)内。磁性材料20可包括例如Co、Fe、CoFeB、NiFe或类似者。
如本文中所用，术语“大体上”、“基本上”、“大约”及“约”用于描述及考虑小的变化。在结合事件或情况而使用时，所述术语可涉及其中事件或情况精确发生的实例以及其中事件或情况紧密近似发生的实例。
在一些实施例中，如果两个表面之间的位移较小，例如不大于1pm、不大于5pm或不大于10pm，那么可认为这两个表面是共面的或大体上共面的。
在一些实施例中，如果两个组件定位的方向之间的角度较小，例如不大于10度、不大于5度或不大于1度，那么可认为所述两个组件是平行或大体上平行的。
另外，本文中有时以范围格式呈现量、比率及其它数值。应理解，此范围格式是出于便利及简洁而使用且应灵活地理解成包含明确指定为范围界限的数值，并且包含所述范围内涵盖的所有个别数值或子范围，如同每一数值及子范围被明确指定一般。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应理解，在不脱离如通过所附权利要求书界定的本发明的真实精神和范围的情况下，可作出各种改变且可取代等效物。所述说明可能不一定按比例绘制。归因于制造工艺及公差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可作出修改，以使特定情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有所述修改都既定在所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序及分组不是对本发明的限制。

Claims (14)

1.一种半导体封装结构(1)，其包括：
第一电介质层(10)，其具有第一表面及与所述第一表面相对的第二表面；
裸片垫(12)，其在所述第一电介质层(10)内；
有源组件(13)，其在所述第一电介质层(10)内且安置在所述裸片垫(12)上；
多个第一金属条(14a)，其安置在所述第一电介质层(10)的所述第一表面上，所述多个第一金属条(14a)互相平行，且所述多个第一金属条(14a)中的至少一者电连接到所述有源组件(13)；
多个第二金属条(14b)，其安置在所述第一电介质层(10)的所述第二表面上，所述多个第二金属条(14b)互相平行；及
多个通孔(15)，其穿透所述第一电介质层(10)且将所述多个第一金属条(14a)中的每一者连接到相应的第二金属条(14b)；
其中所述多个第一金属条，所述多个第二金属条以及所述多个通孔形成螺旋电感器。
2.根据权利要求1所述的半导体封装结构，其中所述多个第一金属条不平行于所述多个第二金属条。
3.根据权利要求1所述的半导体封装结构，其中：
所述多个第一金属条中的每一者布置在第一方向上；
所述多个第二金属条中的每一者布置在第二方向上；且
所述第一方向不同于所述第二方向。
4.根据权利要求1所述的半导体封装结构，其进一步包括所述第一电介质层内的多个导线。
5.根据权利要求4所述的半导体封装结构，其进一步包括：
第一组金属触点，其安置在所述第一电介质层的所述第一表面上且电连接到所述多个导线；
第一组通孔，其在所述第一电介质层内且将所述第一组金属触点电连接到所述有源组件。
6.根据权利要求1所述的半导体封装结构，其中：
每一通孔具有向下渐细上部部分及向上渐细底部部分，且其中所述向下渐细上部部分的深度不同于所述向上渐细底部部分的深度。
7.根据权利要求1所述的半导体封装结构，其进一步包括：
由所述多个通孔包围的芯，其中所述芯包括磁性材料。
8.一种半导体封装结构(1)，其包括：
第一电介质层(10)，其具有顶表面(101)及与所述顶表面(101)相对的底表面(102)；
裸片(13)，其在所述第一电介质层(10)内；及
第一螺旋电感器(14)，其在所述第一电介质层(10)内，所述第一螺旋电感器(14)的至少一个端子电连接到所述裸片(13)，其中所述第一螺旋电感器布置在所述裸片的周边处，
其中所述第一螺旋电感器(14)的中心轴平行于所述第一电介质层(10)的所述顶表面(101)。
9.根据权利要求8所述的半导体封装结构，其中：
所述第一螺旋电感器(14)具有多个通孔(15)，每一通孔(15)具有第一部分(15a)及第二部分(15b)，所述第一部分(15a)从所述第一电介质层(10)的所述顶表面(101)暴露，且所述第二部分(15b)从所述第一电介质层(10)的所述底表面(102)暴露。
10.根据权利要求9所述的半导体封装结构，其进一步包括：
第二电介质层，所述第二电介质层安置在所述第一电介质层的所述顶表面上且覆盖第一组金属触点及所述第一螺旋电感器的所述第一部分，所述第一组金属触点形成在所述第一电介质层的所述顶表面上。
11.根据权利要求10所述的半导体封装结构，其进一步包括：
第二组金属触点，其安置在所述第二电介质层的顶表面上；及
第二组通孔，其在所述第二电介质层内且将所述第二组金属触点电连接到所述第一组金属触点中的一或多者。
12.根据权利要求8所述的半导体封装结构，其进一步包括电连接到所述裸片的第二螺旋电感器。
13.根据权利要求8所述的半导体封装结构，其进一步包括：
金属层，其安置在所述第一电介质层的所述底表面上；以及
第三组通孔，其将所述金属层与所述裸片垫连接。
14.根据权利要求8所述的半导体封装结构，其进一步包括由所述第一螺旋电感器包围的芯，其中所述芯包括磁性材料。
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