CN105849902B - 制造电子封装件的方法 - Google Patents

制造电子封装件的方法 Download PDF

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Publication number
CN105849902B
CN105849902B CN201480025074.9A CN201480025074A CN105849902B CN 105849902 B CN105849902 B CN 105849902B CN 201480025074 A CN201480025074 A CN 201480025074A CN 105849902 B CN105849902 B CN 105849902B
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microdevice
aimed wafer
source chip
attached
wafer
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CN105849902A (zh
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P·常
M·梅伯里
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Intel Corp
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Intel Corp
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Abstract

一些示例性形式涉及制造电子封装件的方法。该方法包括将包括微型器件的源晶片附连至目标晶片。该方法还包括从目标晶片去除一部分源晶片以形成电子封装件。当从目标晶片去除源晶片时，微型器件保留在目标晶片上。该方法还包括在电子封装件上执行后处理，所述电子封装件是在从目标晶片去除源晶片后形成的。在方法的一些形式中，当从目标晶片去除源晶片时，一些微型器件保留在源晶片上。

Description

制造电子封装件的方法
技术领域
本文描述的实施例总体涉及制造电子封装件的方法，更具体地涉及通过将源晶片附连至目标晶片来制造电子封装件的方法。
背景技术
一般存在与将微型器件集成到电子封装件中相关的各种困难。这些困难包括管芯分离、处理(handle)和接合以及在包括微型器件的电子组件中形成互连。
传统拾取和布置方法一般能够处理XY尺寸小至大约250微米和厚度(即Z高度)50微米的器件。然而，这种相对大的厚度是难以在包括微型器件的电子组装件中形成互连的原因之一。
存在两种常见的传递方法，用于集成XY定向上10微米和Z方向上5微米那样小的微型切块(dice)。一种方法利用复杂的MEMS印刷头技术，而另一方法限于使用弹黏性压印的室温接合。
附图简述
图1A示出一示例性源晶片。
图1B示出另一示例性源晶片。
图2A示出一示例性目标晶片。
图2B示出另一示例性目标晶片。
图2C示出又一示例性目标晶片。
图3示出通过将图1A的源晶片附连至图2A的目标晶片而形成的示例性封装件。
图4示出图3的示例性封装件，其中将源晶片的一部分去除。
图5示出通过将图1A的源晶片附连至图2B的目标晶片而形成的示例性封装件。
图6示出图5的示例性封装件，其中将源晶片的一部分去除。
图7示出通过将图1A的源晶片附连至图2C的目标晶片而形成的示例性封装件。
图8示出图7的示例性封装件，其中将源晶片的一部分去除。
图9示出图4的电子封装件，其中电子封装件已经历示例性后源晶片去除处理(post source wafer removal processing)。
图10是制造电子封装件的方法的流程图。
图11是包含本文描述的至少一种方法的电子装置的方框图。
具体实施方式
下面的描述和附图充分地示出特定实施例以使本领域内技术人员实现它们。其它实施例可包括结构、逻辑、电、过程和其它的变化。一些实施例的部分和特征可包括在或取代其它实施例的部分和特征。权利要求书中阐述的实施例涵盖这些权利要求的所有可用等效物。
本申请中使用的方向术语“水平”是相对于与晶片或衬底的传统平面或表面平行的平面定义的，不管晶片或衬底的定向如何。术语“垂直”指与如前定义的水平垂直的方向。诸如“上”、“侧”(例如“侧壁”)、“较高”、“较低”、“之上”和“之下”的介词是相对于在晶片或衬底的顶表面上的传统平面或表面定义的，而不管晶片或衬底的定向如何。
本文描述的示例性方法能够通过微型器件之间的直接接合而集成微型器件(即在XY定向上小于10微米并在Z高度上小于5微米的微型器件)，而无需类似于切割、拾取和拾取头或压印之类的中间步骤。该方法也能够通过多种传统材料、工艺和工具将微型器件嵌入到另一管芯或衬底上。
可通过底切预制微型器件的衬底来制造源晶片，在微型器件之间具有锚定结构。在一些形式下，介电基座或机械止动件可形成在预制的目标晶片上
作为本文描述的方法的一部分，源晶片可倒转(flipped upside-down)并通过对介电基座的接合或受机械止动件控制的焊料接合而接合至目标晶片。一旦源晶片被接合至目标晶片，可从目标晶片拉开源晶片以使微型器件从源晶片上的锚定结构脱开。由于微型器件非常薄，因此可通过晶片级处理而形成互连或硅通孔以完成源晶片和微型器件的集成，从而形成电子封装件。
图1A和图1B示出两种不同示例类型的源晶片10A、10B。图1A中的源晶片10A包括连结在锚定件12之间的微型器件11，其中导电盘13位于微型器件11的顶部侧。图1B中的源晶片10B包括连结在锚定件12之间的微型器件11，其中导电盘14位于微型器件11的底部侧。这两种不同类型的源晶片10A、10B可直接地接合至目标晶片，如下文所述。源晶片10A、10B可使用目前已知或未来发现的任何技术来制造。
图2A、2B和2C示出目标晶片的三种不同示例性配置。图2A示出目标晶片20A，其包括在目标晶片20A的上表面上的介电基座21。
图2B示出包括介电基座23的目标晶片20B。目标晶片20B还包括介电基座23上的导电盘24和焊料凸起25。
图2C示出目标晶片20C，其包括目标晶片20C的表面上的导电盘26。目标晶片20C还包括导电盘26上的焊料凸起28和目标晶片20C的表面上的止动件(stop)29。
图10是制造电子封装件(例如参见图4、图6、图8中的电子封装件40、60、80)的方法[1000]的流程图。方法[1000]包括[1010]将包括微型器件11的源晶片10A或10B附连至目标晶片20A或20B或20C。应当注意，尽管所示附图将图1的源晶片10A图示为用于形成电子封装件40、60、80，然而源晶片10B可替代地用于形成电子封装件40、60、80(以及目前已知或未来发现的其它类型的源晶片)。
作为示例，包括微型器件11的源晶片10A或10B可在室温下使用粘合剂接合至目标晶片20A或20B或20C。源晶片10A或10B可接合至目标晶片20A或20B或20C的方式可部分地取决于源晶片10A或10B和目标晶片20A或20B或20C的配置以及电子封装件40、60、80的所需功能和/或配置。
方法[1000]还包括[1020]从目标晶片去除一部分源晶片10A或10B以形成电子封装件(例如参见图4、图6、图8，其中一部分源晶片10A被去除)。当从目标晶片20A或20B或20C去除源晶片10A或10B时，微型器件11保留在目标晶片20A或20B或20C上。
图3示出通过将图1A的源晶片10A附连至图2A的目标晶片20A而形成的示例性封装件40。图4示出图3的示例性封装件40，其中源晶片10A的一部分被去除。
图5示出通过将图1A的源晶片10A附连至图2B的目标晶片20B而形成的示例性封装件60。图6示出图5的示例性封装件60，其中源晶片10A的一部分被去除。
图7示出通过将图1A的源晶片10A附连至图2C的目标晶片20C而形成的示例性封装件80。图8示出图7的示例性封装件80，其中源晶片20C的一部分被去除。
如图3所示，在方法[1000]的某些形式下，[1010]将包括微型器件11的源晶片10A附连至目标晶片20A可包括：(i)将微型器件11附连至从目标晶片20A的表面伸出的相应介电基座21。
如图5所示，在方法[1000]的某些形式下，[1010]将包括微型器件11的源晶片10A附连至目标晶片20B可包括：将微型器件11附连至从目标晶片20B的表面伸出的焊料凸起25。另外，焊料凸起25可附连至目标晶片20B的表面上的导电盘24。
如图7所示，在方法[1000]的某些形式下，[1010]将包括微型器件11的源晶片10A附连至目标晶片20C可包括：将微型器件11上的导电盘13与目标晶片20C上的导电盘26附连。另外，[1010]将包括微型器件11的源晶片10A附连至目标晶片20C可包括将微型器件11附连至从目标晶片20C的表面伸出的焊料凸起28并使微型器件11与从目标晶片20C的表面伸出的止动件29配合(例如附着)。
作为示例，焊料凸起28可具有大约5微米的厚度和5微米的高度，其中止动件29提供间隙高度控制，尤其是当使用传统热压接合工具时。另外，当使用InAu或AuSn焊料时，焊料凸起28高度可进一步减小。
方法[1000]可进一步包括：[1130]对在从目标晶片20A或20B或20C去除源晶片10A或10B之后形成的电子封装件40、60、80执行后处理(post processing)。图9示出图4的电子封装件40，其中电子封装件40已经历示例性后源晶片10A去除处理(post source wafer10A removal processing)。被执行以进一步制造电子封装件40、60、80的后源晶片10A去除处理的类型将部分取决于电子封装件40、60、80的所需最终配置和功能(以及其它因素，包括但不限于成本、产出、可制造性和材料)。
在方法[1000]的某些形式下，当从目标晶片20A或20B或20C去除源晶片10A或10B时，一些微型器件11保留在源晶片10A或10B上。如图4、图6和图8所示，三个微型器件11中只有两个保留在目标晶片20A、20B、20C上。保留在源晶片10A或10B上的微型器件11的数目将取决于源晶片10A、10B和目标晶片20A、20B、20C的相对对准性和尺寸。设想，可随后将源晶片10A或10B的去除部分上的微型器件11施加到另一目标晶片或另一目标晶片区。
在方法[1000]的其它形式下，目标晶片20A、20B、20C可包括作为目标晶片20A、20B、20C的一部分的连接部(例如参见图4中的介电基座21和管芯22)，由此将包括微型器件11的源晶片10A、10B附连至目标晶片20A、20B、20C可包括将每个连接部附连至源晶片10A、10B。
然而，在一些形式下，不是所有的连接部都可附连至源晶片10A、10B。作为示例，源晶片10A或10B可小于目标晶片20A或20B或20C，以使目标晶片20A或20B或20C上的一些连接部不接纳微型器件11，或者可能需要多个源晶片以便利目标晶片上的所有连接部。
本文描述的方法可减少或省去当利用微型器件时所需的切割和处理，尤其是相比与微型器件关联的传统拾取和布置技术而言。另外，通过相关管芯上互连的更紧密集成，可使微型器件尺寸小很多。这种减小的管芯尺寸和互连的紧密集成可降低功耗，因为具有很少或没有IO驱动器以及减少的寄生效应。
本文描述的方法也可减少制造压印或研发新工具的需要，尤其相比已有的微转印技术。电子组件和方法可以是简单的并适用于许多SoC、光子IC、传感器、IoT和可佩戴产品。一些示例包括但不限于SoC上的GaN晶体管、高级逻辑IC上的小尺寸闪存、传感器上的IA核心或光子IC上的激光器。
图11是包含本文描述的至少一种方法[1000]的电子装置1100的方框图。电子装置1100仅仅是其中可使用本文描述的方法[1000]的一些形式的电子装置的一个例子。电子装置1100的例子包括但不限于个人计算机、平板计算机、移动电话、游戏设备、MP3或其它数字音乐播放器等。在该例中，电子装置1100包括数据处理系统，该数据处理系统包括系统总线1102以耦合电子装置1100的各种器件。系统总线102提供电子装置1200的各个器件之间的通信链路并可被实现为单个总线、总线组合或以任何其它适宜方式实现。
本文描述的电子组件1110可耦合至系统总线1102。电子组件1110可包括任何电路或电路组合。在一个实施例中，电子组件1110包括可以是任何形式的处理器1112。如本文所述，“处理器”表示任何类型的计算电路，例如但不限于微处理器、微控制器、复杂指令集计算(CISC)微处理器、精简指令集计算(RISC)微处理器、超长指令字(VLIW)微处理器、图形处理器、数字信号处理器(DSP)、多核处理器或任何其它类型的处理器或处理电路。
可包括在电子组件1110中的其它类型电路是常用电路、专用集成电路(ASIC)等等，例如用于诸如移动电话、平板计算机、膝上计算机、双向无线电的无线设备和类似电子系统中的一个或多个电路(例如通信电路1114)。IC能够执行任何其它类型的功能。
电子装置1100也可包括外部存储器1120，该外部存储器120可包括适于特殊应用的一个或多个存储器元件，例如以随机存取存储器(RAM)形式出现的主存储器1122、一个或多个硬盘驱动器1124和/或处理诸如紧凑盘(CD)、闪存卡、数字视频盘(DVD)之类可移动介质1126的一个或多个驱动器。
电子装置1100也可包括显示设备1116、一个或多个扬声器1118以及键盘和/或控制器1130，它可包括鼠标、跟踪球、触摸屏、语音识别装置或允许系统用户将信息输入到电子装置1100和从电子装置1100接收信息的任何其它装置。
在某些形式下，电子装置1100可包括在计算系统中本文所述的任何微型器件，其中计算系统附加到如本文描述的任何目标晶片的至少一部分。在一些形式下，本文描述的任何源晶片的至少一部分也可附连于微型器件。其它形式也可以是计算系统中如本文描述的任何微型器件，其中微型器件附加到本文描述的任何目标晶片的至少一部分。
为了更好地阐述本文所述的方法，下面给出诸实施例的非限制性列表：
例1包括方法，该方法包括将包括微型器件的源晶片附连至目标晶片并从目标晶片去除一部分源晶片以形成电子封装件。当从目标晶片去除源晶片时，微型器件保留在目标晶片上。
例2包括例1的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件附连至从目标晶片的表面伸出的相应介电基座。
例3包括例1-2中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件附连至从目标晶片的表面伸出的焊料凸起。
例4包括例1-3中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件与从目标晶片的表面伸出的止动件配合。
例5包括例4的方法，其中将微型器件与从目标晶片的表面伸出的止动件配合包括使微型器件附着于止动件。
例6包括例1-5中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件附连至从目标晶片的表面伸出的焊料凸起以及将微型器件与从目标晶片的表面伸出的止动件配合。
例7包括例1-6中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件附连至在目标晶片的表面上的相应管芯。
例8包括例1-7中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件上的导电盘与目标晶片进行附连。
例9包括例1-8中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将源晶片附连至目标晶片上的导电盘。
例10包括例1-9中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件上的导电盘与源晶片上的导电盘进行附连。
例11包括例1-10中任何一个的方法，其中将包括微型器件的源晶片附连至目标晶片包括将微型器件上的导电盘与安装在目标晶片上的导电盘上的焊料凸起进行附连。
例12包括例1-11中任何一个的方法，并进一步包括在电子封装件上执行后处理，所述电子封装件是在从目标晶片去除源晶片后形成的。
例13包括例1-12中任何一个的方法，其中当从目标晶片去除源晶片时，微型器件中的一些保留在源晶片上。
例14包括例13的方法，其中目标晶片包括作为目标晶片的一部分的连接部，其中将包括微型器件的源晶片附连至目标晶片包括将每个连接部附连至目标晶片。
例15包括一种方法，所述方法包括将包含微型器件的源晶片附连至目标晶片。微型器件包括导电盘并且目标晶片包括在目标晶片表面上的介电基座。该方法还包括从目标晶片去除一部分源晶片以形成电子封装件。当从目标晶片去除源晶片时，微型器件上的导电盘与目标晶片上的管芯配合。
例16包括例15的方法，其中目标晶片包括介电基座，由此当从目标晶片去除源晶片时，一些微型器件上的导电盘与目标晶片上的介电基座配合。
例17包括例15-16中任何一个的方法，其中当从目标晶片去除源晶片时，微型器件中的一些保留在源晶片上。
例18包括一种方法，所述方法包括将包含微型器件的源晶片附连至目标晶片表面上的导电盘。附连源晶片可包括：使微型器件与从目标晶片表面伸出的止动件配合，以及将微型器件附连至从目标晶片上的导电盘伸出的焊料凸起。该方法还包括从源晶片去除一部分源晶片以形成电子封装件。当从目标晶片去除源晶片时，微型器件被附连至焊料凸起。
例19包括例18的方法，其中附连源晶片包括将微型器件上的导电盘与目标晶片上的焊料凸起进行附连。
例20包括例18-19中任何一个的方法，其中当从目标晶片去除源晶片时，微型器件中的一些保留在源晶片上。
例21包括在计算系统中的微型器件，其中计算系统被附加到任何目标晶片的至少一部分。
例22包括在例18的计算系统中的微型器件，其中源晶片的至少一部分也可被附加到微型器件。
例23包括在计算系统中的微型器件，其中微型器件被附加到目标晶片的至少一部分。
本方法和计算系统的这些和其它例子和特征部分地在详细予以阐述。
这种总述旨在提供当前主题事项的非限定例子。其不旨在提供排他性或穷尽性解释。详细说明被包括以提供关于本文描述的方法的进一步信息。
上面的详细描述包括对附图的引用，附图构成详细描述的一部分。附图借助示例示出本发明可实践到的具体实施例。这些实施例在这里也被称为“例子”。这些例子可包括除了图示或描述的那些以外的要素。然而，本发明人也考虑其中仅提供所示或所描述的那些要素的例子。此外，本发明人也考虑使用图示或描述的那些要素的任意组合或置换的例子(或者其一个或多个方面)，或者针对特定例子(或者其一个或多个方面)，或者针对图示或本文所述的其它例子(或者其一个或多个方面)。
在该文件中，如同在专利文件中常用的那样，使用术语“一”或“一个”以包括一个或一个以上，这与“至少一个”或“一个或多个”的任何其它实例或用法无关。在该文件中，术语“或”用来指非排他的“或”，以使“A或B”包括“A但非B”、“B但非A”以及“A和B”，除非另有指示。在该文件中，术语“包括”和“在其中”被用作相应术语“包含”和“其中”的平文英语等同物。另外，在后面的权利要求书中，术语“包括”和“包含”是开放式的，也就是说，权利要求书中在这种术语之后的包括除了后面列出的要素以外的要素的系统、设备、物品、组合物、配方或工艺仍然被认为落在权利要求书的范围内。此外，在后面的权利要求书中，术语“第一”、“第二”和“第三”等仅用作标记，而不旨在对它们的对象强加数值要求。
以上描述是说明旨在是解说性的而非限制性的。例如，前面描述的例子(或者其一个或多个方面)可彼此结合地使用。例如本领域内技术人员在阅读前面的说明书之后可使用其它实施例。
遵照37C.F.R.§1.72(b)提供摘要，以使读者快速地确定本技术公开的性质。该摘要是以不用于解释或限制权利要求的范围或含义的理解而提交的。
另外，在前面的详细描述中，可将各种特征组合到一起以使本公开变得流畅。这不应当解释为旨在使未要求的公开特征对任何权利要求是必需的。相反，创造性主题事项可通过比具体公开的实施例的所有特征更少的特征来实现。因此，下面的权利要求书在此纳入到详细说明中，每个权利要求作为单独实施例而自成一体，并且期望这些实施例能够以各种组合或置换彼此结合。本发明的范围应参考所附权利要求书以及这些权利要求享有权利的等效方案的完整范围来确定。

Claims (19)

1.一种用于制造电子封装件的方法，包括：
将包括微型器件的源晶片附连至目标晶片；
从所述目标晶片去除所述源晶片的一部分以形成电子封装件，其中当从目标晶片去除所述源晶片时，所述微型器件保留在所述目标晶片上；以及
将包括微型器件的源晶片附连至目标晶片包括将所述微型器件与从所述目标晶片的表面伸出的止动件配合。
2.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件附连至从所述目标晶片的表面伸出的相应介电基座。
3.如权利要求1-2中的任一项所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件附连至从所述目标晶片的表面伸出的焊料凸起。
4.如权利要求1所述的方法，其特征在于，将微型器件与从所述目标晶片的表面伸出的止动件配合包括使微型器件附着于所述止动件。
5.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件附连至从所述目标晶片的表面伸出的焊料凸起以及将微型器件与从所述目标晶片的表面伸出的止动件配合。
6.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件附连至目标晶片的表面上的相应管芯。
7.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件上的导电盘与所述目标晶片附连。
8.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述源晶片附连至所述目标晶片上的导电盘。
9.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件上的导电盘与所述源晶片上的导电盘进行附连。
10.如权利要求1所述的方法，其特征在于，将包括微型器件的源晶片附连至目标晶片包括将所述微型器件上的导电盘与被安装在所述目标晶片上的导电盘上的焊料凸起进行附连。
11.如权利要求1所述的方法，其特征在于，还包括在电子封装件上执行后处理，所述电子封装件是在从所述目标晶片去除源晶片后形成的。
12.如权利要求1所述的方法，其特征在于，当从目标晶片去除源晶片时，所述微型器件中的一些保留在所述源晶片上。
13.如权利要求12所述的方法，其特征在于，所述目标晶片包括作为目标晶片的部分的连接部，其中将包括微型器件的所述源晶片附连至所述目标晶片包括将每个连接部附连至所述目标晶片。
14.一种用于制造电子封装件的方法，包括：
将包括微型器件的源晶片附连至目标晶片，其中所述微型器件包括导电盘并且所述目标晶片包括所述目标晶片的表面上的介电基座；以及
从所述目标晶片去除所述源晶片的一部分以形成电子封装件，其中当从目标晶片去除源晶片时，微型器件上的所述导电盘与所述目标晶片上的管芯配合。
15.如权利要求14所述的方法，其特征在于，所述目标晶片包括介电基座，由此当从所述目标晶片去除源晶片时，一些微型器件上的导电盘与目标晶片上的所述介电基座配合。
16.如权利要求14-15中的任一项所述的方法，其特征在于，当从目标晶片去除所述源晶片时，所述微型器件中的一些保留在所述源晶片上。
17.一种用于制造电子封装件的方法，包括：
将包括微型器件的源晶片附连至目标晶片的表面上的导电盘，其中附连所述源晶片包括使所述微型器件与从所述目标晶片的表面伸出的止动件配合以及将所述微型器件附连至从所述目标晶片上的所述导电盘伸出的焊料凸起；以及
从所述源晶片去除所述源晶片的一部分以形成电子封装件，其中当从所述目标晶片去除所述源晶片时，所述微型器件附连至所述焊料凸起。
18.如权利要求17所述的方法，其特征在于，附连所述源晶片包括将所述微型器件上的导电盘与所述目标晶片上的所述焊料凸起进行附连。
19.如权利要求17-18中的任一项所述的方法，其特征在于，当从目标晶片去除所述源晶片时，所述微型器件中的一些保留在源晶片上。
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