CN105848370A - Household light intelligent control system - Google Patents

Abstract

The invention relates to a household light intelligent control system comprising multiple decorative lighting controllers and a master controller. The AC power supply of each decorative lighting controller is connected in parallel on an original socket or load controlled by a switch so that decorative lighting control is realized. The master controller and each decorative lighting controller are provided with a cyclic wave discrimination circuit which is used for generating synchronization time of the system and maintaining consistency of system action. The master controller is also provided with an infrared receiving circuit. The decorative lighting operation mode is controlled and changed by a remote control emitter.

Description

Household intelligent lamplight control system body

(1) technical field:

The present invention relates to a kind of household intelligent lamplight control system body, comprise multiple lamp controller and One main controller, the alternating current power supply of each lamp controller is all connected to former socket or replaces former switch The load controlled, it is achieved lamp decoration controls.Main controller and each lamp controller are respectively mounted cycle Discriminator circuit, keeps system acting consistent for producing the lock in time of system, and main controller is also pacified Equipped with infrared receiving circuit, by remote control transmitter control break lamp decoration operational mode.

(2) background technology:

Thered is provided the control system of power supply by power network, its each electronic equipment or intermodule all pass through Special circuit communicates, and corrects the timing time of each electronic equipment or electronic module, reaches to synchronize Run purpose.Owing to using special circuit communication make wiring complicate and increase cost, if meter Time the time do not corrected by line traffic, then due to tradition timing error, run after a few hours, Its accumulation timing error can make system control action inconsistent, is likely to result in system crash, one A little often design for change, its products application of occasion that wiring installation amount is big is restricted.

(3) summary of the invention:

A kind of household intelligent lamplight control system body, comprises multiple lamp controller and a main controller. On household housing unit room main switchboard, miniature circuit breaker comprises multichannel independent air switch, and it is Guide tracked installation and presser type wiring reconfiguration are convenient, and each air switch controls a road electrical equipment and bears Carrying, such as socket, illumination are a road electric appliance load etc., select an air switch as required, One electrical switch, this electrical switch parallel diode are installed after air switch.And leading Control device and each lamp controller are respectively mounted cycle discriminator circuit, for producing the synchronization of system Time keeps system acting consistent, and in its telecommunication circuit, one communications electronics of each installation is opened simultaneously Close and switch drive module.Each lamp controller arranges unique number, and each lamp decoration controls Device is leaving a period of time after system is the most just started shooting, and sequentially shows the LED of varying number, The quantity that its LED is lighted is corresponding with the number of numbering, and certain lights quantity to select display During LED, shutdown obtains corresponding numbering and preserves, and sticking mark can be by showing school again Right, it is that single-chip microcomputer relies on its power supply in the numbering period when can't detect grid cyclic wave signal Numbering data are stored in nonvolatile storage by the energy storage of electric capacity.During communication, main controller closes power-off Son switch also connects its communications electronics switch, and through isolating diode, civil power is sent into system, system Half wave communication and the half-wave that use electric lines of force are powered, and each lamp controller can't detect power network When being isolated the half-wave voltage signal that diode blocks, i.e. close LED power on communications electronics and open Close；Otherwise, when switching to before all-wave from half-wave, main controller first sends to each lamp controller and cuts Change instruction, turn off communications electronics switch.The alternating current power supply of each lamp controller is all connected to former inserting Seat or the load of replacement on-off control, take the load on former socket or switch short switch away, Realize lamp decoration control, so change design convenient, wall paper line need not be broken.Each lamp controller is equal Control one group of LED, under control lock in time, form the lamp decoration of the most independent cooperation again Effect.Whole house signal light control divides illumination, indoor color normal complexion outdoor or roof colour lamp decoration, All using LED, wherein room lighting part uses white led lamps, colored lamp decoration to carry Illuminate for entourage, constitute various slow change illusion illuminator；Roof colour lamp decoration provides strong and becomes The light decorative effect changed, owner can control its opening and closing and lamp decoration model selection by remote controller.

The switch drive module of communications electronics switch is to divide two after resistance blood pressure lowering from electric power netting twine Road, a road is used for each lamp controller, and it is connected to the list of each lamp controller through reversal connection diode Sheet machine I/O mouth, when half-wave is born in clock timer timing to cycle, scans this I/O mouth, as Fruit does not has signal i.e. system to be in half-wave communications status.Another road is used for each lamp controller and master Control device, communication therebetween is that this road is through electric resistance partial pressure by controlling lock in time to keep keeping strokes It is followed by the CLK end of d type flip flop, the external interrupt mouth (INT0 of the Q termination single-chip microcomputer of d type flip flop Or INT1), this external interrupt mouth is set to level triggers.The D end ground connection of d type flip flop, its S End connects with the I/O mouth of single-chip microcomputer, and original state S end puts 1.Positive square-wave signal when CLK end During arrival, its rising edge makes d type flip flop set to 0, and external interrupt mouth low level produces interrupts, First making S end set to 0 in interrupt service routine, to make d type flip flop put 1 i.e. Q end be 1 to close interruption, Then communicating, communications electronics switch is connected to single-chip microcomputer corresponding port according to used communication mode, And carry out signal condition, before sign off, S end puts 1 communication making out next cycle of interrupt latency, So go round and begin again and realize half wave communication.

Main controller is provided with infrared receiving circuit, and it is generally integrated in an element by producer, Being integrally forming infrared receiving terminal, when needing to change lamp decoration operational mode, infrared remote-controlled transmitting Device sends operational mode command signal, and main controller mid-infrared receiving device receives infra-red remote control and sends out During the infrared command signal of emitter, infrared signal is become the signal of telecommunication and delivers to preposition amplification by it Circuit is amplified, then after demodulated device, signal detection circuit is detected by command signal, Implementation pattern changes and various operation.Main controller selects when running the glimmer of lamp decoration or suspending Carrying out half-wave traffic operation, call duration time is the shortest, does not affect light decorative effect.

The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three and screens some realization to cycle The identification decision of signal, recycling the cycle time set up lock in time, it is achieved main controller in system Synchronous operation with each lamp controller.

The cycle discriminator circuit structural representation of main controller and each lamp controller as in figure 2 it is shown, It is made up of two voltage comparators using hysteresis loop comparator, each voltage comparator all comprises Filter circuit, the reference voltage of its voltage comparator is provided by mu balanced circuit.System arranges clock Timer and synchrotimer.If be detected that adjacent two cycle signals are very, then take Go out the clock timer timing time between these two adjacent cycle signal zero passages, be sequentially stored in In cycle time memory cell, this cycle time memory cell can deposit 100 cycle times, Often it is stored in a cycle time when being filled with, the most first removes the cycle time being stored at first, and Calculate meansigma methods Tz of the cycle time being stored in and preserve, utilizing Tz value to differentiate cycle to be identified Signal, to reduce the impact of power network frequency fluctuation, uses three to screen point simultaneously and reduces erroneous judgement Probability.

Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.At cycle just At the cycle zero passage of half cycle ascent stage, i.e. screening point 0 and arrange voltage zero-cross detection module, it is adopted Negative half period, signal condition is isolated further through electric resistance partial pressure, diode with cycle positive half-wave signal The clock end CLK of rear feeding d type flip flop, the Q of d type flip flop terminate single-chip microcomputer external interrupt mouth, This external interrupt mouth is arranged to level triggers, the D end ground connection of d type flip flop, and S terminates single-chip microcomputer I / O mouth, this I/O mouth puts 1 at ordinary times.When cycle positive half-wave zero cross signal arrives, immediately its After cycle signal rising edge make d type flip flop Q end be 0, single-chip microcomputer external interrupt mouth low level, Thus produce interruption, interrupt service routine performs instruction: described I/O mouth sets to 0, the Central Shanxi Plain Disconnected, timing, described I/O mouth are put 1, are opened interruption.Remaining two comparator is separately positioned on week The ripple positive half cycle ascent stage, the examination point 1 and 50% to 70% at 35% to 50% place of crest voltage The examination point 2 at place.

Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and opens Beginning timing, when cycle voltage zero-cross, is arranged on the voltage zero-cross detection module screening point 0 In V0, the output voltage of d type flip flop jumps vanishing, produces and interrupts, records in its zero crossing Break time Th0；Hereafter, the output of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning Voltage, when week, wave voltage reached the threshold voltage of V1, output voltage saltus step from high to low, Scanning records its bound-time Th1；Voltage comparator V2 at point 2 screened in same scanning record Output voltage bound-time Th2, by the output electricity of Th0 and voltage zero-cross detection module V0 Pressure bound-time setting value Ts0 is made comparisons；The output voltage of Th1 and voltage comparator V1 During the output voltage saltus step of bound-time setting value Ts1 and Th2 and voltage comparator V2 Between setting value Ts2 make comparisons respectively, if in the range of allowable error, then this Zhen detected Level signal is true, is otherwise false.Above-mentioned judge discriminator signal as true time, calculate this cycle letter Clock timer number between zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time Timing time Tzu, makes comparisons it with meansigma methods Tz of cycle time, if less than setting Cycle time error Tzv then cycle signal is true, at this moment preserves Tzu and takes 20ms with synchronization Timer timing time is added, and the value that will add up is stored in synchrotimer.

When clock timer starts timing with cycle voltage zero-cross, then timing is to 16ms to 18.5ms Between open interruption, clock timer timing to 25ms to 27ms when opening break period setting value Tk Between pass break period setting value Tn time close interrupt.

After system boot, clock timer starts timing, when first all wave voltage mistake being detected When zero, it is arranged on the output voltage saltus step of the voltage zero-cross detection module V0 screening point 0, Thus producing interruption, the time T0 taking out cycle voltage over zero preserves, and clock timer is clear Zero and start timing, at this moment cycle time voltage crosses zero Th0 is 0, and above-mentioned side pressed by single-chip microcomputer simultaneously Method scans and judges discriminator signal.Due to detection is first cycle, clock timer be Starting timing during cycle voltage zero-cross, the value of its Th0, Th1 and Th2 must add the cycle time 20ms deducts out the difference of break period setting value Tk, if three discriminator signals are true, takes The time T0 of the cycle voltage over zero gone out is stored in synchrotimer as initial time, next Secondary i.e. for the first time open the break period and take Tk.Being otherwise fictitious time, now the clock timer time must add Upper T0, continues detection.

When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving inspection Survey the cycle time, therefore the clock timer timing time between twice cycle signal zero passage be with The cycle time, 20ms made comparisons, it is determined that cycle signal is true time, then be to take 20ms to subtract Th0 Difference be added with synchrotimer timing time, preserve the standard cycle time 20 i.e. for the first time Ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all the most every time Restart timing after being reset by clock timer when opening interruption, and be will when opening interruption The standard cycle time counts in synchrotimer, and clock timer of having no progeny in opening resets, and otherwise judges Cycle signal is fictitious time, and now the clock timer time must continue by upper plus T1=T0+Tk Method of stating detects first cycle again.After first cycle signal of detection is very, recover with Upper described cycle signal determining.

As it is shown in figure 1, if be detected that cycle signal is false, open the break period all exists next time After this opens the break period, when meansigma methods Tz of time delay cycle time, open interruption, and in opening Have no progeny time delay Tns time close interrupt, arrange pass the break period be when cycle signal screen point 0 time Do not produce interruption, at this moment must start to sweep more than the setting time point of Ts0 allowable error scope Retouch, and when scanning is screened point 1 and screens point 2, voltage comparator output voltage does not produce Saltus step, is all closing the interruption of break period Tns pass and is stopping scanning, and Tns is:

Tns=Tn-Tk

If be detected that cycle signal is true, then next cycle is opened break period Tks and is:

Tks=Tk+Th0

I.e. from opening for the first time after the break period takes Tk, clock timer is all that timing is opened to Tks Interrupt, and restart timing after clearing, close during timing to Tns and interrupt, so that synchrometer Time the device time corrected by cycle time voltage crosses zero.

Repeat said process.If the upper cycle signal detected described in is true, and this cycle judges Time, discriminator signal is false, or the cycle time detected compares with meansigma methods Tz of cycle time Exceed setting cycle time error Tzv, or clock timer timing is to closing break period setting value During Tns, the voltage zero-cross detection module non-saltus step of V0 output voltage, do not produce interruption, Then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and deposits Storage, open the break period is to open the break period in last time to drive interruption, clock meter after Tz next time Time device have no progeny in opening clearing and timing, during timing to Tns close interruption, judge week the most every time The ripple signal true and false, though if false or this detection discriminator signal is true last time is false, then take N, Restore after N+1 in memorizer.

When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by memorizer N zero setting, and recover to use setting value Tks, the value at this moment taking (N+1) × 20ms is added on same In step timer.

The system synchronization time is the time of synchrotimer, adds current just at the clock meter of timing Time device time.

When judging to screen the some signal true and false, Th0, Th1, Th2 are by exporting with voltage comparator Voltage jump time setting value Ts0, Ts1, Ts2 make comparisons and see the most overproof, judge to screen The point signal true and false, can select: Th0, Th1, Th2 are this cycle discriminator signal of true time and are Very, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true Time, this cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.

If system fault, when N is more than a setting value between 25 to 70, owing to being Main controller and each lamp controller in system, the Tz value of its detection may be different with N value, at this moment, Power network frequency cumulative error, being likely to result in the synchrotimer time cannot be true by detecting Corrected during cycle signal, when detecting that cycle signal is true time, at this moment used clock timing The accumulative clocking value of device is directly added in synchrotimer, to reduce the asynchronous time of system, Accumulative clocking value is N × Tz+20ms.In the case of power network normal operation, N is much smaller than 25.

The cycle time error Tzv allowed and the flip-flop transition of voltage comparator output voltage set Value, is taken its meansigma methods by test assessment and obtains.

(4) accompanying drawing explanation:

Fig. 1 is that cycle screens data relationship schematic diagram；

Fig. 2 is cycle discriminator circuit structural representation；

Fig. 3 is the circuit structure block diagram of household intelligent lamplight control system body.

(5) detailed description of the invention:

Fig. 3 is that household intelligent lamplight control system body circuit structure block diagram includes: main controller 10, communications electronics switch 11, switch drive module 12, infra-red remote control are sent out Emitter 13, LED 14, electrical switch 15, cycle discriminator circuit 16, Lamp controller 17, wherein communications electronics switch 11, switch drive module 12, In cycle discriminator circuit 16 and Fig. 2, single-chip microcomputer U0 is included in lamp controller respectively 17 and main controller 10 in.Electrical switch 15, communications electronics switch 11 makes With bidirectional triode thyristor as switch.

Fig. 2 is the structural representation of cycle discriminator circuit 16, by: input circuit S0, Voltage zero-cross detection module V0, voltage comparator V1 and voltage comparator V2 structure Become.Single-chip microcomputer U0 refers to the single-chip microcomputer in lamp controller 17 and main controller 10. Input circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, turns It is changed to the input voltage that voltage comparator is the most stable.Single-chip microcomputer U0 uses 89C55WD, voltage comparator V1, voltage comparator V2 all use special voltage Comparator LM393, its reference voltage is to use the mu balanced circuit of stabilivolt to carry out burning voltage to compare The threshold voltage of device.

When mains AC voltage cycle signal zero passage, voltage zero-cross detection module V0's is defeated Going out voltage jump, single-chip microcomputer U0 produces interruption, records break period, simultaneously single-chip microcomputer U0 is additionally operable to the output electricity of scanning voltage comparator V1 and voltage comparator V2 Pressure, when output voltage saltus step record bound-time, be used for judging power network cycle signal thus Produce lock in time.

The infrared ray command signal that infra-red remote control transmitter sends, in main controller, integration is infrared When reception head receives this infrared ray command signal, infrared signal is become the signal of telecommunication and send preposition Amplifying circuit is amplified, then after the demodulation of demodulated device, instruction is believed signal detection circuit Number detection, it is achieved its various operations.

Claims (2)

1. the present invention relates to household intelligent lamplight control system body, it is characterized in that, after air switch One electrical switch is installed, this electrical switch parallel diode, and at main controller and each lamp decoration Controller is respectively mounted cycle discriminator circuit, for producing the lock in time of system, simultaneously at it One communications electronics switch of each installation and switch drive module, each lamp decoration control in telecommunication circuit Device processed all arranges unique number, and when selecting to show some number of LED, shutdown obtains corresponding Numbering and preserve, it is in the numbering period when can't detect grid cyclic wave signal, single-chip microcomputer Numbering data are stored in nonvolatile storage by the energy storage relying on its power capacitor, and system uses electricity Half wave communication of the line of force and half-wave are powered, and each lamp controller is isolated can't detect power network During the half-wave voltage signal that diode blocks, i.e. close LED power on communications electronics switch；Often The alternating current power supply of individual lamp controller is all connected to former socket or replaces the load of former on-off control, and Short switch, it is achieved lamp decoration controls, and each lamp controller all controls one group of LED, it synchronizes Time controls the lower light decorative effect forming the most independent cooperation again, and owner can pass through remote controller Control its opening and closing and lamp decoration model selection；

The switch drive module of communications electronics switch is to divide two after resistance blood pressure lowering from electric power netting twine Road, a road is used for each lamp controller, and it is connected to the list of each lamp controller through reversal connection diode Sheet machine I/O mouth, when half-wave is born in clock timer timing to cycle, scans this I/O mouth, as Fruit does not has signal i.e. system to be in half-wave communications status, and another road is used for each lamp controller and master Control device, this road is followed by the CLK end of d type flip flop through electric resistance partial pressure, and the Q termination of d type flip flop is single The external interrupt mouth of sheet machine, when the positive square-wave signal of CLK end arrives, its rising edge makes D touch Sending out device to set to 0, external interrupt mouth low level produces interrupts, and communicates, and main controller is provided with infrared Receive circuit, select to carry out half-wave traffic operation when running the glimmer of lamp decoration or suspending；

Cycle discriminator circuit is the positive half cycle ascent stage utilizing power network cycle, takes three and screens point Realizing the identification decision to cycle signal, the recycling cycle time sets up lock in time, and system sets Put clock timer and synchrotimer, if be detected that adjacent two cycle signals are very, Then take out the clock timer timing time between these two adjacent cycle signal zero passages, sequentially It is stored in cycle time memory cell, when being often stored in a cycle when being filled with 100 cycle time Between, the most first remove the cycle time being stored at first, and calculate the flat of cycle time of being stored in Average Tz, utilizes Tz value to differentiate cycle signal to be identified；

Two comparators are respectively used to screen point 1, screen point 2, in the cycle positive half cycle ascent stage At cycle zero passage, i.e. screening point 0 and arrange voltage zero-cross detection module, it uses cycle positive half-wave Signal is sent into D after electric resistance partial pressure, diode isolate negative half period, signal condition further and is triggered The clock end CLK of device, when cycle positive half-wave zero cross signal arrives, cycle letter immediately after Number rising edge makes d type flip flop Q end be 0, single-chip microcomputer external interrupt mouth low level, thus produces Interrupting, remaining two comparator is separately positioned on cycle positive half cycle ascent stage, the 35% of crest voltage Examination point 1 at 50% and the examination point 2 at 50% to 70% place；

Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, clock timer resets also Start timing, when cycle voltage zero-cross, be arranged on the voltage zero-cross detection module screening point 0 The output voltage of middle d type flip flop jumps vanishing, produces and interrupts, records its zero crossing break period Th0；Hereafter, the output voltage of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning, when When all wave voltages reach the threshold voltage of voltage comparator V1, output voltage is jumped from high to low Becoming, scanning records its bound-time Th1；Voltage comparator at point 2 screened in same scanning record V2 output voltage bound-time Th2, if described bound-time is in the range of allowable error, This discriminator signal then detected is true, is otherwise false, above-mentioned judge discriminator signal as true time, Calculate this cycle signal zero passage and the cycle signal zero passage that an adjacent front discriminator signal is true time Between clock timer timing time Tzu, it is made comparisons with meansigma methods Tz of cycle time, If less than setting cycle time error Tzv, cycle signal is true, at this moment preserves Tzu also Taking 20ms to be added with synchrotimer timing time, the value that will add up is stored in synchrotimer；

When clock timer starts timing with cycle voltage zero-cross, then timing is to 16ms to 18.5 Opening interruption when opening break period setting value Tk between ms, clock timer timing is to 25ms extremely Close during pass break period setting value Tn between 27ms and interrupt；

When first cycle voltage zero-cross being detected, it is arranged on the voltage zero-cross inspection screening point 0 Survey the output voltage saltus step of module, thus produce interruption, take out the time of cycle voltage over zero T0 preserves, and is reset by clock timer and starts timing, at this moment cycle time voltage crosses zero Th0 Being 0, single-chip microcomputer scans as stated above and judges discriminator signal, its Th0, Th1 and Th2's Value must deduct open the difference of break period setting value Tk plus cycle time 20ms, if three Individual discriminator signal is true, and the time T0 of the cycle voltage over zero of taking-up is stored in as initial time In synchrotimer, i.e. for the first time open the break period takes Tk next time, is otherwise fictitious time, now The clock timer time must continue detection plus T0；

When first and adjacent second cycle voltage zero-cross being detected, it is determined that cycle signal is True time, then be to take 20ms to subtract the difference of Th0 and be added with synchrotimer timing time, in opening Clock timer of having no progeny reset, otherwise judge cycle signal as fictitious time, now during clock timer Between must continue first cycle of detection the most again, work as detection plus T1=T0+Tk First cycle signal be very after, recover above-described cycle signal determining；

If be detected that cycle signal is false, open the break period all when this opens interruption next time After between, when meansigma methods Tz of time delay cycle time, open interruption, and the time delay Tns that has no progeny in opening Time close interrupt, arrange pass the break period be when cycle signal screening is fictitious time, close the break period Tns closes and interrupts and stop scanning, and Tns is:

Tns=Tn-Tk

If be detected that cycle signal is true, then next cycle is opened break period Tks and is:

Tks=Tk+Th0

I.e. from opening for the first time after the break period takes Tk, clock timer is all that timing is opened to Tks Interrupt, and restart timing after clearing, close during timing to Tns and interrupt；

Repeat said process, if described in the upper cycle signal that detects be true, this cycle judges Time, discriminator signal is false, then close when clock timer timing to Tns and interrupt, at this moment remember not Meter cycle N be 1 and store, open next time the break period be last time opened the break period pass through Opening interruption after Tz, clock timer is had no progeny in opening and is reset and timing, Central Shanxi Plain during timing to Tns Disconnected, judge the cycle signal true and false the most every time, though if false or this detection discriminator signal is true But last time is false, then take N, restore after N+1 in memorizer；

When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by memorizer Middle N zero setting, and recover to use setting value Tks, the value at this moment taking (N+1) × 20ms is added on In synchrotimer；

The system synchronization time is the time of synchrotimer, adds current just at the clock of timing The time of timer；

When judging to screen the some signal true and false, select: Th0, Th1, Th2 are this cycle of true time Discriminator signal is true, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 is true time, and this cycle discriminator signal is true, depending on to judgement cycle signal true and false difference requirement It is fixed,

If N is more than a setting value between 25 to 70, use the accumulative timing of clock timer Value is directly added in synchrotimer, and accumulative clocking value is N × Tz+20ms.

Household intelligent lamplight control system body the most according to claim 1, it is characterised in that bag Include:

Main controller 10, communications electronics switch 11, switch drive module 12, red Outside line remote control transmitter 13, LED 14, electrical switch 15, cycle are screened Circuit 16, lamp controller 17, wherein single-chip microcomputer U0 and communications electronics switch 11, switch drive module 12 and cycle discriminator circuit 16 are included in lamp respectively In decorations controller 17 and main controller 10；

Cycle discriminator circuit 16 is by input circuit S0, voltage zero-cross detection module V0, voltage comparator V1 and voltage comparator V2 are constituted, input circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to voltage The input voltage that comparator is the most stable；

The infrared ray command signal that infra-red remote control transmitter sends, in main controller, integration is infrared Reception head receives this infrared ray command signal and realizes its various operations.