CN105826294A - Six-layer integrated circuit board and technical method thereof - Google Patents
Six-layer integrated circuit board and technical method thereof Download PDFInfo
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- CN105826294A CN105826294A CN201610195956.0A CN201610195956A CN105826294A CN 105826294 A CN105826294 A CN 105826294A CN 201610195956 A CN201610195956 A CN 201610195956A CN 105826294 A CN105826294 A CN 105826294A
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- clad plate
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000003825 pressing Methods 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000007689 inspection Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 6
- 235000003392 Curcuma domestica Nutrition 0.000 claims description 3
- 244000008991 Curcuma longa Species 0.000 claims description 3
- 238000010009 beating Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 235000003373 curcuma longa Nutrition 0.000 claims description 3
- 238000011161 development Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 238000003801 milling Methods 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 238000002203 pretreatment Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 235000013976 turmeric Nutrition 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000012545 processing Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 2
- 238000012797 qualification Methods 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
- B32B37/24—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer not being coherent before laminating, e.g. made up from granular material sprinkled onto a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a six-layer integrated circuit board. The six-layer integrated circuit board has a thickness of 1.2mm, comprises a first-layer circuit, a second-layer circuit, a third-layer circuit, a fourth-layer circuit (L4), a fifth-layer circuit, a sixth-layer circuit, a first pressing insulation layer, a second pressing insulation layer, and a first guide hole, and is characterized in that the needed six-layer integrated circuit board is obtained by respectively manufacturing the first-layer circuit, the second-layer circuit, the third-layer circuit, the fourth-layer circuit, the fifth-layer circuit and the sixth-layer circuit, then pressing the circuits and carrying out subsequent processing. The six-layer integrated circuit board and the technical method, brought forward by the invention solve the problems of complex manufacturing process, low finished product qualification rate and the like of a conventional six-layer circuit board, have the advantages of simple structure and simple technical method, realize modular processing of a six-layer board to a certain degree, reduce the technical complexity, improve the production efficiency and finished product qualification rate, decrease the economic cost and improve economic benefits.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly relate to a kind of six layers of integrated circuit and process thereof.
Background technology
Along with developing rapidly of electronic technology, the integrated level of integrated circuit is more and more higher, particularly the most urgent to the demand of the high-end integrated circuit plate of high-power and Highgrade integration at aerospace field.Prior art uses the feature of copper base: coefficient of heat transfer is high, require the biggest to hold stream ability with base circuit board circuit layer, but there are six layers of copper base in prior art, owing to pressure plate structure is more complicated, each operation of follow-up batch plate produces and has some setbacks, the problems such as complex process, product qualified rate are low.
Summary of the invention
For deficiency of the prior art, it is an object of the invention to provide a kind of six layers of surface-mounted integrated circuit and process thereof.By making first and second layer of circuit respectively three pieces of copper-clad plates, third and fourth layer of circuit, five, the six layers of circuit, then by its pressing and carry out subsequent treatment and obtain required 6-layer circuit board, achieve the modularity processing of six laminates to a certain extent, this invention effectively solves the problems such as six layers of circuit manufacturing process complexity, product qualified rate are low, improves 6-layer circuit board and manufactures economy.
The technical solution of the present invention:
A kind of six layers of surface-mounted integrated circuit, its thickness is 1.2mm, including ground floor circuit L1, second layer circuit L2, third layer circuit L3, the 4th layer of circuit L4, layer 5 circuit L5, layer 6 circuit L6, the 1st pressing insulating barrier N1, the 2nd pressing insulating barrier N2, guide hole 1D1；Ground floor circuit L1 and second layer circuit L2 is made up of one piece of copper-clad plate two sides, third layer circuit L3 and the 4th layer of circuit L4 is made up of one piece of copper-clad plate two sides, layer 5 circuit L5 and layer 6 circuit L6 is made up of one piece of copper-clad plate two sides；It is characterized in that: described six layers of surface-mounted integrated circuit are formed by three pieces of copper-clad plate pressings, and third layer circuit L3 is ground plane, the 4th layer of circuit L4 is bus plane, and first and second, five, six layers of circuit are signals layer.
A kind of process of six layers of surface-mounted integrated circuit, it is characterised in that: comprise the following steps:
Sawing sheet: the copper-clad plate of bulk is cut into the size of design；
L1 L2 layer make: in first piece of copper-clad plate, complete ground floor circuit (L1) and the making of second layer circuit (L2)；
L3 L4 layer make: in second piece of copper-clad plate, complete third layer circuit (L3) and the making of second layer circuit (L4)；
Lamination N1: the second layer circuit (L2) of make first piece of copper-clad plate and the third layer circuit (L3) of second piece of copper-clad plate are pressed into formation the 1st pressing insulating barrier (N1)；
Boring: get out required hole, such as guide hole 1 (D1) by design requirement on circuit boards；
L5 L6 layer make: in the 3rd piece of copper-clad plate, complete layer 5 circuit (L5) and the making of layer 6 circuit (L6)；
Lamination N2: the 4th layer of circuit (L4) of make second piece of copper-clad plate and the layer 5 circuit (L5) of the 3rd piece of copper-clad plate are pressed into formation the 2nd pressing insulating barrier (N2)；
Welding resistance: the 6-layer circuit board good by pre-treatment, is printed onto solder mask the space of a whole page by silk screen, then is exposed after required pad protection with film image, is dissolved by not ink in UV photoreaction, finally give required pad and hole during development；
Surface processes: 6-layer circuit board carries out turmeric process, layer gold thickness >=0.08 μm；
Molding: carry out 6-layer circuit board beating on lathe pin hole, on pin location, upper plate, milling plate and cleaning etc.；
Inspection: 6-layer circuit board energising is carried out electrical property inspection and inspection eventually.
Preferably, described first, second, third and fourth, five, six layers of circuit copper cash >=10Z, live width, line-spacing and impedance tolerance are ± 10%.
Preferably, described guide hole D1 copper thickness >=25 μm.
Preferably, described: the 1st pressing insulating barrier N1, the 2nd pressing insulating barrier N2 thickness >=15 μm respectively.
The present invention has simple in construction, the feature that process is easy, first and second layer of circuit, third and fourth layer of circuit, the five, the six layers of circuit are made respectively three pieces of copper-clad plates, then by its pressing and carry out subsequent treatment and obtain required 6-layer circuit board, achieve the modularity processing of six laminates to a certain extent, reduce process complexity, improve production efficiency and product qualified rate, reduce Financial cost, improve economy.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in describing embodiment below, the required accompanying drawing used is briefly described, wherein:
Fig. 1 is present configuration schematic diagram；
Fig. 2 is present invention process flow chart；
In accompanying drawing, the labelling of each parts is as follows: L1, ground floor circuit；L2, second layer circuit；L3, third layer circuit；L4, the 4th layer of circuit；L5, layer 5 circuit；L6, layer 6 circuit；N1, the 1st pressing insulating barrier；N2, the 2nd pressing insulating barrier；D1, guide hole 1.
Detailed description of the invention
The present invention can be embodied as by disclosed technology, can be conducted further description the present invention by the following examples, but, the scope of the present invention is not limited to following embodiment.
Embodiment 1
Embodiment is as shown in Figure 1: a kind of six layers of surface-mounted integrated circuit, its thickness is 1.2mm, including ground floor circuit L1, second layer circuit L2, third layer circuit L3, the 4th layer of circuit L4, layer 5 circuit L5, layer 6 circuit L6, the 1st pressing insulating barrier N1, the 2nd pressing insulating barrier N2, guide hole 1D1；Ground floor circuit L1 and second layer circuit L2 is made up of one piece of copper-clad plate two sides, third layer circuit L3 and the 4th layer of circuit L4 is made up of one piece of copper-clad plate two sides, layer 5 circuit L5 and layer 6 circuit L6 is made up of one piece of copper-clad plate two sides；It is characterized in that: described six layers of surface-mounted integrated circuit are formed by three pieces of copper-clad plate pressings, and third layer circuit L3 is ground plane, the 4th layer of circuit L4 is bus plane, and first and second, five, six layers of circuit are signals layer.
It is arranged so as to 6-layer circuit board and makes between signals layer mutually isolated, it is to avoid the crosstalk that wiring layer cabling is brought, bus plane is adjacent with ground plane, defines a capacitance structure, intercouples effective, signal is more stable.
Further, described first, second, third and fourth, five, six layers of circuit copper cash >=10Z, live width, line-spacing and impedance tolerance are ± 10%.
Further, described guide hole D1 copper thickness >=25 μm.
Further, described: the 1st pressing insulating barrier N1, the 2nd pressing insulating barrier N2 thickness >=15 μm respectively.
Embodiment 2
Embodiment is as shown in Figure 2: the process of a kind of six layers of surface-mounted integrated circuit, it is characterised in that: comprise the following steps:
Sawing sheet: the copper-clad plate of bulk is cut into the size of design；
L1 L2 layer make: in first piece of copper-clad plate, complete ground floor circuit (L1) and the making of second layer circuit (L2)；
L3 L4 layer make: in second piece of copper-clad plate, complete third layer circuit (L3) and the making of second layer circuit (L4)；
Lamination N1: the second layer circuit (L2) of make first piece of copper-clad plate and the third layer circuit (L3) of second piece of copper-clad plate are pressed into formation the 1st pressing insulating barrier (N1)；
Boring: get out required hole, such as guide hole 1 (D1) by design requirement on circuit boards；
L5 L6 layer make: in the 3rd piece of copper-clad plate, complete layer 5 circuit (L5) and the making of layer 6 circuit (L6)；
Lamination N2: the 4th layer of circuit (L4) of make second piece of copper-clad plate and the layer 5 circuit (L5) of the 3rd piece of copper-clad plate are pressed into formation the 2nd pressing insulating barrier (N2)；
Welding resistance: the 6-layer circuit board good by pre-treatment, is printed onto solder mask the space of a whole page by silk screen, then is exposed after required pad protection with film image, is dissolved by not ink in UV photoreaction, finally give required pad and hole during development；
Surface processes: 6-layer circuit board carries out turmeric process, layer gold thickness >=0.08 μm；
Molding: carry out 6-layer circuit board beating on lathe pin hole, on pin location, upper plate, milling plate and cleaning etc.；
Inspection: 6-layer circuit board energising is carried out electrical property inspection and inspection eventually.
Claims (5)
1. six layers of surface-mounted integrated circuit, its thickness is 1.2mm, including ground floor circuit (L1), second layer circuit (L2), third layer circuit (L3), the 4th layer of circuit (L4), layer 5 circuit (L5), layer 6 circuit (L6), the 1st pressing insulating barrier (N1), the 2nd pressing insulating barrier (N2), guide hole 1 (D1)；Ground floor circuit (L1) and second layer circuit (L2) are made up of one piece of copper-clad plate two sides, third layer circuit (L3) and the 4th layer of circuit (L4) is made up of one piece of copper-clad plate two sides, layer 5 circuit (L5) and layer 6 circuit (L6) are made up of one piece of copper-clad plate two sides；It is characterized in that: described six layers of surface-mounted integrated circuit are formed by three pieces of copper-clad plate pressings, and third layer circuit (L3) is ground plane, the 4th layer of circuit (L4) is bus plane, and first and second, five, six layers of circuit are signals layer.
Six layers of surface-mounted integrated circuit the most according to claim 1, it is characterised in that: described first, second, third and fourth, five, six layers of circuit copper cash >=10Z, live width, line-spacing and impedance tolerance are ± 10%.
Six layers of surface-mounted integrated circuit the most according to claim 1, it is characterised in that: described guide hole 1 (D1) copper thickness >=25 μm.
Six layers of surface-mounted integrated circuit the most according to claim 1, it is characterised in that: described: the 1st pressing insulating barrier (N1), the 2nd pressing insulating barrier (N2) thickness >=15 μm respectively.
5. the process of six layers of surface-mounted integrated circuit, it is characterised in that: comprise the following steps:
Sawing sheet: the copper-clad plate of bulk is cut into the size of design；
L1 L2 layer make: in first piece of copper-clad plate, complete ground floor circuit (L1) and the making of second layer circuit (L2)；
L3 L4 layer make: in second piece of copper-clad plate, complete third layer circuit (L3) and the making of second layer circuit (L4)；
Lamination N1: the second layer circuit (L2) of make first piece of copper-clad plate and the third layer circuit (L3) of second piece of copper-clad plate are pressed into formation the 1st pressing insulating barrier (N1)；
Boring: get out required hole, such as guide hole 1 (D1) by design requirement on circuit boards；
L5 L6 layer make: in the 3rd piece of copper-clad plate, complete layer 5 circuit (L5) and the making of layer 6 circuit (L6)；
Lamination N2: the 4th layer of circuit (L4) of make second piece of copper-clad plate and the layer 5 circuit (L5) of the 3rd piece of copper-clad plate are pressed into formation the 2nd pressing insulating barrier (N2)；
Welding resistance: the 6-layer circuit board good by pre-treatment, is printed onto solder mask the space of a whole page by silk screen, then is exposed after required pad protection with film image, is dissolved by not ink in UV photoreaction, finally give required pad and hole during development；
Surface processes: 6-layer circuit board carries out turmeric process, layer gold thickness >=0.08um；
Molding: carry out 6-layer circuit board beating on lathe pin hole, on pin location, upper plate, milling plate and cleaning etc.；
Inspection: 6-layer circuit board energising is carried out electrical property inspection and inspection eventually.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610195956.0A CN105826294A (en) | 2016-03-31 | 2016-03-31 | Six-layer integrated circuit board and technical method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610195956.0A CN105826294A (en) | 2016-03-31 | 2016-03-31 | Six-layer integrated circuit board and technical method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105826294A true CN105826294A (en) | 2016-08-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610195956.0A Pending CN105826294A (en) | 2016-03-31 | 2016-03-31 | Six-layer integrated circuit board and technical method thereof |
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| Country | Link |
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| CN (1) | CN105826294A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111134671A (en) * | 2019-12-27 | 2020-05-12 | 上海交通大学 | Flexible multi-channel repeatable array type HD-sEMG sensor and preparation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101448373A (en) * | 2007-11-27 | 2009-06-03 | 华硕电脑股份有限公司 | Method for improving electromagnetic band gap architecture and multilayer board architecture applying same |
| CN102137551A (en) * | 2011-03-16 | 2011-07-27 | 蔡新民 | Production method of high-frequency four-layer circuit board |
| CN103037636A (en) * | 2011-09-30 | 2013-04-10 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board and manufacture method of multilayer circuit board |
-
2016
- 2016-03-31 CN CN201610195956.0A patent/CN105826294A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101448373A (en) * | 2007-11-27 | 2009-06-03 | 华硕电脑股份有限公司 | Method for improving electromagnetic band gap architecture and multilayer board architecture applying same |
| CN102137551A (en) * | 2011-03-16 | 2011-07-27 | 蔡新民 | Production method of high-frequency four-layer circuit board |
| CN103037636A (en) * | 2011-09-30 | 2013-04-10 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board and manufacture method of multilayer circuit board |
Non-Patent Citations (2)
| Title |
|---|
| 宋双杰: "《电子线路CAD技术》", 30 June 2009 * |
| 杨玉芳: "《电器制图及CAD》", 28 February 2014 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111134671A (en) * | 2019-12-27 | 2020-05-12 | 上海交通大学 | Flexible multi-channel repeatable array type HD-sEMG sensor and preparation |
| CN111134671B (en) * | 2019-12-27 | 2021-07-06 | 上海交通大学 | Flexible multi-channel repeatable array type HD-sEMG sensor and preparation |
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Application publication date: 20160803 |
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