CN105789065A - 一种芯片封装结构、终端设备及方法 - Google Patents

一种芯片封装结构、终端设备及方法 Download PDF

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Publication number
CN105789065A
CN105789065A CN201610219333.2A CN201610219333A CN105789065A CN 105789065 A CN105789065 A CN 105789065A CN 201610219333 A CN201610219333 A CN 201610219333A CN 105789065 A CN105789065 A CN 105789065A
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China
Prior art keywords
chip
substrate
packaging structure
described substrate
soldered ball
Prior art date
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CN201610219333.2A
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CN105789065B (zh
Inventor
周意保
张文真
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Application filed by Guangdong Oppo Mobile Telecommunications Corp Ltd filed Critical Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority to CN201610219333.2A priority Critical patent/CN105789065B/zh
Priority to CN201811653795.0A priority patent/CN109727935A/zh
Publication of CN105789065A publication Critical patent/CN105789065A/zh
Priority to PCT/CN2017/079593 priority patent/WO2017174007A1/zh
Priority to EP17778671.2A priority patent/EP3442017A1/en
Priority to US16/079,459 priority patent/US20190051574A1/en
Application granted granted Critical
Publication of CN105789065B publication Critical patent/CN105789065B/zh
Priority to US16/438,918 priority patent/US10679917B2/en
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

本发明公开了一种芯片封装结构，包括：基底；芯片，设置于所述基底之上；以及填充层，设置于所述基底之上，且围绕所述芯片的一部分，所述填充层的材料为环氧树脂材料，且所述环氧树脂材料呈白色。本发明还公开了一种具有该芯片封装结构的终端设备，以及一种芯片封装结构的制备方法。采用本发明实施例可提供一种响应速度快的芯片封装结构。

Description

一种芯片封装结构、终端设备及方法
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种芯片封装结构、终端设备及方法。
背景技术
电子产品已进入表面贴装技术(SurfaceMountTechnology，SMT)时代，随着电子产品向小型化方向发展，贴装元件的外向尺寸逐渐小型化。
随着科技的进步，指纹识别功能已成为智能手机、平板电脑等终端设备的标配。目前，指纹模组芯片的形态多种多样，有圆形、正方形、长方形等。实际应用中，指纹模组芯片或其他芯片的封装需要考虑多方面的因素，比如性能、成本、外观等等。可见，如何提供一种响应速度快的芯片封装结构已成为亟待解决的问题。
发明内容
本发明实施例所要解决的技术问题在于，提供一种响应速度快的芯片封装结构、终端设备及方法。
第一方面，本发明实施例提供一种芯片封装结构，包括：
基底；
芯片，设置于所述基底之上；
以及填充层，设置于所述基底之上，且围绕所述芯片的一部分，所述填充层的材料为环氧树脂材料，且所述环氧树脂材料呈白色。
在结合第一方面的一个可能的设计中，所述芯片通过焊球连接所述基底，所述焊球呈阵列式分布在所述基底上。
在结合第一方面的一个可能的设计中，所述芯片通过金线连接所述基底。
在结合第一方面的一个可能的设计中，所述基底和所述芯片通过透明光学胶粘结。
在结合第一方面的一个可能的设计中，所述焊球的直径的范围为0.22mm～0.3mm。
在结合第一方面的一个可能的设计中，相邻焊球间的间距为0.46mm～0.55mm。
在结合第一方面的一个可能的设计中，所述芯片封装结构还包括设置于所述基底之上的加强结构。
在结合第一方面的一个可能的设计中，所述加强结构的热传导系数高于所述基底的热传导系数。
在结合第一方面的一个可能的设计中，所述基底与所述加强结构通过透明光学胶粘结。
在结合第一方面的一个可能的设计中，所述加强结构延伸超出所述基底的边缘。
第二方面，本发明实施例提供一种终端设备，包括一种芯片封装结构，其中，所述芯片封装结构包括基底、芯片、以及填充层，所述芯片设置于所述基底之上，所述填充层，设置于所述基底之上，且围绕所述芯片的一部分，所述填充层的材料为环氧树脂材料，且所述环氧树脂材料呈白色。
在结合第二方面的一个可能的设计中，所述芯片通过焊球连接所述基底，所述焊球呈阵列式分布在所述基底上。
在结合第二方面的一个可能的设计中，所述芯片通过金线连接所述基底。
在结合第二方面的一个可能的设计中，所述基底和所述芯片通过透明光学胶粘结。
在结合第二方面的一个可能的设计中，所述焊球的直径的范围为0.22mm～0.3mm和/或相邻焊球间的间距为0.46mm～0.55mm。
在结合第二方面的一个可能的设计中，所述芯片封装结构还包括设置于所述基底之上的加强结构。
在结合第二方面的一个可能的设计中，所述加强结构的热传导系数高于所述基底的热传导系数。
第三方面，本发明实施例提供一种芯片封装结构的制备方法，该方法用于制备第一方面提供的芯片封装结构，包括：
提供一基底；
在所述基底之上设置一芯片。
在所述基底之上设置一围绕芯片的一部分的填充层。
在结合第三方面的一个可能的设计中，在所述基底与芯片之间设置一金线，以使所述芯片通过所述金线连接所述基底。
在结合第三方面的一个可能的设计中，在所述基底和所述芯片之间设置一透明光学胶，以粘结所述基底和所述芯片。
在结合第三方面的一个可能的设计中，所述焊球的直径的范围为0.22mm～0.3mm和/或相邻焊球间的间距为0.46mm～0.55mm。
在结合第三方面的一个可能的设计中，在所述基底之上设置加强构件，以避免所述基底翘曲。
在结合第三方面的一个可能的设计中，设置所述基底之上的所述加强构件高于所述基底的热传导系数。
在结合第三方面的一个可能的设计中，在所述基底与所述加强构件之间设置一透明光学胶，以粘结所述基底与所述加强结构。
可以看出，本发明实施例中，填充层30呈白色，当芯片封装结构应用在白色面板玻璃的终端设备上时，指纹芯片或者其他芯片的表面盖板，无需再印刷油墨层，可省去一道工序，降低成本，且减少油墨层的厚度之后，芯片到手指的距离变短，整个电容响应，信号强度更高，终端设备获取到的信息质量更好，有利于提高终端设备响应速度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种芯片封装结构的剖面示意图；
图2为本发明实施例提供的另一种芯片封装结构的剖面示意图；
图3为本发明实施例提供的另一种芯片封装结构的剖面示意图；
图4为本发明实施例提供的一种终端设备的结构示意图；
图5为本发明实施例提供的一种芯片封装结构的制备方法。
具体实施方式
为了使本发明实施例的目的、技术方案和优点更加清楚，下面结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
除非另作定义，此处使用的技术术语或科学术语应对作为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明中使用的“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序、数量或者重要性。同样，“一个”、“一”或“该”等类似词语也不表示数量限制，而只是用来表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词语前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或物件。“连接”或者相连等类似的词语并非限定于物理的或者机械的连接，而是可以包含电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了清晰起见，在附图中层或区域的厚度被放大，而非根据实际的比例绘制。当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”时，该元件可以“直接”位于另一个元件“上”，或者可以存在中间元件。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参见图1-图3，图1-图3为一种芯片封装结构的剖面示意图，该芯片封装结构包括基底10、芯片20，填充层30、芯片20设置于基底10之上，填充层30设置于基底10之上，且围绕芯片20的一部分，填充层30的材料为环氧树脂材料(EpoxyMoldingCompound，EMC)，且该环氧树脂材料呈白色。可见，由于填充层30呈白色，当芯片封装结构应用在白色面板玻璃的终端设备上时，指纹芯片或者其他芯片的表面盖板，无需再印刷油墨层，可省去一道工序，降低成本，且减少油墨层的厚度之后，芯片到手指的距离变短，整个电容响应，信号强度更高，终端设备获取到的信息质量更好，有利于提高终端设备响应速度。
其中，基底10可包括介电材料，比如有机材料。有机材料可为具有玻璃纤维的聚丙烯(polypropylene，PP)、环氧树脂(epoxyresin)、聚酰亚胺(polyimide)中的至少一种。填充层30可保护芯片20免于受损及/或被污染。芯片20为指纹模组芯片，当然芯片20也可以是其他芯片。
可选的，该封装结构还可包括另一基底，该基底例如为(但不限于)印刷电路板。基底10及芯片20可设置于另一基底的上表面之上。在一个实施例中，基底10的厚度可小于另一基底的厚度。
可选的，该封装结构还可包括导电构件，该导电构件设置在另一基底与芯片20之间，电性信号可通过该导电构件在另一基底与芯片20之间传递。
可选的，芯片20通过焊球40连接基底，焊球40呈阵列式分布在基底10上。
可选的，焊球40的直径的范围为0.22mm～0.3mm。
可选的，相邻焊球40间的间距为0.46mm～0.55mm。
其中，相邻焊球40之间的间距可以是相等的也可以是不相等的，比如阵列式排列的焊球的最外行与次外行之间行间距小于其他相邻行之间的行间距，阵列式排列的焊球的最外列与次外列之间列间距小于其他列邻行之间的行间距，又比如，阵列式排列的焊球的行间距沿芯片封装结构的中心点方向依次增大，阵列式排列的焊球的列间距沿芯片封装结构的中心点方向依次增大等等，本发明不作限定。
可选的，芯片20通过金线50连接基底10。
可选的，基底10和芯片20通过透明光学胶60粘结。
其中，在芯片20通过金线50连接基底10的结构中，为了强化芯片封装的可靠度与结构稳定度，需要在基底10和芯片20之间通过光学胶60进行粘结。当然光学胶60可以用其他具有黏结作用的胶水替代，本发明不作限定。
可选的，芯片封装结构还包括设置于基底10之上的加强结构70。
可选的，加强结构70的热传导系数高于基底10的热传导系数。
可选的，基底10与加强结构70通过透明光学胶80粘结。
可选的，加强结构70延伸超出基底10的边缘。
其中，基于电子产品轻、薄及集成化的需求，芯片封装的尺寸已持续缩小。基底10的厚度因而缩小。比如，基底10的厚度范围可在100μm～200μm之间，或者，基底10的厚度可在20μm～80μm之间。由于基底10厚度的缩减，基底10的结构强度也相应减小。承载芯片20的基底10可能存在翘曲(warpage)问题，使得将基底10设置在其他电子构件上的步骤变得难以进行。因此，芯片封装的可靠度与结构稳定度是不足的。为了强化芯片封装的可靠度与结构稳定度，在基底10之上设置加强构件70以避免基底10翘曲。此外，加强构件70热传导系数(thermalconductivity)高于基底10的热传导系数。这样，不仅强化了芯片封装的结构强度及可靠度，还能增进芯片运作期间所产生热能的消散。加强构件70可包括(但不限于)不锈钢、铜、铝、金、银、不同金属材料所制成的合金、或前述的组合。为了增强加强构件70与基底10之间的黏结，可在加强构件70与基底10通过透明光学胶80进行粘结。当然光学胶80可以用其他具有黏结作用的胶水替代，本发明不作限定。
请参见图4，图4为本发明实施例提供的一种终端设备的结构示意图，其中，图4中所示的A为图1-图3所示的芯片封装结构，该芯片封装结构包括基底10、芯片20，填充层30、芯片20设置于基底10之上，填充层30设置于基底10之上，且围绕芯片20的一部分，填充层30的材料为环氧树脂材料(EpoxyMoldingCompound，EMC)，且该环氧树脂材料呈白色。
其中，本发明所述的终端设备，又称之为用户设备(UserEquipment，UE)，是一种向用户提供语音和/或数据连通性的设备，例如，具有无线连接功能的手持式设备、车载设备等。常见的终端例如包括：手机、平板电脑、笔记本电脑、掌上电脑、移动互联网设备(mobileinternetdevice，MID)、可穿戴设备，例如智能手表、智能手环、计步器等。
可选的，芯片20通过焊球40连接基底，焊球40呈阵列式分布在基底10上。
可选的，焊球40的直径的范围为0.22mm～0.3mm。
可选的，相邻焊球40间的间距为0.46mm～0.55mm。
可选的，芯片20通过金线50连接基底10。
可选的，基底10和芯片20通过透明光学胶60粘结。
可选的，芯片封装结构还包括设置于基底10之上的加强结构70。
可选的，加强结构70的热传导系数高于基底10的热传导系数。
可选的，基底10与加强结构70通过透明光学胶80粘结。
可选的，加强结构70延伸超出基底10的边缘。
可以看出，本发明实施例中，当终端设备的面板玻璃为白色面板玻璃时，芯片封装结构的填充层30呈白色，将该芯片封装结构安置于该终端设备上时，指纹芯片或者其他芯片的表面盖板，无需再印刷油墨层，可省去一道工序，降低成本，且减少油墨层的厚度之后，芯片到手指的距离变短，整个电容响应，信号强度更高，终端设备获取到的信息质量更好，有利于提高终端设备响应速度。
请参见图5，图5为本发明实施例提供的一种芯片封装结构的制备方法，包括：
S501、提供一基底10。
S502、在基底10之上设置一芯片20。
S503、在基底10之上设置一围绕芯片20的一部分的填充层30。
可选的，在基底10之上设置一呈阵列式分布的焊球40，以使芯片20通过焊球40连接基底10。
可选的，在基底10与芯片20之间设置一金线50，以使芯片20通过金线50连接基底10。
可选的，在芯片20通过金线50连接基底10的结构中，为了强化芯片封装的可靠度与结构稳定度，在基底10和芯片20之间设置一透明光学胶60，以粘结基底10和芯片20。
可选的，焊球40的直径的范围为0.22mm～0.3mm。
可选的，相邻焊球40间的间距为0.46mm～0.55mm。
可选的，为了强化芯片封装的可靠度与结构稳定度，在基底10之上设置加强构件70以避免基底10翘曲。
可选的，为了进芯片运作期间所产生热能的消散，设置基底10之上的加强构件70高于基底10的热传导系数。
可选的，为了增强加强构件70与基底10之间的黏结，在基底10与加强构件70之间设置一透明光学胶80，以粘结基底10与加强结构70。
以上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种芯片封装结构，其特征在于，包括：
基底；
芯片，设置于所述基底之上；
以及填充层，设置于所述基底之上，且围绕所述芯片的一部分，所述填充层的材料为环氧树脂材料，且所述环氧树脂材料呈白色。
2.根据权利要求1所述的芯片封装结构，其特征在于，所述芯片通过焊球连接所述基底，所述焊球呈阵列式分布在所述基底上。
3.根据权利要求1所述的芯片封装结构，其特征在于，所述芯片通过金线连接所述基底。
4.根据权利要求3所述的芯片封装结构，其特征在于，所述基底和所述芯片通过透明光学胶粘结。
5.根据权利要求2所述的芯片封装结构，其特征在于，所述焊球的直径的范围为0.22mm～0.3mm和/或相邻焊球间的间距为0.46mm～0.55mm。
6.根据权利要求1-5任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括设置于所述基底之上的加强结构。
7.根据权利要求6所述的芯片封装结构，其特征在于，所述加强结构的热传导系数高于所述基底的热传导系数。
8.根据权利要求6或7所述的芯片封装结构，其特征在于，所述基底与所述加强结构通过透明光学胶粘结。
9.一种终端设备，其特征在于，包括权利要求1至8任一权项所述的芯片封装结构。
10.一种芯片封装结构的制备方法，其特征在于，包括：
提供一基底；
在所述基底之上设置一芯片；
在所述基底之上设置一围绕芯片的一部分的填充层。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106897709A (zh) * 2017-03-08 2017-06-27 广东欧珀移动通信有限公司 指纹识别模组及电子装置
WO2017174007A1 (zh) * 2016-04-08 2017-10-12 广东欧珀移动通信有限公司 一种芯片封装结构、终端设备及方法
CN110544674A (zh) * 2018-05-28 2019-12-06 浙江清华柔性电子技术研究院 芯片集成结构
CN113261096A (zh) * 2019-12-13 2021-08-13 深圳市汇顶科技股份有限公司 一种芯片封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076206A (ja) * 2000-08-21 2002-03-15 Orient Semiconductor Electronics Ltd フリップチップ結合パッケージ
US20020121705A1 (en) * 2001-03-02 2002-09-05 Siliconware Precision Industries Co., Ltd. Flip chip semiconductor package
JP2005223366A (ja) * 2005-04-27 2005-08-18 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
CN101026131A (zh) * 2006-02-22 2007-08-29 富士通株式会社 半导体器件及其制造方法
CN103354228A (zh) * 2013-07-10 2013-10-16 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法
CN104867919A (zh) * 2015-05-27 2015-08-26 沈震强 提高光耦可靠性的封装结构及封装工艺

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6195142B1 (en) 1995-12-28 2001-02-27 Matsushita Electrical Industrial Company, Ltd. Organic electroluminescence element, its manufacturing method, and display device using organic electroluminescence element
JPH11340355A (ja) * 1998-05-25 1999-12-10 Nec Corp 半導体装置
DE10223035A1 (de) * 2002-05-22 2003-12-04 Infineon Technologies Ag Elektronisches Bauteil mit Hohlraumgehäuse, insbesondere Hochfrequenz-Leistungsmodul
JP4390541B2 (ja) * 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
CN100592538C (zh) * 2006-08-09 2010-02-24 广东昭信光电科技有限公司 高亮度白色光发光二极管的封装方法
JP5117843B2 (ja) * 2007-12-27 2013-01-16 三菱重工業株式会社 インバータ一体型電動圧縮機
JP2010093109A (ja) * 2008-10-09 2010-04-22 Renesas Technology Corp 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法
KR101744756B1 (ko) 2010-06-08 2017-06-09 삼성전자 주식회사 반도체 패키지
US20130119532A1 (en) * 2011-11-11 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Bumps for Chip Scale Packaging
US9607951B2 (en) * 2013-08-05 2017-03-28 Mediatek Singapore Pte. Ltd. Chip package
WO2015076591A1 (ko) * 2013-11-21 2015-05-28 주식회사 루멘스 발광 소자 패키지, 백라이트 유닛, 조명 장치 및 발광 소자 패키지의 제작 방법
US9746604B2 (en) * 2014-01-06 2017-08-29 Agira, Inc. Light guide apparatus and fabrication method thereof
CN104051367A (zh) * 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
CN105336733A (zh) * 2014-07-01 2016-02-17 四川新力光源股份有限公司 Led封装结构及发光器件
CN104182738A (zh) * 2014-08-26 2014-12-03 南昌欧菲生物识别技术有限公司 指纹识别模组及其制造方法
CN204242200U (zh) * 2014-08-26 2015-04-01 南昌欧菲生物识别技术有限公司 指纹识别装置及终端设备
CN204515795U (zh) * 2015-03-06 2015-07-29 南昌欧菲生物识别技术有限公司 指纹识别装置、设有该装置的触摸屏及终端设备
CN104882419B (zh) 2015-05-08 2017-11-24 无锡中感微电子股份有限公司 芯片封装
US9683278B2 (en) 2015-06-08 2017-06-20 Infineon Technologies Ag Diffusion solder bonding using solder preforms
CN105260707A (zh) * 2015-09-17 2016-01-20 南昌欧菲生物识别技术有限公司 一种指纹传感器模组及电子设备
KR101787832B1 (ko) * 2015-10-22 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
CN105789065B (zh) * 2016-04-08 2019-02-12 Oppo广东移动通信有限公司 一种芯片封装结构、终端设备及方法
CN205845930U (zh) * 2016-04-08 2016-12-28 广东欧珀移动通信有限公司 一种芯片封装结构及终端设备
US11003884B2 (en) 2016-06-16 2021-05-11 Qualcomm Incorporated Fingerprint sensor device and methods thereof
JP2018186197A (ja) 2017-04-26 2018-11-22 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076206A (ja) * 2000-08-21 2002-03-15 Orient Semiconductor Electronics Ltd フリップチップ結合パッケージ
US20020121705A1 (en) * 2001-03-02 2002-09-05 Siliconware Precision Industries Co., Ltd. Flip chip semiconductor package
JP2005223366A (ja) * 2005-04-27 2005-08-18 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
CN101026131A (zh) * 2006-02-22 2007-08-29 富士通株式会社 半导体器件及其制造方法
CN103354228A (zh) * 2013-07-10 2013-10-16 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法
CN104867919A (zh) * 2015-05-27 2015-08-26 沈震强 提高光耦可靠性的封装结构及封装工艺

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
王孝培等: "《实用冲压技术手册》", 31 October 2013, 机械工业出版社 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017174007A1 (zh) * 2016-04-08 2017-10-12 广东欧珀移动通信有限公司 一种芯片封装结构、终端设备及方法
CN106897709A (zh) * 2017-03-08 2017-06-27 广东欧珀移动通信有限公司 指纹识别模组及电子装置
CN110544674A (zh) * 2018-05-28 2019-12-06 浙江清华柔性电子技术研究院 芯片集成结构
CN113261096A (zh) * 2019-12-13 2021-08-13 深圳市汇顶科技股份有限公司 一种芯片封装结构

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