US20020121705A1 - Flip chip semiconductor package - Google Patents

Flip chip semiconductor package Download PDF

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Publication number
US20020121705A1
US20020121705A1 US09973611 US97361101A US2002121705A1 US 20020121705 A1 US20020121705 A1 US 20020121705A1 US 09973611 US09973611 US 09973611 US 97361101 A US97361101 A US 97361101A US 2002121705 A1 US2002121705 A1 US 2002121705A1
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substrate
semiconductor package
chip
flip chip
semiconductor
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US09973611
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US6459144B1 (en )
Inventor
Han-Ping Pu
Shih-Kuang Chiu
Keng-Yuan Liao
Chien-Ping Huang
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

Description

    FIELD OF THE INVENTION
  • The present invention relates to flip chip semiconductor packages, and more particularly, to a flip chip semiconductor package in the use of an adhesive larger in contractibility during thermal contraction. [0001]
  • BACKGROUND OF THE INVETION
  • A flip-chip semiconductor package employs advanced packaging technology, which differs from a conventional BGA semiconductor package mainly in that, a semiconductor chip is disposed in the flip-chip semiconductor package in an upside down manner. That is, an active side of the semiconductor chip having a plurality of electronic circuits and electronic elements mounted thereon faces toward a substrate, and is electrically connected to the substrate by a plurality of solder bumps. Then, an underfilling process is performed to underfill gaps between the adjacent solder bumps with an insulative adhesive, for allowing the semiconductor chip to be firmly disposed on the substrate. Such a flip-chip semiconductor package is advantageous with no need of space-occupying bonding wires for providing the electrical connection for the semiconductor chip. This therefore effectively reduces overall thickness of the flip-chip semiconductor package as desired for a low profile demand. [0002]
  • In order to improve both performance and capacity for a single semiconductor package, a substrate can be enlarged in surface area for incorporating more semiconductor chips, or a semiconductor chip can be increased in size for sufficiently accommodating a larger number of electronic elements thereon. However, as shown in FIG. 1, in a solder reflow process for bonding solder bumps [0003] 15 and in a cooling process after curing, due to a significant difference in coefficient of thermal expansion (CTE) between a large sized substrate 10 (35×35 mm2) and a large sized semiconductor chip 11 (15×15 mm2), the substrate 10 having a relatively greater CTE thermally contracts more rapidly than the chip 11, and accordingly the substrate 10 is warped with its planarity reduced. This further causes the solder bumps 15 to be delaminated or cracked from the substrate 10, and even impedes the adhesive flow in a subsequent underfilling process, thereby possibly resulting in void formation. As such, the reliability concern for the packaged product is greatly increased.
  • In order to eliminate the above-mentioned drawbacks, U.S. Pat. No. 6,020,221 discloses a fabrication method for preventing substrate warpage from occurrence. As shown in FIG. 2, a stiffener member made of metal such as copper is disposed around the semiconductor chip [0004] 11 on the large sized substrate 10, so as to reinforce the resistance of the substrate 10 to thermal contracting stress, and prevent the substrate 10 from deforming in response to the thermal stress in subsequent processes. However, the stiffener member 12 greatly increases the weight of the packaged product, which is not preferable for a low profile demand. Further, the stiffener member 12 is adhered to the substrate 10, and this additional adhering process increases the complexity and cost in fabrication.
  • Alternatively, U.S. Pat. No. 5,844,319 discloses the use of a collar [0005] 13, which has a smaller CTE than that of the substrate 10 and is disposed around the chip 11 on the substrate 10, as shown in FIGS. 3A and 3B. In the solder-reflow process, the collar 13 is used to absorb the difference in thermal stress between the chip 11 and the substrate 10, so as to maintain the planarity of the substrate 10 and protect solder joints 14 from damage, and further allow maintenance or rework to be easily performed for the chip with no need of the underfilling process. However, in no use of the underfilling process, the gaps between the adjacent solder bumps 15 are not blocked by the insulative adhesive, thereby easily resulting in improper electrical contact and short circuit; further, the chip and the substrate may suffer structural cracking and electricity loss in a high temperature process.
  • SUMMARY OF THE INVENTION
  • A primary objective of the present invention is to provide a flip chip semiconductor package, in which an adhesive compound having a larger coefficient of thermal expansion than that of a substrate is used to form an adhesive dam around a semiconductor chip on the substrate, so as to maintain the substrate planarity and structural intactness of the semiconductor chip. Moreover, the use of the adhesive dam, instead of a metal stiffener member, does not increase the overall weight of semiconductor the package, and eliminates the need of an additional adhering process for disposing the stiffener member, so that fabrication cost can be reduced. In addition, in the flip chip semiconductor package, a gap between the semiconductor chip and the substrate is filled with an insulative adhesive, in an effort to prevent improper electrical contact between adjacent solder bumps, and improve bonding quality of the solder bumps, as well as avoid structural cracking for the semiconductor chip and the substrate in a high temperature environment. [0006]
  • In accordance with the foregoing and other objectives, the present invention proposes a flip-chip semiconductor package, comprising a substrate predefined with a chip bonding area for mounting a semiconductor chip thereon; a larger sized semiconductor chip having its active surface facing toward the substrate and electrically connected to the substrate by a plurality of solder bumps; a dam structure formed around the chip and made of an adhesive compound having larger coefficient of thermal expansion of that of the substrate; an insulative adhesive for filling a gap between the chip and the substrate, and for encapsulating the solder bumps; a plurality of solder balls implanted on a back side of the substrate for electrically connecting the substrate to external devices; and an encapsulant for encapsulating the chip. [0007]
  • Since a conventional solder reflow process is employed for bonding the solder bumps to the substrate, it is not further detailed herein. It is to be noted that, during variation from high to low temperature in the solder reflow process, the substrate deforms more rapidly and to a greater extent than the semiconductor chip, and thus the dam structure needs to have more extensive deformation and produce a greater contraction force for counteracting excessive thermal stress of the substrate. As the result, planarity and structural intactness can be well maintained for the substrate and the semiconductor chip, as well as bonding quality of the solder bumps can be assured. Compared to a conventional metal stiffener member for increasing resistance for a substrate to thermal stress, the dam structure of the invention not only reduces overall weight of the semiconductor package, but also eliminates the need of an additional adhering process for use with the metal stiffener member, so that the fabrication cost can be reduced. [0008]
  • Moreover, gaps between the adjacent solder bumps are filled with the insulative adhesive by using a conventional dispensing process; this can prevent the adjacent solder bumps from electrically coming into contact with each other, and also help dissipate thermal stress between the substrate and the semiconductor chip. Therefore, bonding reliability of the solder bumps can be assured, and the substrate and the semiconductor chip can be prevented from structurally cracking at a high temperature in subsequent fabrication processes.[0009]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: [0010]
  • FIG. 1 (PRIOR ART) is a sectional view of a conventional large sized semiconductor package with a warped substrate; [0011]
  • FIG. 2 (PRIOR ART) is a sectional view of a conventional large sized semiconductor package with a stiffener member; [0012]
  • FIGS. 3A and 3B (PRIOR ART) are respectively a top view and a sectional view of a conventional semiconductor package with a collar; [0013]
  • FIG. 4 is a sectional view of a semiconductor package of a first preferred embodiment of the invention; [0014]
  • FIGS. [0015] 5A-5F are schematic diagrams depicting the steps involved in fabricating a semiconductor package of the invention;
  • FIG. 6 is a top view of a semiconductor package of a second preferred embodiment of the invention; [0016]
  • FIG. 7 is a top view of a semiconductor package of a third preferred embodiment of the invention; [0017]
  • FIG. 8 is a sectional view of a semiconductor package of a fourth preferred embodiment of the invention; [0018]
  • FIG. 9 is a sectional view of a semiconductor package of a fifth preferred embodiment of the invention; and [0019]
  • FIG. 10 is a sectional view of another semiconductor package of a fifth preferred embodiment of the invention.[0020]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • First Preferred Embodiment [0021]
  • A flip chip semiconductor package of a first embodiment of the invention is described as follows with reference to FIGS. 4 and 5A-[0022] 5F.
  • Illustrated in FIG. 4 is a sectional view of the flip chip semiconductor package of the invention. The semiconductor package [0023] 2 of the first embodiment comprises a large sized substrate 20 having a chip bonding area 202 for mounting a large sized semiconductor chip 21 thereon, and electrically connected to the semiconductor chip 21 by a plurality of solder bumps 22; an adhesive dam 203 surrounding the semiconductor chip 21, and made of an adhesive compound having a larger coefficient of thermal expansion (CTE) than that of the substrate 20; an insulative adhesive 23 for filling a gap between the semiconductor chip 21 and the substrate 20, for encapsulating the solder bumps 22; a plurality of solder balls 24 for electrically connecting the substrate 20 to external devices; and an encapsulant 25 for encapsulating the semiconductor chip 21.
  • Referring first to FIGS. 5A (top view) and [0024] 5B (sectional view), a large sized substrate 20 (referred to a substrate larger in size than 35×35 mm2) has a front side 200 and an opposing back side 201. On the front side 200 there is predefined a chip bonding area 202. An adhesive compound, e.g. epoxy resin with a CTE of 25 ppm/° C., greater in CTE than the substrate 20 is used to form an adhesive dam 203 by using a conventional dispensing process, in a manner that the adhesive dam 203 surrounds and is spaced apart from the chip bonding area 202 by a pathway 204 with a certain width used for adhesive injection in an underfilling process. The type, applying area on the substrate and usage amount of the adhesive compound depend on the surface area and CTE of the substrate. Generally a large sized substrate is made of an organic material such as polyimide resin, bismaleimidetriazine, epoxy resin, or triazine resin. The larger the CTE or size of a substrate, the greater the degree of warpage; thus an adhesive compound having an even higher CTE (i.e. greater contraction degree) is desired.
  • Referring to FIG. 5C, a large sized semiconductor chip [0025] 21 (referred to a semiconductor chip larger in size than 15 mm×15 mm) has an active surface 210 and an opposing non-active surface 211. On the active surface 210, there are formed a plurality of bonding pads 212 and a plurality of solder bumps 22, wherein, after disposing the solder bumps 22 on the chip bonding area 202, a solder reflow process is performed for electrically connecting the solder bumps 22 to the substrate 20.
  • Referring to FIG. 5D, after completing the high temperature solder reflow process, in a cooling process, the adhesive dam [0026] 203 surrounding the semiconductor chip 21 thermally contracts more rapidly due to its larger CTE (as indicated by arrows in the drawing). This therefore provides a stronger contraction force to counteract excessive thermal stress of the substrate 20 (as indicated by arrows in the drawing). As a result, planarity of the semiconductor chip 21 and the substrate 20, and bonding reliability of the solder bumps 22 can be assured, as well as quality of performing subsequent fabrication processes (such as underfilling process) for the semiconductor package can be improved.
  • Referring to FIG. 5E, after completing the electrical connection of the solder bumps [0027] 22 to the substrate 20, an insulative adhesive 23 is injected by using a conventional dispenser 27 into the pathway 204 between the semiconductor chip 21 and the adhesive dam 203, so as to fill a gap 28 between the semiconductor chip 21 and the substrate 20 and encapsulate the solder bumps 22. This underfilling process is capable of preventing the adjacent solder bumps 22 from electrically coming into contact with each other, and dissipating thermal stress between the substrate 20 and the semiconductor chip 21, so as to maintain structural intactness for both the substrate 20 and the semiconductor chip 21 at a high temperature.
  • Referring to FIG. 5F, after completing the underfilling process, a molding process is performed in a manner that the semiconductor package [0028] 2 is placed in a mold 29, and a molding resin (not shown) is injected into the mold 29 at a high temperature for forming an encapsulant 25 that encapsulates the semiconductor chip 21. Then, a conventional ball implanting process is employed for implanting a plurality of solder balls 24 on the back side 201 of the substrate 20, so as to electrically connect the substrate 20 to external devices. This therefore completes the fabrication of the semiconductor package 2 of the invention, as shown in FIG. 4.
  • In conclusion, as the adhesive dam [0029] 203 can function in counteracting the excessive thermal stress of the substrate 20 in the molding process and the solder reflow process, the planarity of the substrate as well as the quality and reliability of the solder ball implantation can all be effectively assured.
  • Second Preferred Embodiment [0030]
  • FIG. 6 illustrates a top view of a flip chip semiconductor package of a second embodiment of the invention. The semiconductor package [0031] 3 of the second embodiment is structurally identical to that of the first embodiment, with the only difference in that, in the semiconductor package 3, a semiconductor chip 31 is used as the center of a circle for forming a circular adhesive dam 30-3 around the semiconductor chip 31 on peripheral area of a substrate 30, allowing underfilling adhesive 33 together with the semiconductor chip 31 to be included within the adhesive dam 303. Such a circular adhesive dam 303 is symmetrically distributed around the semiconductor chip 31, thereby making the substrate 30 sustain equal contraction force of the adhesive dam 303 at either of two sides thereof, and thus planarity of the substrate 30 can be well maintained.
  • Third Preferred Embodiment [0032]
  • FIG. 7 illustrates a top view of a flip chip semiconductor package of a third embodiment of the invention The third embodiment is structurally and functionally identical to the foregoing first and second embodiments, with the only difference in that an adhesive dam [0033] 303 of this embodiment is formed as two strips positioned on peripheral area at two sides of a substrate, respectively. As described above in the second embodiment, since the adhesive dam 303 is symmetrically distributed at two sides of a semiconductor chip, thus planarity of the substrate can be well maintained.
  • Fourth Preferred Embodiment [0034]
  • As shown in FIG. 8, a fourth embodiment of the invention is identical to the foregoing first embodiment in structure and fabrication for the semiconductor package, with the only difference in that a semiconductor chip [0035] 31 is fabricated in a direct exposing manner in this embodiment. After disposing the semiconductor chip 31 on a substrate 30 in a flip-chip manner, an underfilling process is performed for encapsulating an active surface 310 of the semiconductor chip 31 with no need of a subsequent molding process. This therefore reduces the fabrication cost, and allows a non-active surface 311 of the semiconductor chip 31 to be directly exposed to the atmosphere, so that a heat dissipating path is shortened for facilitating dissipation of heat generated by the semiconductor chip 31.
  • Fifth Preferred Embodiment [0036]
  • The flip chip semiconductor package of the invention can also incorporate a heat sink for increasing heat dissipating efficiency. As shown in FIGS. 9 and 10, the semiconductor package of the fifth embodiment is structurally identical to that of the first embodiment, with the only difference in that a heat sink [0037] 36 of this embodiment is directly or indirectly disposed on a semiconductor chip 31, in consideration of overall thickness of the semiconductor package and the heat dissipating efficiency of the semiconductor chip 31. The heat sink 36 does not interfere with an adhesive dam 303 formed on a substrate 30, and planarity of the substrate 30 disposed with the heat sink 36 can still be well maintained due to thermal contraction of the adhesive dam 303.
  • The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. [0038]

Claims (19)

    What is claimed is:
  1. 1. A flip chip semiconductor package, comprising:
    a substrate;
    a semiconductor chip mounted on the substrate in a flip chip manner that a gap is formed between the semiconductor chip and the substrate;
    a dam structure formed on the substrate outside the semiconductor chip, and made of an adhesive compound having a greater coefficient of thermal expansion than that of the substrate;
    an underfilling material for filling the gap between the semiconductor chip and the substrate;
    a plurality of first conductive elements for electrically connecting the semiconductor chip to the substrate; and
    a plurality of second conductive elements for electrically connecting the substrate to an external device.
  2. 2. The flip chip semiconductor package of claim 1, wherein the substrate is dimensioned to be larger than 35×35 mm2.
  3. 3. The flip chip semiconductor package of claim 1, wherein the coefficient of thermal expansion of the substrate is between 16 and 20 ppm/° C.
  4. 4. The flip chip semiconductor package of claim 1, wherein the substrate is made of a material selected from the group consisting of polyimide resin, bismaleimide triazine, epoxy resin and triazine resin.
  5. 5. The flip chip semiconductor package of claim 1, wherein the semiconductor chip is dimensioned to be larger than 15×15 mm2.
  6. 6. The flip chip semiconductor package of claim 1, wherein the substrate is much greater in coefficient of thermal expansion than the semiconductor chip.
  7. 7. The flip chip semiconductor package of claim 1, wherein the coefficient of thermal expansion of the adhesive compound is 25 ppm/° C.
  8. 8. The flip chip semiconductor package of claim 1, wherein the adhesive compound is an insulative material.
  9. 9. The flip chip semiconductor package of claim 8, wherein the insulative material is epoxy resin.
  10. 10. The flip chip semiconductor package of claim 1, wherein the adhesive compound for forming the dam structure is used in an amount and applied at a position on the substrate dependent on the coefficient of thermal expansion and size of the substrate, respectively.
  11. 11. The flip chip semiconductor package of claim 1, wherein the dam structure is formed around the semiconductor chip.
  12. 12. The flip chip semiconductor package of claim 1, wherein the dam structure is formed as a circular structure with the semiconductor chip being a circle center.
  13. 13. The flip chip semiconductor package of claim 1, wherein the dam structure is formed as two strips on peripheral area at two sides of the substrate.
  14. 14. The flip chip semiconductor package of claim 1, wherein the first conductive elements are solder bumps.
  15. 15. The flip chip semiconductor package of claim 1, wherein the semiconductor chip has an exposed non-active surface.
  16. 16. The flip chip semiconductor package of claim 1, wherein the semiconductor chip is encapsulated by an encapsulant.
  17. 17. The flip chip semiconductor package of claim 1, wherein a heat sink is disposed in the semiconductor package.
  18. 18. The flip chip semiconductor package of claim 13, wherein gaps between the adjacent solder bumps are filled with the underfilling material.
  19. 19. The flip chip semiconductor package of claim 1, wherein the second conductive elements are solder balls.
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