CN105765661B - 用于减少在存储器读存取期间的电力假信号的静态随机存取存储器(sram)全局位线电路及其相关方法和系统 - Google Patents

用于减少在存储器读存取期间的电力假信号的静态随机存取存储器(sram)全局位线电路及其相关方法和系统 Download PDF

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Publication number
CN105765661B
CN105765661B CN201480062055.3A CN201480062055A CN105765661B CN 105765661 B CN105765661 B CN 105765661B CN 201480062055 A CN201480062055 A CN 201480062055A CN 105765661 B CN105765661 B CN 105765661B
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Prior art keywords
bit line
sram
data
global
global bit
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CN105765661A (zh
Inventor
乔舒亚·兰斯·帕克特
史蒂芬·爱德华·莱尔斯
贾森·菲利浦·马茨洛夫
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
CN201480062055.3A 2013-11-26 2014-11-25 用于减少在存储器读存取期间的电力假信号的静态随机存取存储器(sram)全局位线电路及其相关方法和系统 Active CN105765661B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/090,288 2013-11-26
US14/090,288 US9019752B1 (en) 2013-11-26 2013-11-26 Static random access memory (SRAM) global bitline circuits for reducing power glitches during memory read accesses, and related methods and systems
PCT/US2014/067269 WO2015081056A1 (en) 2013-11-26 2014-11-25 Static random access memory (sram) global bitline circuits for reducing power glitches during memory read accesses, and related methods and systems

Publications (2)

Publication Number Publication Date
CN105765661A CN105765661A (zh) 2016-07-13
CN105765661B true CN105765661B (zh) 2018-08-28

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Country Status (8)

Country Link
US (1) US9019752B1 (enExample)
EP (3) EP3757998A1 (enExample)
JP (1) JP6639391B2 (enExample)
KR (1) KR102293806B1 (enExample)
CN (1) CN105765661B (enExample)
ES (1) ES2733375T3 (enExample)
HU (1) HUE043832T2 (enExample)
WO (1) WO2015081056A1 (enExample)

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US10446201B2 (en) * 2017-06-26 2019-10-15 Samsung Electronics Co., Ltd. Distributed global-bitline keeper/precharge/header circuit for low voltage operation
US10147483B1 (en) 2017-09-19 2018-12-04 Qualcomm Incorporated Robust write driver scheme for static random access memory compilers
US10783938B2 (en) * 2018-06-29 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM with local bit line, input/output circuit, and global bit line
US10741263B2 (en) * 2018-12-31 2020-08-11 Micron Technology, Inc. Standby biasing techniques to reduce read disturbs
US10984843B2 (en) 2019-03-01 2021-04-20 International Business Machines Corporation RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption
US11615837B2 (en) * 2020-09-22 2023-03-28 Qualcomm Incorporated Pseudo-triple-port SRAM datapaths
US12400690B2 (en) * 2022-08-10 2025-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Global boosting circuit

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US7423900B2 (en) * 2006-11-15 2008-09-09 Sony Computer Entertainment Inc. Methods and apparatus for low power SRAM using evaluation circuit
US7668037B2 (en) * 2007-11-06 2010-02-23 International Business Machines Corporation Storage array including a local clock buffer with programmable timing
US8077533B2 (en) * 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
US20110320851A1 (en) * 2010-06-23 2011-12-29 International Business Machines Corporation Port enable signal generation for gating a memory array device output
US20120008379A1 (en) * 2010-07-12 2012-01-12 International Business Machines Corporation Global bit line restore by most significant bit of an address line
US8345497B2 (en) * 2010-06-23 2013-01-01 International Business Machines Corporation Internal bypassing of memory array devices

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JP4721776B2 (ja) * 2004-07-13 2011-07-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7167385B2 (en) * 2005-02-11 2007-01-23 International Business Machines Corporation Method and apparatus for controlling the timing of precharge in a content addressable memory system
US7440335B2 (en) * 2006-05-23 2008-10-21 Freescale Semiconductor, Inc. Contention-free hierarchical bit line in embedded memory and method thereof
US7679979B1 (en) 2008-08-30 2010-03-16 Fronteon Inc High speed SRAM
JP5418207B2 (ja) * 2009-12-24 2014-02-19 富士通セミコンダクター株式会社 半導体メモリ、半導体メモリの動作方法およびシステム
US8325543B2 (en) 2010-02-26 2012-12-04 International Business Machines Corporation Global bit select circuit interface with false write through blocking
JP5505274B2 (ja) * 2010-11-22 2014-05-28 富士通セミコンダクター株式会社 スタティックｒａｍ
US8422313B2 (en) 2010-12-16 2013-04-16 International Business Machines Corporation Reduced power consumption memory circuitry
JP5776418B2 (ja) * 2011-07-29 2015-09-09 富士通セミコンダクター株式会社 半導体記憶装置及び半導体記憶装置の制御方法
US8934308B2 (en) 2011-10-14 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Tracking bit cell
US8755239B2 (en) 2011-11-17 2014-06-17 Texas Instruments Incorporated Read assist circuit for an SRAM

Patent Citations (6)

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Publication number Priority date Publication date Assignee Title
US8077533B2 (en) * 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
US7423900B2 (en) * 2006-11-15 2008-09-09 Sony Computer Entertainment Inc. Methods and apparatus for low power SRAM using evaluation circuit
US7668037B2 (en) * 2007-11-06 2010-02-23 International Business Machines Corporation Storage array including a local clock buffer with programmable timing
US20110320851A1 (en) * 2010-06-23 2011-12-29 International Business Machines Corporation Port enable signal generation for gating a memory array device output
US8345497B2 (en) * 2010-06-23 2013-01-01 International Business Machines Corporation Internal bypassing of memory array devices
US20120008379A1 (en) * 2010-07-12 2012-01-12 International Business Machines Corporation Global bit line restore by most significant bit of an address line

Also Published As

Publication number Publication date
CN105765661A (zh) 2016-07-13
HUE043832T2 (hu) 2019-09-30
US9019752B1 (en) 2015-04-28
EP3757998A1 (en) 2020-12-30
KR102293806B1 (ko) 2021-08-24
EP3531422A1 (en) 2019-08-28
ES2733375T3 (es) 2019-11-28
JP6639391B2 (ja) 2020-02-05
KR20160089473A (ko) 2016-07-27
EP3074980B1 (en) 2019-04-17
EP3074980A1 (en) 2016-10-05
JP2016537760A (ja) 2016-12-01
WO2015081056A1 (en) 2015-06-04

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