CN105762181A - Polycrystalline silicon emitting electrode transistor and manufacturing method therefor - Google Patents
Polycrystalline silicon emitting electrode transistor and manufacturing method therefor Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 230000007797 corrosion Effects 0.000 claims description 13
- 238000005260 corrosion Methods 0.000 claims description 13
- 239000010953 base metal Substances 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- -1 boron ion Chemical class 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000003892 spreading Methods 0.000 claims description 3
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- 230000004888 barrier function Effects 0.000 description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
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- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention provides a polycrystalline silicon emitting electrode transistor. The upper surface of a silicon substrate is provided with a plurality of N-type emitting regions with high doping density, wherein the lower layer of the silicon substrate is an N-type low-resistivity layer, and the upper layer of the silicon substrate is an N-type high-resistivity layer. An N-type doped polycrystalline silicon layer is connected with the upper part of the emitting regions. The transistor is characterized in that the upper part of a P-type thick base region is connected with an N-type auxiliary emitting region; the upper part of the N-type auxiliary emitting region is directly connected with the doped polycrystalline silicon layer; and a side surface of the N-type auxiliary emitting region is connected with the N-type emitting regions. The invention also provides a manufacturing method for the transistor. The transistor is advantageous in that the transistor can provide more uniform current distribution, is stronger in impact resistance, is better in reliability, and is lower in cost.
Description
Technical field
The invention belongs to silicon semiconductor device technical field, relate to a kind of transistor, be specifically related to a kind of polysilicon emitter transistor.
Background technology
Within 1979, HisaoKondo proposes gate associated transistor GAT (GateAssociatedTransistor), has carried out detailed analysis (see IEEETrans.ElectronDevice, vol.ED-27, PP.373-379.1980) subsequently.1994, Chen Fuyuan, inscription on ancient bronze objects are new, Wuzhong is imperial has done further analysis (see " Power Electronic Technique " the 4th phase 1994.11.pp52-55 in 1994) to gate associated transistor GAT, it is indicated that gate associated transistor device presents high pressure, high-speed switch and low saturation pressure degradation good characteristic.
null2000，Chinese invention patent ZL00100761.0 proposes the gate associated transistor of a kind of grooved gate polysilicon structure，The principle of its structure is as shown in Figure 8: be N-type low-resistivity layer 42 in lower floor、Upper strata is the upper surface of the silicon substrate film 4 of N-type high resistivity layer 41，There is the N-type launch site 3 of a plurality of high-dopant concentration，Launch site 3 is connected with emitter metal layer 1 by doped polysilicon layer 9，There is P type base 2 in the surrounding of every launch site 3，The side of P type base 2 P type doping content of ining succession is higher than base 2、The grid region 6 ' that depth ratio P type base 2 degree of depth is deep，Grid region 6 ' is connected with gate metal layer，The N-type high resistivity layer 41 of silicon substrate film 4 is collecting zone in base less than 2 and grid region part below 6 '，The N-type low-resistivity layer 42 of silicon substrate film 4 is colelctor electrode，The lower surface of N-type low-resistivity layer 42 is connected with collector electrode metal layer 8，Wherein: grid region 6 ' is flute profile，The bottom of this silicon groove 5 is P type high-doped zone；The above doped polysilicon layer 9 being connected to N-type of N-type launch site 3, this doped polysilicon layer 9 is connected with emitter metal layer 1；The bottom surface of every silicon groove 5 and side are covered with oxide layer 7, and the oxide layer 7 of side extends to the upper surface of silicon substrate film 4.The repetition interval of the unit of gate associated transistor and the distance in adjacent grid region are only small, it is possible to obtain bigger electric current density, CURRENT DISTRIBUTION evenly, faster switching speed, higher reliability than gate associated transistor before this.
The gate associated transistor of the grooved gate polysilicon structure of prior art requires that the bottom surface of every groove and side are covered with insulating barrier, and the insulating barrier of side extends to the upper surface of silicon substrate film.Otherwise being likely to be formed both sides after high temperature advances is all highly doped PN junction.It is conventional theory that the impurity concentration of the highly doped P-type silicon in both sides and N-type silicon reaches 5E19/cm3Above, then there is tunnels (see " semiconductor device basis " Edward S poplar work, People's Education Publishing House, book number: 13012.0638, P110 Fig. 4-12).In order to avoid the PN junction that formation both sides are all highly doped, sufficiently large alignment spacing must be reserved between emitter window and grooved grid region during layout design, which results in the distance in two adjacent grooved grid regions can not be too near, and the distance in the two of gate associated transistor adjacent grid regions its pinch off ability more remote is more weak.And the photoetching of launch site can not be fully aligned with the photoetching in grid region, this current unevenness allowing for launch site is even, thus reducing the current capacity of whole tube core.
Summary of the invention
In view of the above problems, it is an object of the invention to for the deficiencies in the prior art, a kind of polysilicon emitter transistor is provided, by the method then noting phosphorus diffusion in whole P type base and the dense base of P type depositing polysilicon immediately above, make it can provide CURRENT DISTRIBUTION evenly, there is stronger impact resistance, there is higher reliability, there is lower cost.
It is a further object of the present invention to provide the manufacture method of above-mentioned polysilicon emitter transistor.
For completing the purpose of the present invention, one polysilicon emitter transistor of the present invention, it is N-type low-resistivity layer in lower floor, upper strata is the N-type launch site that the upper surface of the silicon substrate film of N-type high resistivity layer has multiple high-dopant concentration, the above doped polysilicon layer being connected to N-type of this N-type launch site, this doped polysilicon layer is connected with emitter metal layer, P type base is had below each N-type launch site, in succession the doping content P type dense base higher than base in the side of P type base, the dense base of P type is orthogonal with P type dense base busbar, silicon substrate film arranged above with base metal layer, it is collecting zone that the upper strata N-type high resistivity layer of silicon substrate film is positioned at the part of below below P type base and the dense base of P type, lower floor's N-type low-resistivity layer of silicon substrate film is colelctor electrode, the lower surface of colelctor electrode is connected with collector electrode metal layer；
Described base metal layer is connected with P type dense base busbar；
The above of the described dense base of P type is connected with N-type pair launch site, and the above of this N-type pair launch site is connected with n-type doping polysilicon layer；
The side of described N-type pair launch site is connected with N-type launch site.
Preferably, the described dense base of P type is plane, or, the described dense base of P type is grooved.
Preferably, the junction depth of the described dense base of P type is deeper than the junction depth of P type base, or, the junction depth of the described dense base of P type is more shallow than the junction depth of P type base.
The present invention also provides for the manufacture method of a kind of polysilicon emitter transistor, including following process steps:
A., lower floor is provided to be N-type low-resistivity layer, upper strata is the silicon substrate film of N-type high resistivity layer；
B. advancing technique by oxidation, photoetching, boron ion implanting, diffusion, form P type base, the dense base of P type, P type dense base busbar, after diffusion advances, the upper surface of silicon substrate has layer of oxide layer；
C. optionally corrosion scale, the oxide layer corrosion above P type base and the dense base of P type is clean, retain the oxide layer above P type dense base busbar；
D. depositing polysilicon layer；
E. phosphonium ion injects, and forms n-type doping polysilicon layer, and advances the top in silicon substrate film P type base to form N-type launch site by spreading, forms N-type pair launch site on the top of the dense base of P type；
F. optionally shelter and corrode doped polysilicon layer, in N-type launch site and N-type pair launch site reserved above with doped polysilicon layer, above P type dense base busbar, do not stay doped polysilicon layer；
G. optionally corrosion scale, the oxide layer corrosion above dense for P type base busbar is clean, form contact hole；
H. splash-proofing sputtering metal layer；
I. optionally shelter and corroding metal layer, form emitter metal layer disconnected from each other and base metal layer；
J. thinning back side, sputtering collector electrode metal layer.
Preferably, described step B is formed P type base, the dense base of P type, P type dense base busbar order be: be initially formed P type base, then form the dense base of P type and P type dense base busbar.
Or, it is initially formed the dense base of P type and P type dense base busbar, then forms P type base.
Preferably, the dense base of P type in described step B, P type dense base busbar are the P type dense base busbar of the dense base of P type of the grooved formed by grooving and grooved.
Or, for the P type dense base busbar of the dense base of P type of plane and plane.
Technical scheme theing improvement is that than prior art:
First, the technique decreasing the high-quality oxide layer of one making, provide cost savings.Traditional handicraft needed before doing polysilicon, grow one layer of high-quality oxide layer, as insulating barrier, to avoid N-type polycrystalline silicon to connect through the pin hole of oxide layer with the following dense base of P type, eliminate now this time oxidation technology, save product cost and the production time of this process accordingly.
Second, it is achieved that launch site is fully aligned with dense base, solve in traditional method owing to the problem that the launch site current unevenness partially caused is even is overlapped in photoetching.
3rd, owing to alignment spacing need not be reserved, it is possible to the distance between two adjacent dense bases is reduced, namely it is repetitive is done little, improves the density of tube core unit, and then improve tube core and process the ability of electric current；And when off, owing to the distance of two adjacent dense bases is closer to causing that pinch off ability is higher, thus it is higher to resist second breakdown ability.
4th, particularly with the dense base of grooved, owing to eliminating the oxide layer of bottom and the sidewall covering groove, the width making groove increases, and then the emitter metal layer thickness of the sidewall of groove is increased, reduce the all-in resistance of emitter metal layer, be conducive to improving the current flow uniformity of die internal.
The beneficial effects of the present invention is:
A kind of polysilicon emitter transistor provided by the invention and manufacture method thereof, by reducing the technique forming oxide layer, the polysilicon emitter transistor made can lead to the CURRENT DISTRIBUTION provided evenly, has higher impact resistance, there is higher reliability, and lower in cost.Alternative bipolar tube, power MOS pipe and IGBT, it is applied to the fields such as great power LED, Switching Power Supply, electric car charger, electric automobile charging pile, motor variable-frequency speed-regulating, high-frequency welding machine, electromagnetic oven, convertible frequency air-conditioner, ups power, photovoltaic power generation grid-connecting, has wide market prospect.
Accompanying drawing explanation
Fig. 1 is the structural representation of a preferred embodiment of the present invention.
Fig. 2 is the overall schematic of a tube core of embodiment illustrated in fig. 1.
The A-A section that Fig. 3-Fig. 5 is Fig. 2 is positioned at the process flow diagram near P type dense base busbar.
Fig. 6 is the structural representation of another preferred embodiment of the present invention.
Fig. 7 is the structural representation of the another preferred embodiment of the present invention.
Fig. 8 is the structural representation of prior art.
Fig. 9 is another structural representation of prior art.
Accompanying drawing labelling
1: emitter metal layer；2:P type base；3:N type launch site；4: silicon substrate film；41:N type high resistivity layer；42:N type low-resistivity layer；5: silicon groove；51: dense base busbar silicon groove；The dense base of 6:P type；61:P type dense base busbar；6 ': grid region；7: oxide layer；8: collector electrode metal layer；9: doped polysilicon layer；10: base metal layer；11:N type pair launch site.
Detailed description of the invention
The present invention relates to polysilicon emitter transistor and preparation method thereof.
It should be noted that the N-type region territory above dense for P type base is called N-type pair launch site, measuring by experiment and find that this region is smaller on current amplification factor impact, namely actually this region only serves the effect in secondary emission district.
Oxide layer is the most frequently used insulating barrier, and in the present invention, oxide layer synonymously uses with insulating barrier or silicon dioxide oxide layer/insulating barrier.
The dense base of P type is called grid region in the prior art in the inventive solutions, and the two is distinctive in that, time the dense base of P type is deeper than P type base, the dense base of P type can be described as grid region, in embodiments of the present invention, uses both as synonym.
nullFig. 1-Fig. 5 is the structural representation of an embodiment of the polysilicon emitter transistor of the present invention and along the process chart of A-A section，Shown in Fig. 1, structure includes，It is N-type low-resistivity layer 42 in lower floor、Upper strata is the N-type launch site 3 that the upper surface of the silicon substrate film 4 of N-type high resistivity layer 41 has multiple high-dopant concentration，The above doped polysilicon layer 9 being connected to N-type of this N-type launch site 3，This doped polysilicon layer 9 is connected with emitter metal layer 1，P type base 2 is had below each N-type launch site 3，In succession the doping content P type dense base 6 higher than P type base 2 in the side of P type base 2，The dense base of P type 6 is orthogonal with P type dense base busbar 61，Silicon substrate film 4 arranged above with base metal layer 10，It is collecting zone that the upper strata N-type high resistivity layer 41 of silicon substrate film 4 is positioned at the part of P type base less than 2 and the dense base less than 6 of P type，N-type silicon for 60 μm of resistivity 35 Ω cm of thickness.Lower floor's N-type low-resistivity layer 42 of silicon substrate film 4 is colelctor electrode, and for the N-type silicon of 420 μm of resistivity 0.01 Ω cm of thickness, the lower surface of colelctor electrode is connected with collector electrode metal layer 8, and described base metal layer 10 is connected with P type dense base busbar 61；The above of the described dense base of P type 6 is connected with N-type pair launch site 11, and the above of this N-type pair launch site 11 is connected with n-type doping polysilicon layer 9；The side of described N-type pair launch site 11 is connected with N-type launch site 3.In the present embodiment, the dense base 6 of P type is grooved, and the junction depth of the dense base of P type 6 is deeper than the junction depth of P type base.
Fig. 2 is the overall schematic of a tube core of embodiment illustrated in fig. 1.Can be seen that the be separated by arrangement (in X direction) parallel with the dense base of P type 6 of a plurality of P type base 2, orthogonal with P type dense base busbar 61 (along Y-direction), in tube core lower edges part P type base 2 and the dense base 6 of P type, parallel with P type dense base busbar 61.Due to orthogonality relation P type base 2, the dense base 6 of P type in the middle part of tube core, cannot show in a process chart embodying structure with P type dense base busbar 61 simultaneously, therefore select near A-A profile P type dense base busbar that the part of (the dense base of P type 6 is parallel with P type dense base busbar 61) is to illustrate the technological process of the present embodiment structure, as shown in Figure 3-Figure 5.
As shown in Figure 3, corresponding to processing step A-B, the upper surface of silicon substrate film 4 has the dense base busbar silicon groove 51 of a plurality of parallel strip silicon groove 5 and orthogonal with silicon groove 5 (in the middle part of tube core) or parallel (die edge), the spacing of two adjacent silicon grooves 5 is 16 μm, silicon groove 5 deep 3 μm wide 4 μm, dense base busbar silicon groove 51 groove depth 3 μm between silicon groove 5, wide 20 μm, die edge dense base busbar silicon groove 51 deep 3 μm.Silicon groove 5 and dense base busbar silicon groove 51 bottom land by inject boron ion and in addition high temperature propelling and be correspondingly formed the dense base of high concentration grooved P type 6 and high concentration grooved P type dense base busbar 61, the surface concentration of boron is 5E19-1E20/cm3, junction depth 6 μm.In the process that high temperature advances, add oxygen so that the upper surface of N-type high resistivity layer 41 generates oxide layer (silicon dioxide oxide layer/insulating barrier), by the method for photoetching corrosion, outputs base window in oxide layer.The domain of base is designed such that base window is big window, and it includes the region between the dense base of grooved P type 6 and the dense base of adjacent grooved P type.After base window is outputed, by boron ion implanting and diffusible oxydation, forming the surface concentration of boron in type base, P type base 2, P 2 is 1E17-3E18/cm3, junction depth 4 μm.After base diffusible oxydation, the surface of P type base 2, the dense base of P type 6 and P type dense base busbar 61 forms the oxide layer 7 of silicon dioxide.
As shown in Figure 4.Corresponding to processing step C-E, optionally corrosion scale 7, clean for the oxide layer corrosion above dense to P type base 2 and P type base 6, retain P type dense base busbar 61 oxide layer 7 above.The doped polysilicon layer 9 of 0.6 μ m-thick is deposited by the method for LPCVD.Injected by phosphonium ion, form n-type doping polysilicon layer, and advance the top in silicon substrate film P type base 2 to form N-type launch site 3 by spreading, form N-type pair launch site 11 on the top of the dense base 6 of P type.The surface concentration of phosphorus is up to 1E21-4E21/cm3.The junction depth of N-type launch site 3 is 1.8 μm, the junction depth of N-type pair launch site 11 1.1 μm.
As it is shown in figure 5, corresponding to processing step F-J, optionally shelter and etch doped polysilicon layer, in N-type launch site 3 and N-type pair launch site 11 reserved above with doped polysilicon layer 9, above P type dense base busbar 61, do not stay doped polysilicon layer.Selective corrosion oxide layer 7, corrodes the oxide layer 7 above dense for P type base busbar 61 totally, forms contact hole.Splash-proofing sputtering metal layer, metal level is the aluminium lamination of 4 μm.By optionally sheltering and corroding metal layer, form emitter metal layer 1 disconnected from each other and base metal layer 10.Finally, the thinning back side of chip to 280 μm, sputtering thickness is that the titanium nickeline three-layer metal of 1 μm is as collector electrode metal layer 8.
Fig. 9 is the gate associated transistor of the grooved gate polysilicon structure shown in prior art.Fig. 9 and Fig. 1 is different in that: after the oxide layer 7 on P type base and the dense base of P type is formed, and adopts the method for photoetching corrosion to form emitter window.The layout size of emitter window is 4 μm, and the alignment deviation between itself and grid region is 2 μm.After emitter window is outputed, do polysilicon, note phosphorus, diffusion.Comparison diagram 9 and Fig. 1 are it can be seen that the dense base of P type 6 of the polysilicon emitter transistor shown in Fig. 1, P type base 2 and N-type launch site 3 are self aligned, and be self aligned between the grid region 6 ' of the gate associated transistor shown in Fig. 9 and P type base 2, N-type launch site 3 is not self aligned with grid region 6 ', P type base 2, emitter window is closer from the grid region 6 ' on the left side, distant from the grid region 6 ' on the right.So, in the launch site of the gate associated transistor of the prior art shown in Fig. 9, collector-emitter current density is uneven, in region between emitter window and the grid region on the left side, collector-emitter current density is relatively larger, in region between emitter window and the grid region on the right, collector-emitter current density is smaller.And the polysilicon emitter transistor of the technology of the present invention shown in Fig. 1 does not overlap inclined problem, so, in launch site, collector-emitter current density is uniform.
Fig. 6 is another preferred embodiment of the present invention.Fig. 6 and Fig. 1 is distinctive in that the dense base of the embodiment of Fig. 6 is plane.
Fig. 7 is the another preferred embodiment of the technology of the present invention.Fig. 7 and Fig. 1 is different only in that layout design, and the distance of the adjacent dense base of Fig. 1 is 16 μm, and the distance of the adjacent dense base of Fig. 7 is 10 μm.
Comparison diagram 7 and Fig. 9, technical scheme can be made close the distance of two adjacent dense bases, thus pinch off ability when improve shutoff, improves impact resistance.Prior art is then not all right, and two adjacent dense bases can cause launch site to overlap with dense base apart near, is unallowed according to the theory in past.
The base of the polysilicon emitter transistor of the present invention can be formed by adjacent dense base is overlapping.When adjacent dense base layout design close together and formed diffusion temperature higher time of dense base long time, adjacent dense base can overlap mutually, and the concentration of the p type impurity at overlapping position is relatively low.In such a case, it is possible to base need not individually be done, overlapping formation base, position.
The polysilicon of the polysilicon emitter transistor of the present invention can be monolayer, it is also possible to bilayer, the emission effciency of double level polysilicon is higher than single level polysilicon.Launch site can be plane, it is also possible to be grooved, and the current amplification factor of plane launch site is higher.The donor impurity of N-type launch site can be phosphorus, it is also possible to be phosphorus and two kinds of impurity of arsenic, applies two kinds of donor impurities and can reduce the stress of die internal, reduces defect concentration.
The shape of the launch site of the present invention can be bar shaped, square, hexagon, circle or other shapes, generally adopts bar shaped.For simplicity, the many places of description describe and have employed launch site is bar shaped, and base is bar shaped, and groove is bar shaped, mutually orthogonal groove the table top surrounded is bar shaped.This is the finger fork configuration of a kind of common power transistor.
Implementation result:
Compare by the embodiment (being called that B manages) of the prior embodiment (being called that A manages) shown in Fig. 9 with the technology of the present invention shown in Fig. 7.The die area of A pipe and B pipe is all 0.7mm*0.7mm.
A pipe and B pipe are used for 3U-105 electricity-saving lamp, power 24W.It is put in baking oven, impacts by High Temperature High Pressure.Result A pipe withstands 85 DEG C of switching surges 10 times, washes out for the 11st time.And B pipe can withstand 110 DEG C of 300V switching surges 200 times.Can be seen that the polysilicon emitter transistor of the present invention is more higher than the gate associated transistor impact resistance of existing grooved gate polysilicon structure, reliability is higher.
The polysilicon emitter transistor of the present invention, and between dense base and doped polysilicon layer, have the polysilicon emitter transistor of insulating barrier, broadly fall into latest generation power transistor, it is called cold bipolar tube (COOLBIPOLAR), (COOLGAT) is managed also referred to as cold GAT, belong to the regeneration product of bipolar tube, be also the strong competitor of power MOS pipe and IGBT.Doing power high equally, die area is less than the 1/4 of bipolar tube, power MOS pipe and IGBT, and maximum operating temperature will be high than above-mentioned power tube.Bipolar tube is owing to being subject to being susceptible to the restriction of second breakdown, and its maximum operating temperature is 150 DEG C.The restriction that IGBT declines rapidly owing to being subject under high temperature anti-breech lock ability, its maximum operating temperature is 175 DEG C.Power MOS pipe is owing to being subject to the restriction increased rapidly with temperature rising conducting resistance, and its maximum operating temperature is 200 DEG C.And cold bipolar tube is owing to can be operated in the weak negative temperature coefficient district of electric current, being not limited to the above, its maximum operating temperature is 220 DEG C.The alternative bipolar tube of cold bipolar tube, power MOS pipe and IGBT, it is applied to great power LED, Switching Power Supply, electric car charger, electric automobile charging pile, motor variable-frequency speed-regulating, high-frequency welding machine, electromagnetic oven, convertible frequency air-conditioner, ups power, the fields such as photovoltaic power generation grid-connecting, there is wide market prospect, and between dense base and DOPOS doped polycrystalline silicon, the polysilicon emitter transistor of non-oxidation layer has the polysilicon emitter transistor of oxide layer more to save technique than between dense base and DOPOS doped polycrystalline silicon in technical scheme, save cost, and the electric current in tube core is evenly, impact resistance is higher, reliability is higher.
Above-described embodiment is only for the present invention will be described but not limits the invention; therefore; for a person skilled in the art, when without departing substantially from spirit and scope of the invention, it is carried out various apparent change, all should within protection scope of the present invention.
Claims (10)
1. a polysilicon emitter transistor, it is N-type low-resistivity layer in lower floor, upper strata is the N-type launch site that the upper surface of the silicon substrate film of N-type high resistivity layer has multiple high-dopant concentration, the above doped polysilicon layer being connected to N-type of this N-type launch site, this doped polysilicon layer is connected with emitter metal layer, P type base is had below each N-type launch site, in succession the doping content P type dense base higher than P type base in the side of P type base, the dense base of P type is orthogonal with P type dense base busbar, silicon substrate film arranged above with base metal layer, it is collecting zone that the upper strata N-type high resistivity layer of silicon substrate film is positioned at the part of below below P type base and the dense base of P type, lower floor's N-type low-resistivity layer of silicon substrate film is colelctor electrode, the lower surface of colelctor electrode is connected with collector electrode metal layer, it is characterized in that:
Described base metal layer is connected with P type dense base busbar；
The above of the described dense base of P type is connected with N-type pair launch site, and the above of this N-type pair launch site is connected with n-type doping polysilicon layer；
The side of described N-type pair launch site is connected with N-type launch site.
2. polysilicon emitter transistor as claimed in claim 1, it is characterised in that: the described dense base of P type is plane.
3. polysilicon emitter transistor as claimed in claim 1, it is characterised in that: the described dense base of P type is grooved.
4. polysilicon emitter transistor as claimed in claim 1, it is characterised in that: the junction depth of the described dense base of P type is deeper than the junction depth of P type base.
5. polysilicon emitter transistor as claimed in claim 1, it is characterised in that: the junction depth of the described dense base of P type is more shallow than the junction depth of P type base.
6. the manufacture method of a polysilicon emitter transistor, it is characterised in that include following process steps:
A., lower floor is provided to be N-type low-resistivity layer, upper strata is the silicon substrate film of N-type high resistivity layer；
B. advancing technique by oxidation, photoetching, boron ion implanting, diffusion, form P type base, the dense base of P type, P type dense base busbar, after diffusion advances, the upper surface of silicon substrate has layer of oxide layer；
C. optionally corrosion scale, the oxide layer corrosion above P type base and the dense base of P type is clean, retain the oxide layer above P type dense base busbar；
D. depositing polysilicon layer；
E. phosphonium ion injects, and forms n-type doping polysilicon layer, and advances the top in silicon substrate film P type base to form N-type launch site by spreading, forms N-type pair launch site on the top of the dense base of P type；
F. optionally shelter and corrode doped polysilicon layer, in N-type launch site and N-type pair launch site reserved above with doped polysilicon layer, above P type dense base busbar, do not stay doped polysilicon layer；
G. optionally corrosion scale, the oxide layer corrosion above dense for P type base busbar is clean, form contact hole；
H. splash-proofing sputtering metal layer；
I. optionally shelter and corroding metal layer, form emitter metal layer disconnected from each other and base metal layer；
J. thinning back side, sputtering collector electrode metal layer.
7. manufacture method as claimed in claim 6, it is characterised in that described step B is formed P type base, the dense base of P type, P type dense base busbar order be: be initially formed P type base, then form the dense base of P type and P type dense base busbar.
8. manufacture method as claimed in claim 6, it is characterised in that described step B is formed P type base, the dense base of P type, P type dense base busbar order be: be initially formed the dense base of P type and P type dense base busbar, then form P type base.
9. the manufacture method as described in any one of claim 6-8, it is characterised in that the dense base of P type in described step B, P type dense base busbar are the P type dense base busbar of the dense base of P type of the grooved formed by grooving and grooved.
10. the manufacture method as described in any one of claim 6-8, it is characterised in that the dense base of P type in described step B, P type dense base busbar are the P type dense base busbar of the dense base of P type of plane and plane.
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