CN105552109B - A kind of short circuit anode landscape insulation bar double-pole-type transistor - Google Patents
A kind of short circuit anode landscape insulation bar double-pole-type transistor Download PDFInfo
- Publication number
- CN105552109B CN105552109B CN201510936970.7A CN201510936970A CN105552109B CN 105552109 B CN105552109 B CN 105552109B CN 201510936970 A CN201510936970 A CN 201510936970A CN 105552109 B CN105552109 B CN 105552109B
- Authority
- CN
- China
- Prior art keywords
- type
- sub
- anode
- regions
- district
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000009413 insulation Methods 0.000 title description 2
- 230000011218 segmentation Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 230000024241 parasitism Effects 0.000 description 2
- 241000406668 Loxodonta cyclotis Species 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
Abstract
The invention belongs to technical field of semiconductors, more particularly to a kind of SA LIGBT.The present invention major programme be, P+ anode regions and N+ anode regions inside N-type well region in the present invention, and the P+ anodes sub-district that is parallel to each other respectively by multiple row along device horizontal direction of P+ anode regions and N+ anode regions and N+ anode sub-districts are formed, while it is segmentation structure along device longitudinal direction；Meanwhile P+ anode regions and N+ anode regions lower contact have p type buried layer.When device forward conduction is in monopolar mode initial stage, p type buried layer and P+ anode regions form electronic barrier layer, they can hinder to collect from the electronics that emission of cathode comes by N+ anode regions, so as to increase the forward voltage drop of the PN junction that P+ anode regions and the first buried regions of p-type are formed with N-type well region or N-type high resistance area under monopolar mode, device just can be entered double pole mode under less monopolar current, so as to suppress the appearance of snapback phenomenons.Beneficial effects of the present invention are that can effectively suppress snapback phenomenons, while can also lift the OFF state characteristic of device.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of SA-LIGBT (Short Anode IGBT,
Short Anode-Lateral Insulated Gate Bipolar Transistor, short-circuit anode lateral insulated gate bipolar
Transistor npn npn).
Background technology
Igbt (IGBT) for BJT before and MOSFET element, it is maximum difference lies in
Its in forward conduction there are conductivity modulation effect, so as to which there is relatively low positive guide while keeping compared with high voltage
Logical pressure drop.But the negative effect thus brought is that plasma is stored in the drift region of IGBT in large quantities before device turns off, this
So that the turn-off power loss of IGBT is very big.SA-LIGBT (Short Anode LIGBT) is due to for the excess electron in drift region
Low-resistance leakage path is provided, so as to solve the problems, such as this well.
As shown in Figure 1, be traditional SA-LIGBT structure diagrams, compared to traditional IGBT, the characteristics of SA-LIGBT
It is to be used for a part for P+ anode regions to do N+ anode regions, so the excess electron in device turn off process kind, drift region is very
It is collected easily by N+ anode regions, can not only so reduce the OFF state loss of device can also greatly reduce the shut-off of device
Time.Meanwhile in order to control anode hole injection efficiency and adjust electric field distribution, usually all it can increase by one in the anode of IGBT
The higher N-buffer layers of doping concentration.
SA-LIGBT is primarily present two kinds of conduction modes during forward conduction：Monopolar mode and double pole mode.Work as SA-
When LIGBT is operated in monopolar mode, device is equivalent to a MOSFET at this time, and electronics comes from emission of cathode, by drift
Collected by N+ anode regions in area；Double pole mode is exactly normal IGBT patterns.Monopolar mode mode current very little, and conducting resistance
Greatly, it is often desirable that device is more early better into double i.e. patterns.But for traditional SA-IGBT, from monopolar mode to double
Snapback phenomenons occur in pole mode transition procedure kind, and snapback phenomenons can be more obvious under cryogenic, this can lead
Cause device can not be normally-open, seriously affect the stability of power electronic system.
The content of the invention
It is to be solved by this invention, aiming at the above problem, propose a kind of SA- that can effectively suppress snapback phenomenons
LIGBT。
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of SA-LIGBT, including N-type substrate 1, the dielectric layer 2 positioned at N-type substrate upper surface and positioned at 2 upper table of dielectric layer
The N-type drift region 3 in face；Described 3 upper strata one end of N-type drift region has P type trap zone 4, its other end has N-type well region 5, the P
There is spacing between type well region 4 and N-type well region 5；4 upper strata of P type trap zone has P+ body contact zones 8 and N+ cathodic regions 9, the P+
Body contact zone 8 and N+ cathodic regions 9 are set up in parallel along device horizontal direction, and N+ cathodic regions 9 are located at one close to N-type well region 5
Side；The surface of P type trap zone 4 between the N+ cathodic regions 9 and N-type drift region 3 has gate structure；It is characterized in that, the N
5 upper strata of type well region has P+ anode regions 10 and a N+ anode regions 11, and the P+ anode regions 10 and N+ anode regions 11 are along device transverse direction side
To arranged side by side；The P+ anode regions 10 arrange the P+ anode sub-districts being parallel to each other along device horizontal direction, each row P+ anodes including X
Area is segmentation structure along device longitudinal direction, the gap in each row P+ anode sub-districts between adjacent two sections of P+ anode sub-districts
It is corresponding with a segmentation of adjacent column P+ anode sub-districts along device horizontal direction, and each gap is along device longitudinal direction
Length is less than it and corresponds to the segmentation of P+ anodes sub-district along the length on device longitudinal direction；The N+ anode regions 11 are arranged along device including Y
The N+ anodes sub-district that part horizontal direction is parallel to each other is formed, and each row N+ anodes sub-district is segmented knot along device longitudinal direction
Structure, each row N+ anodes sub-district is along the corresponding row P+ anodes sub-district of device horizontal direction and positioned at the P+ anode sub-districts away from P
4 side of type well region；There is the first buried regions of p-type 7, upper surface and the P+ anode regions of first buried regions of p-type 7 in the N-type well region 5
10 lower surface contact.
There is the first buried regions of p-type 7 and M to arrange and are segmented along device longitudinal direction for the total technical solution of the present invention, the anode of device
P+ anode regions 10, when device forward conduction is in monopolar mode initial stage, they can increase the electronics into N-type well region 6
Flow path of the electric current before being collected by N+ anode regions 11, so as to increase P+ anode regions 10 and the first buried regions of p-type 7 under monopolar mode
The forward voltage drop of the PN junction formed with N-type well region 5 or N-type high resistance area 12, makes device just can be under less monopolar current
Enter double pole mode, so as to suppress the appearance of snapback phenomenons.
Further, X >=2, Y<X.
This programme is on the basis of preceding solution, proposes the columns that P+ anode regions 10 are divided along device horizontal direction
At least 2 row, while the columns that divide of N+ anode regions 11 is less than the columns of P+ anode regions 10.
Further, there is the second buried regions of p-type 6, the upper surface of second buried regions of p-type 6 and P+ in the P type trap zone 4
The lower surface contact of the lower surface and N+ cathodic regions 9 of body contact zone 8.
Further, first buried regions of p-type 7 is more than P+ anode regions 10 and N+ anode regions along the width of device horizontal direction
The sum of 11 width, and have gap between the border of side and N-type well region 5 away from 4 side of P type trap zone of the first buried regions of p-type 7.
Further, between the adjacent P+ anodes sub-district, there is N-type high resistance area 12 between adjacent N+ anodes sub-district.
Further, between the adjacent P+ anodes sub-district, between adjacent N+ anodes sub-district, the upper table of the first buried regions of p-type 7
Face and the first buried regions of p-type 7 and N-type well region 5 have N-type high resistance area 12 between the border away from 4 side of P type trap zone.
Beneficial effects of the present invention are that can effectively suppress snapback phenomenons, while the OFF state that can also lift device is special
Property and latch-up immunity.
Brief description of the drawings
Fig. 1 is traditional SA-LIGBT structure diagrams；
Fig. 2 is the structure diagram of embodiment 1；
Fig. 3 is the structure diagram of embodiment 2；
Fig. 4 is the structure diagram of embodiment 3；
Fig. 5 is the structure diagram of embodiment 4；
Fig. 6 is the structure diagram of embodiment 5；
Fig. 7 is the structure diagram of embodiment 6；
Fig. 8 is the structure diagram of embodiment 7；
Fig. 9 is the structure diagram of embodiment 8；
Figure 10 is the structure diagram of embodiment 9.
Embodiment
With reference to the accompanying drawings and examples, detailed description of the present invention technical solution：
X-axis direction in heretofore described device horizontal direction respective figure, z side in device longitudinal direction respective figure
To y directions in device vertical direction respective figure.
Embodiment 1：
As shown in Fig. 2, dielectric layer 2 including N-type substrate 1, positioned at N-type substrate upper surface and positioned at 2 upper surface of dielectric layer
N-type drift region 3；The 3 upper strata side of N-type drift region has P type trap zone 4, its opposite side has N-type well region 5；The p-type
4 upper strata of well region has P+ body contact zones 8 and a N+ cathodic regions 9, and the P+ body contact zones 8 and N+ cathodic regions 9 are along device horizontal direction
It is set up in parallel, and N+ cathodic regions 9 are located at close to the side of N-type well region 5；P-type between the N+ cathodic regions 9 and N-type drift region 3
The upper surface of well region 4 has gate structure；It is characterized in that, 5 upper strata of N-type well region has P+ anode regions 10 and N+ anode regions
11, the P+ anode regions 10 are located at close to the side of P type trap zone 4；The P+ anode regions 10 are for two array structures and horizontal along device
Direction is parallel to each other；There is p-type first between the bottom of the P+ anode regions 10 and the bottom of N+ anode regions 11 and N-type well region 5
Buried regions 7；The P+ anode regions 10 include two row, are respectively first row P+ anodes sub-district and secondary series P+ anode sub-districts；Described
Spacing between one row P+ anodes sub-district and secondary series P+ anode sub-districts is m；The first row P+ anodes sub-district is longitudinal along device
Direction is divided into three sections, is respectively first row first segment P+ anodes sub-district, first row second segment P+ anodes sub-district, the 3rd section of first row
P+ anode sub-districts, the first row first segment P+ anodes sub-district are located at the side of device, first row the 3rd along device longitudinal direction
Section P+ anodes sub-district is located at the opposite side of device along device longitudinal direction, and first row second segment P+ anodes sub-district is located at first row
Between the 3rd section of P+ anode sub-district of first segment P+ anodes sub-district and first row；First row first segment P+ anodes sub-district and first row the
Spacing between two sections of P+ anode sub-districts is a1, the 3rd section of P+ anodes sub-district of first row second segment P+ anodes sub-district and first row it
Between spacing be a1；The secondary series P+ anodes sub-district is divided into two sections along device longitudinal direction, is respectively secondary series first segment P+
Anode sub-district and secondary series second segment P+ anode sub-districts；The secondary series first segment P+ anodes sub-district and secondary series second segment P+ sun
Spacing between the sub-district of pole is a2；The secondary series first segment P+ anodes sub-district and secondary series second segment P+ anodes sub-district are along device
The length of longitudinal direction is more than a1, and secondary series first segment P+ anodes sub-district shelters from first row first segment along device horizontal direction
Gap between P+ anodes sub-district and first row second segment P+ anode sub-districts, secondary series second segment P+ anodes sub-district are horizontal along device
Direction shelters from the gap between the 3rd section of P+ anode sub-district of first row second segment P+ anodes sub-district and first row；The N+ anodes
Area 11 is divided into first segment N+ anodes sub-district and the 2nd N+ anode regions along device longitudinal direction；The first segment N+ anodes sub-district is along device
The length of part longitudinal direction is less than length of the secondary series first segment P+ anodes sub-district along device longitudinal direction, and first segment N+ anodes
Sub-district is located at the side of secondary series first segment P+ anode sub-districts；Length of the second segment N+ anodes sub-district along device longitudinal direction
Less than length of the secondary series second segment P+ anodes sub-district along device longitudinal direction, and second segment N+ anodes sub-district is located at secondary series
The side of two sections of P+ anode sub-districts；The side of the first segment N+ anode sub-districts connects with the side of secondary series first segment P+ anode sub-districts
Connect；The side of the second segment N+ anode sub-districts is connected with the side of secondary series second segment P+ anode sub-districts.
The operation principle of this example is：
Since the SA-LIGBT essential reasons for occurring snapback phenomenons during forward conduction are anode parasitism PN junctions
(PN junction that the P+ anode regions 10 in this programme are formed with N-type well region 5) is hardly turned under monopolar mode electric current.Therefore promote
This PN junction turns on as early as possible so that it is to solve break-over of device and snapback occur initial stage to show that device enters double pole mode earlier
The essential idea of elephant.This programme in anode region by adding one layer of p type buried layer 7 and M shows the P+ anode regions 10 of window very
Solves the problems, such as this well.
Device is at forward conduction initial stage, it works in monopolar mode i.e. LDMOS patterns, and cathode electronics launch at this time
Electronic current enters inside the higher N-type well region 5 of concentration by drift region, due to the presence of the first buried regions of p-type 7, forces electronics
Electric current can only flow to N+ anode regions 11 nearby and then by N+ by the gap in each section of P+ anodes subinterval in P+ anode regions 10
Collect anode region 11.However, formed since P+ anode regions 10 arrange the mutually non-conterminous P+ anode sub-districts for having gap by M, Er Qiexiang
There is no overlapping region (in the devices in the longitdinal cross-section diagram in portion, P+ anode regions are continuous) between adjacent two gaps, it is same with this
When only possible m column (being directed toward N-type well region 5 direction number from P type trap zone 4) the P+ anode regions 10 that are present in N+ anode regions 11 away from p-type
The non-sectional area of 4 side of well region.This allow for enter 10 overlap span of first row P+ anodes sub-district at electronic current by N
+ anode region 11 has to pass through one section of tortuous path before collecting, so as to increase electronic current in flow process in above-mentioned sun
The forward voltage drop produced on extremely parasitic PN junction, the rational gap width and row for adjusting P+ anode regions 10 on third dimension direction
Number M, it is possible to the appearance of complete suppression device conducting snapback phenomenons at initial stage.
Embodiment 2
As shown in figure 3, the structure of this example and embodiment is essentially identical, different places are, N+ anode regions 11 in this example
A row P+ anodes sub-district separation adjacent thereto.
This example is identical with the principle and beneficial effect of embodiment 1, but there is provided another implementation.
Embodiment 3
As shown in figure 4, the structure of this example and embodiment 2 is essentially identical, different places is, P+ anode regions 10 in this example
It is respectively first row P+ anodes sub-district, secondary series P+ anodes sub-district and the 3rd row P+ anode sub-districts including three row；The first row
Spacing between P+ anodes sub-district and secondary series P+ anode sub-districts is m1, the secondary series P+ anodes sub-district and the 3rd row P+ anodes
Spacing between sub-district is m2；The first row P+ anodes sub-district is divided into two sections along device longitudinal direction, is respectively first row the
One section of P+ anodes sub-district and first row second segment P+ anode sub-districts, the first row first segment P+ anodes sub-district is along device longitudinal direction side
It is located at the opposite side of device, first row along device longitudinal direction to positioned at the side of device, first row second segment P+ anodes sub-district
Spacing between first segment P+ anodes sub-district and first row second segment P+ anode sub-districts is a1；The 3rd row P+ anode sub-districts edge
Device longitudinal direction is divided into two sections, respectively the 3rd row first segment P+ anodes sub-district and the 3rd row second segment P+ anode sub-districts, institute
State the side that the 3rd row first segment P+ anodes sub-district is located at device along device longitudinal direction, the 3rd row second segment P+ anode sub-districts edge
Device longitudinal direction is located at the opposite side of device, the 3rd row first segment P+ anodes sub-district and the 3rd row second segment P+ anodes sub-district it
Between spacing be a1；The secondary series P+ anodes sub-district is located between first row P+ anodes sub-district and the 3rd row P+ anode sub-districts；
The secondary series P+ anodes sub-district is one section, its length is more than a1 but is less than device longitudinal length, secondary series P+ anodes
Between area is sheltered between first row first segment P+ anodes sub-district and first row second segment P+ anode sub-districts along device horizontal direction
Gap between gap and the 3rd row first segment P+ anodes sub-district and the 3rd row second segment P+ anode sub-districts；The secondary series P+ sun
There is first row N+ anode regions between pole sub-district and the 3rd row P+ anode sub-districts, the first row N+ anode regions are along device transverse direction side
Gap between the 3rd row first segment P+ anodes sub-district of face and the 3rd row second segment P+ anode sub-districts, and first row N+ anodes
Area is less than a1 along the length of device longitudinal direction；The side of the 3rd row P+ anodes sub-district away from first row N+ anode regions has
Secondary series N+ anode regions；The secondary series N+ anode regions 11 along device longitudinal direction be divided into secondary series first segment N+ anodes sub-district and
The 2nd N+ anode regions of secondary series；The secondary series first segment N+ anodes sub-district is located at the side of device, institute along device longitudinal direction
State the opposite side that secondary series second segment N+ anodes sub-district is located at device along device longitudinal direction；The secondary series first segment N+ anodes
Spacing between sub-district and secondary series second segment N+ anode sub-districts is b, and b ＞ a1.
The principle of this example and beneficial effect are same as Example 2, can also equally reach suppression device and turn on initial stage
The effect that snapback phenomenons occur.
Embodiment 4
As shown in figure 5, the present embodiment is identical with the basic structure of embodiment 1, difference lies in this example in 4 inside P of P type trap zone
+ body contact zone 8 and the lower section of N+ cathodic regions 9 introduce the second buried regions of p-type 6, and the buried regions is contacted with the two.
For this example in addition to possessing the beneficial effect shown in embodiment 1,4 internal current stream of P type trap zone can be prevented by also having
Pressure drop caused by dynamic causes P type trap zone 4 and the effect of the PN junction forward conduction of the composition of N+ cathodic regions 9, so as to suppress breech lock effect
The appearance answered.
Embodiment 5
As shown in fig. 6, the present embodiment and the structure of embodiment 4 are essentially identical, difference lies in p-type first in the present embodiment
Buried regions 7 is surrounded by N-type well region 5 completely, i.e. side of the first buried regions 7 away from 4 side of P type trap zone is between the side device edge
For N-type well region 5, the side and bottom surface and P+ anode regions disposed thereon and N+ anode regions side that is to say the first buried regions 7 are N
Type well region 5, the side away from P type trap zone 4 are no longer the edges of device.This structure of this example is special compared to the above embodiments
Sign is the N-type well region 4 between the edge of side and device of the first buried regions of p-type 7 away from 4 side of P type trap zone, has power supply subflow
The N-type well region of the part, in narration below, is defined as the window (or referred to as window) of supplied for electronic flowing by dynamic characteristic
To facilitate description.
Due in device in forward conduction preliminary work in monopolar mode when, the electronics that emission of cathode comes enters anode N
N+ anode regions 11 can not only be flow to behind 5 inside of type well region by the gap in P+ anodes subinterval nearby to receive and then N+ anodes 11
Collection, also can enter its upside by the window in P buried regions 7 so as to be collected by N+ anode regions 11., can be with by optimised devices parameter
So that PN junction 1 and p-type first that device is made of when monopolar mode changes to double pole mode P+ anode regions 10 and N-type well region 5
The PN junction 2 while forward conduction that buried regions 7 is formed with N-type well region, can not only suppress snapback phenomenons, while can also improve at this time
The efficiency and then the OFF state characteristic of raising device that electronics extracts during OFF state.
Embodiment 6
Such as Fig. 7, the structure of the structure and embodiment 4 of this example is essentially identical, and difference lies in the present embodiment in N-type well region 5
The gap location in the first row P+ anodes subinterval of the top of the first buried regions of portion's p-type 7 and its sun of non-P+ away from 4 side of P type trap zone
It is N-type high resistance area 12 at polar region 10 and N+ anode regions 11.The N-type high resistance area occurred in this example and later embodiment, refers in original
Implanting p-type impurity is compensated in the N-type well region come, becomes N-type high resistance area.
Distributed resistance bigger when make it that electronic current flows in N-type high resistance area due to the presence of N-type high resistance area 12, from
And by the PN junction 3 that P+ anode regions 10 and N-type high resistance area 12 are formed compared in Examples 1 and 2 by P+ anode regions 10 and N-type trap
The PN junction 1 that area 5 is formed is easier forward conduction, so the program preferably can turn on snapback phenomenons at initial stage by suppression device
Appearance.
Embodiment 7
As shown in figure 8, the structure of this example and the structure of embodiment 3 are essentially identical, difference lies in N-type trap in the present embodiment
The gap location in the first row P+ anodes subinterval of the top of 5 the first buried regions of inside p-type of area 7 and its away from the non-of 4 side of P type trap zone
It is N-type high resistance area 12 at P+ anode regions 10 and N+ anode regions 11.
The working principle and beneficial effect of this example is same as Example 6.
As the simple deformation of the embodiment, as shown in Figures 9 and 10, when first buried regions of p-type 7 is away from p-type trap
Then also it is N-type high resistance area at window when there is the window that supplied for electronic flows in 4 side of area.At this time, it is high by the first buried regions of p-type 7 and N-type
The PN junction 4 that resistance area is formed similarly is easier the forward conduction under relatively low monopolar current, so that easily optimised devices knot
Structure parameter causes the OFF state efficiency that device can also be improved while can suppress snapback phenomenons.
To sum up, on the one hand a kind of SOI SA-LIGBT devices that present invention speed provides inhibit SA-LIGBT in forward conduction
Snapback phenomenons present in initial stage, this is primarily due to the first buried regions of p-type 7 and M shows the P+ anode sub-districts in gap and deposits
Forcing the flow direction of electronic current to change, considerably improving in electronics flowing flow process in anode parasitism PN junction
The pressure drop of upper generation；On the other hand, since the presence of the second buried regions of p-type 6 inside P type trap zone 4 make it that the anti-breech lock of device is special
Ability significantly increases；Simultaneously as device of the present invention can also pass through window on the first buried regions of p-type 7 in anode region
Mouth is collected by N+ anode regions 11, so as to improve the OFF state efficiency of device in original basis.
Claims (8)
1. a kind of SA-LIGBT, including N-type substrate (1), the dielectric layer (2) positioned at N-type substrate upper surface and positioned at dielectric layer (2)
The N-type drift region (3) of upper surface；Described N-type drift region (3) upper strata one end has P type trap zone (4), its other end has N-type trap
, there is spacing in area (5) between the P type trap zone (4) and N-type well region (5)；P type trap zone (4) upper strata has P+ body contact zones
(8) it is set up in parallel with N+ cathodic regions (9), the P+ body contact zones (8) and N+ cathodic regions (9) along device horizontal direction, and N+ is cloudy
Polar region (9) is located at close to the side of N-type well region (5)；P type trap zone (4) between the N+ cathodic regions (9) and N-type drift region (3)
Surface there is gate structure；It is characterized in that, N-type well region (5) upper strata has P+ anode regions (10) and N+ anode regions
(11), the P+ anode regions (10) and N+ anode regions (11) are arranged side by side along device horizontal direction；The P+ anode regions (10) arrange including X
The P+ anode sub-districts being parallel to each other along device horizontal direction, each row P+ anodes sub-district are segmented knot along device longitudinal direction
Structure, gap in each row P+ anode sub-districts between adjacent two sections of P+ anode sub-districts along device horizontal direction with adjacent column P+ sun
One segmentation of pole sub-district corresponds to, and each gap is less than it along the length on device longitudinal direction and corresponds to the segmentation of P+ anodes sub-district
Length along on device longitudinal direction；The N+ anode regions (11) arrange the N+ anodes being parallel to each other along device horizontal direction including Y
Sub-district is formed, and each row N+ anodes sub-district is segmentation structure along device longitudinal direction, and each row N+ anodes sub-district is horizontal along device
To the corresponding row P+ anodes sub-district in direction and positioned at the P+ anodes sub-district away from P type trap zone (4) side；The N-type well region (5)
In there is the first buried regions of p-type (7), the upper surface of first buried regions of p-type (7) is contacted with the lower surface of P+ anode regions (10), institute
Device longitudinal direction is stated as direction vertical with device horizontal direction in the horizontal plane.
2. a kind of SA-LIGBT according to claim 1, it is characterised in that X >=2, Y<X.
3. a kind of SA-LIGBT according to claim 2, it is characterised in that there is p-type second in the P type trap zone (4)
Under buried regions (6), the upper surface of second buried regions of p-type (6) and the lower surface of P+ body contact zones (8) and N+ cathodic regions (9)
Surface contacts.
4. a kind of SA-LIGBT according to claim 2, it is characterised in that first buried regions of p-type (7) is horizontal along device
The width in direction is more than the sum of the width of P+ anode regions (10) and N+ anode regions (11), and the side of the first buried regions of p-type (7) and N
Type well region (5) has gap between the border away from P type trap zone (4) side.
5. a kind of SA-LIGBT according to claim 3, it is characterised in that first buried regions of p-type (7) is horizontal along device
The width in direction is more than the sum of the width of P+ anode regions (10) and N+ anode regions (11), and the side of the first buried regions of p-type (7) and N
Type well region (5) has gap between the border away from P type trap zone (4) side.
6. a kind of SA-LIGBT according to claim 3, it is characterised in that between the adjacent P+ anodes sub-district, adjacent N
There are N-type high resistance area (12) between+anode sub-district.
7. a kind of SA-LIGBT according to claim 4, it is characterised in that between the adjacent P+ anodes sub-district, adjacent N
Between+anode sub-district, the upper surface of the first buried regions of p-type (7) and the first buried regions of p-type (7) with N-type well region (5) away from P type trap zone
(4) there are N-type high resistance area (12) between the border of side.
8. a kind of SA-LIGBT according to claim 5, it is characterised in that between the adjacent P+ anodes sub-district, adjacent N
Between+anode sub-district, the upper surface of the first buried regions of p-type (7) and the first buried regions of p-type (7) with N-type well region (5) away from P type trap zone
(4) there are N-type high resistance area (12) between the border of side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510936970.7A CN105552109B (en) | 2015-12-15 | 2015-12-15 | A kind of short circuit anode landscape insulation bar double-pole-type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510936970.7A CN105552109B (en) | 2015-12-15 | 2015-12-15 | A kind of short circuit anode landscape insulation bar double-pole-type transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105552109A CN105552109A (en) | 2016-05-04 |
| CN105552109B true CN105552109B (en) | 2018-04-13 |
Family
ID=55831192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510936970.7A Active CN105552109B (en) | 2015-12-15 | 2015-12-15 | A kind of short circuit anode landscape insulation bar double-pole-type transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105552109B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170802B (en) * | 2017-06-07 | 2020-01-17 | 电子科技大学 | Short-circuit anode SOI LIGBT |
| CN110504307B (en) * | 2019-08-28 | 2023-03-14 | 重庆邮电大学 | SA-LIGBT device with grid-controlled collector |
| CN110571264B (en) * | 2019-09-17 | 2023-03-24 | 重庆邮电大学 | SA-LIGBT device with multichannel current bolt |
| CN113793804B (en) * | 2021-11-15 | 2022-02-22 | 微龛(广州)半导体有限公司 | Transverse insulated gate bipolar transistor structure and preparation method thereof |
| CN114220848B (en) * | 2022-02-22 | 2022-05-10 | 浙江大学 | Floating island device capable of being rapidly opened and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773852A (en) * | 1996-03-20 | 1998-06-30 | Korea Electronics Co., Ltd. | Shorted anode lateral insulated gate bipolar transistor |
| TW200525756A (en) * | 2004-01-20 | 2005-08-01 | Univ Nat Chiao Tung | Structure for lateral insulated-gate bipolar transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8937502B2 (en) * | 2013-02-27 | 2015-01-20 | Pakal Technologies Llc | Lateral insulated gate turn-off devices |
| US9070735B2 (en) * | 2013-07-02 | 2015-06-30 | Cambridge Microelectronics Ltd. | Lateral power semiconductor transistors |
-
2015
- 2015-12-15 CN CN201510936970.7A patent/CN105552109B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773852A (en) * | 1996-03-20 | 1998-06-30 | Korea Electronics Co., Ltd. | Shorted anode lateral insulated gate bipolar transistor |
| TW200525756A (en) * | 2004-01-20 | 2005-08-01 | Univ Nat Chiao Tung | Structure for lateral insulated-gate bipolar transistor |
Non-Patent Citations (1)
| Title |
|---|
| A 800 V dual conduction paths segmented anode LIGBT with low specific on-resistance and small shift voltage;Mao Kun et al;《Journal of Semiconductors》;20140531;第35卷(第5期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105552109A (en) | 2016-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105552109B (en) | A kind of short circuit anode landscape insulation bar double-pole-type transistor | |
| CN103890955B (en) | Semiconductor devices | |
| CN102148240B (en) | SOI-LIGBT (silicon on insulator-lateral insulated gate bipolar transistor) device with split anode structure | |
| CN108389900A (en) | A kind of slot grid short circuit anode SOI LIGBT | |
| CN102169892B (en) | Enhancement mode planar insulated gate bipolar transistor (IGBT) | |
| CN103219370A (en) | Reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with P floating layer current bolt | |
| CN107710409A (en) | Semiconductor device | |
| CN105185826A (en) | Transverse RC-IGBT device | |
| CN108321194A (en) | A kind of SOI LIGBT with rapid turn off characteristic | |
| CN103762230B (en) | N-channel injection efficiency reinforced insulation grid bipolar transistor | |
| CN110473917B (en) | Transverse IGBT and manufacturing method thereof | |
| CN105023943A (en) | Longitudinal RC-IGBT device | |
| CN104393056B (en) | Accumulating diode | |
| CN102446966A (en) | IGBT ((Insulated Gate Bipolar Transistor) structure of integrated anti-parallel diode and manufacturing method thereof | |
| CN104779279B (en) | It is a kind of to suppress the RC IGBT of negative resistance effect | |
| CN106252399A (en) | A kind of inverse conductivity type IGBT | |
| CN104795438B (en) | It is a kind of to suppress the SA LIGBT of negative resistance effect | |
| CN104393055B (en) | A kind of groove-shaped diode with chinampa structure | |
| CN106057879A (en) | IGBT device and manufacturing method therefor | |
| CN104078498B (en) | A kind of trench isolations landscape insulation bar double-pole-type transistor | |
| CN106298901A (en) | A kind of landscape insulation bar double-pole-type transistor of high hot carrier reliability | |
| CN106992208A (en) | A kind of thin silicone layer SOI bases landscape insulation bar double-pole-type transistor and its manufacture method | |
| CN103887332A (en) | Novel power semiconductor device | |
| CN103779404B (en) | P Channeling implantation enhanced efficiency insulated gate bipolar transistor | |
| CN103928507A (en) | Reverse-conducting double-insulated-gate bipolar transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |