CN103956377A - GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure - Google Patents
GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure Download PDFInfo
- Publication number
- CN103956377A CN103956377A CN201410152021.5A CN201410152021A CN103956377A CN 103956377 A CN103956377 A CN 103956377A CN 201410152021 A CN201410152021 A CN 201410152021A CN 103956377 A CN103956377 A CN 103956377A
- Authority
- CN
- China
- Prior art keywords
- layer
- resistivity
- type
- silicon substrate
- lower floor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 62
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
- 239000010703 silicon Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 229920005591 polysilicon Polymers 0.000 claims description 67
- 230000015572 biosynthetic process Effects 0.000 claims description 37
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 239000002019 doping agent Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 5
- 230000035939 shock Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 119
- 230000015556 catabolic process Effects 0.000 description 59
- 239000002355 dual-layer Substances 0.000 description 58
- 239000012535 impurity Substances 0.000 description 23
- 229910052782 aluminium Inorganic materials 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 17
- 238000005036 potential barrier Methods 0.000 description 15
- 239000004411 aluminium Substances 0.000 description 13
- 238000003475 lamination Methods 0.000 description 11
- 238000012546 transfer Methods 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000008602 contraction Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000005619 thermoelectricity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
The invention relates to a GAT of a double-high-resistance-layer groove shape gate polycrystalline silicon structure. The upper surface of a silicon substrate sheet with a lower N+ type low-resistivity layer and an upper N type high-resistivity layer is provided with a plurality of N+ type high-dosage concentration emitter regions, and the upper faces of the emitter regions are connected with an N+ type doped polycrystalline silicon layer. The GAT is characterized in that the N type high-resistivity layer of the silicon substrate sheet is divided into an upper layer and a lower layer, the resistivity of the upper layer of the N type high-resistivity layer is higher than that of the lower layer of the N type high-resistivity layer, the resistivity of the lower layer ranges from 2 ohm cm to 9 ohm cm, and the thickness of the lower layer ranges from 13 microns to 40 microns. The GAT has the advantages that a lower tube core can have high power, the shock resistance capacity is high, and the GAT has the effects of high cost performance and high reliability.
Description
Technical field
The present invention relates to the gate associated transistor of a kind of pair of resistive formation grooved gate polysilicon structure, belong to silicon semiconductor device technical field.
Background technology
The gate associated transistor of relevant grooved gate polysilicon structure, at Chinese invention patent application Publication Specification publication number, be that the basic structure explained during CN101527317A name is called the gate associated transistor > > of < < grooved gate polysilicon structure is as follows: Qi lower floor is the first conduction type low-resistivity layer, upper strata is the emitter region that the upper surface of the silicon substrate film of the first conduction type high resistivity layer has the high-dopant concentration of many first conduction types, the doped polysilicon layer that is connecting the first conduction type above emitter region, this doped polysilicon layer is connected with emitter metal layer, there is the base of the second conduction type in the surrounding of every emitter region, the side of the base doping content of ining succession is higher than base, the flute profile grid region of the second conduction type that the depth ratio base degree of depth is dark, bottom surface and the side of every groove are covered with insulating barrier, side insulation layer extends to the upper surface of silicon substrate film, grid region is connected with gate metal layer, the upper strata of silicon substrate film is positioned at below base and the part below grid region is collector region, the lower floor of silicon substrate film is collector electrode, the lower surface of collector electrode is connected with collector electrode metal layer.
Fig. 4 of this patent of invention specification is that the first conduction type high resistivity layer upper strata of silicon substrate film is the structure chart of double-deck embodiment.It is N-type that this embodiment gets the first conduction type, and the second conduction type is P type.The upper strata N-type resistive formation 41 of the silicon substrate film of this embodiment is divided into two-layer, and the resistivity of top one deck 411 is high, is 60 Ω cm, and thickness is 20 μ m, and the resistivity of face one deck 412 is lower on the lower, is 20 Ω cm, and thickness is 40 μ m.The specification explanation of this patent of invention, this double-deck resistive formation, can effectively suppress PN junction potential barrier between collector electrode and base stage in the transfer blockage effect of large electric current, improve the avalanche resistance breakdown capability of device, thereby improve the reliability of long term device work.
But the specifications parameter of this double-deck resistive formation (resistive formation is high resistivity layer) is good not, the transfer blockage effect of the PN junction potential barrier between its inhibition base stage and collector electrode under large electric current is strong not with the avalanche resistance breakdown capability of raising device.
It is N-type that the gate associated transistor of grooved gate polysilicon structure generally adopts the first conduction type, and the second conduction type is P type.The main failure mechanism of the gate associated transistor of grooved gate polysilicon structure is second breakdown, and second breakdown is that thermoelectricity punctures, and existing thermal breakdown mechanism, also has electrical breakdown mechanism.The gate associated transistor of grooved gate polysilicon structure is the actual second breakdown the occurring result that thermal breakdown and two kinds of machine-processed actings in conjunction of electrical breakdown are strengthened mutually often in switch application.Wherein, thermal breakdown mechanism refers in tube core, and due to the inhomogeneous part " focus " of causing of CURRENT DISTRIBUTION, focus place electric current increases, and cause local temperature higher, and then electric current is larger, so moves in circles.When heat radiation, be unable to catch up with adstante febre, local temperature is more and more higher, finally burns.Electrical breakdown mechanism refers to that the PN junction potential barrier between base stage and collector electrode is that collector junction potential barrier to the upper strata of silicon substrate film and the intersection of lower floor, contraction occurs to shift under the large function of current.Along with the increase of electric current, the contraction of collector junction potential barrier strengthens, and collector junction barrier width reduces, and the maximum electric field in collector junction barrier region constantly increases, and avalanche breakdown occurs when maximum electric field reaches capacity electric field.Avalanche breakdown causes electric current further to increase, and electric current increase causes potential barrier further to be shunk, and moves in circles, and presents negative resistance charactertistic.So this avalanche breakdown is called negative resistance second breakdown, also referred to as snowslide second breakdown.Collector junction barrier width while there is snowslide second breakdown is exactly the distance between the Yu Xia interface, upper interface of the collector junction potential barrier while just there is snowslide second breakdown.Electric current between collector electrode and emitter mainly passes through from the intersection of base and collector region, and the current ratio of passing through from the intersection of grid region and collector region is less, it be from the intersection of base and collector region toward the upper strata of silicon substrate film and the intersection of lower floor transfer contraction that main manifestations is shunk in the transfer of collector junction potential barrier.The lower floor of silicon substrate film is N
+type low-resistivity layer, collector junction potential barrier can not be extended toward the lower floor of silicon substrate film, and the lower interface of collector junction potential barrier terminates in the upper strata of silicon substrate film and the intersection of lower floor.Collector region reduced width while therefore, there is snowslide second breakdown be exactly intersection from base and the collector region collector junction potential barrier during to generation snowslide second breakdown the distance at interface.According to the mechanism of snowslide second breakdown, the ability of the avalanche resistance second breakdown of the gate associated transistor of grooved gate polysilicon structure depends on the donor impurity total amount M of the unit are in reduced width region, collector region while there is snowslide second breakdown.The donor impurity total amount M of the unit are when upper strata of silicon substrate film is the gate associated transistor generation snowslide second breakdown of grooved gate polysilicon structure of dual-layer high-resistance layer in reduced width region, collector region is determined by formula (1).
M=(W1-Xb)×Nd1+(W2-D)×Nd2 (1)
Wherein, W1 is the thickness on the upper strata of resistive formation, Xb is base and collector region intersection is base junction depth to the distance of the upper surface of silicon substrate, Nd1 is the donor impurity concentration on the upper strata of resistive formation, W2 is the thickness of the lower floor of resistive formation, D is the collector junction barrier width while there is snowslide second breakdown, and Nd2 is the donor impurity concentration of the lower floor of resistive formation.
Setting base junction depth is 4 μ m.
Collector junction barrier width D while there is snowslide second breakdown is determined by formula (2):
BV=D×EmB／2 (2)
Wherein, EmB is the limit electric field of collector junction barrier region generation avalanche breakdown, one get～4E5V/cm, and BV is the voltage between collector electrode and emitter while there is snowslide second breakdown.
The gate associated transistor of grooved gate polysilicon structure is mainly used in the switch in middle pressure field, is applied to electronic equipment and the device of 110VAC and 220VAC.110VAC and 220VAC are the civilian alternating voltages that most of areas are used in the world.Consider that supply voltage has 20% the factors such as fluctuation range, the collector electrode and the ceiling voltage between emitter that at 110V alternating voltage and 220V alternating voltage, after rectifying and wave-filtering, are added to the gate associated transistor of grooved gate polysilicon structure are estimated according to 200V and 400V respectively.
The gate associated transistor collector electrode of the grooved gate polysilicon structure from actual measurement electronic equipment and the voltage waveform between emitter and current waveform can be seen, in the moment that is forwarded to OFF state by ON state, it is shutdown moment, voltage waveform and current waveform have larger overlapping, at voltage corresponding to overlapping part current peak, are about 1/3 of ceiling voltage between collector electrode and emitter.When the voltage between collector electrode and emitter be raised to ceiling voltage 1/2 time, electric current has fallen lowlyer.Therefore, the voltage between collector electrode and emitter is in below 1/2 of ceiling voltage, and because electric current is less, the transfer blockage effect of collector junction potential barrier is not serious, snowslide second breakdown can not occur.Collector electrode and the voltage between emitter during below generation snowslide second breakdown are set as 1/2 of its ceiling voltage, the collector junction barrier width D while there is snowslide second breakdown in order to estimation.Adopt 110VAC power supply, the collector electrode of the gate associated transistor of grooved gate polysilicon structure and the ceiling voltage 200V between emitter, the voltage BV while there is snowslide second breakdown between collector electrode and emitter is 100V.By formula (2), calculated: the collector junction barrier width D=5 μ m while there is snowslide second breakdown.Adopt 220VAC power supply, the collector electrode of the gate associated transistor of grooved gate polysilicon structure and the ceiling voltage between emitter are 400V, and the voltage while there is snowslide second breakdown between collector electrode and emitter is 200V.By formula (2), calculated: the collector junction barrier width D=10 μ m while there is snowslide second breakdown.
The substrate upper strata of the gate associated transistor of grooved gate polysilicon structure adopts double-deck high resistivity layer can take into account anti-first breakdown and anti-second breakdown.The resistivity on the upper strata of dual-layer high-resistance layer is than lower floor height, so that the BVcbo of gate associated transistor reaches the requirement of resisting first breakdown.The resistivity of N-type silicon materials is lower, and donor impurity concentration is just higher.The resistivity of the lower floor of dual-layer high-resistance layer is lower, and its donor impurity concentration is just higher.The thickness that mates again the lower floor of suitable dual-layer high-resistance layer, just can more effectively suppress the transfer of collector junction potential barrier under large electric current shrinks, large current characteristic be can also take into account, the anti-motor system of gate associated transistor of grooved gate polysilicon structure and the ability of the second breakdown that heat engine making is sent out improved significantly.As the transistor that is applied to middle pressure field switch, resistivity and the thickness of the lower floor that depends on dual-layer high-resistance layer that the reliability of the gate associated transistor of grooved gate polysilicon structure is strong, therefore, the resistivity of the lower floor of the dual-layer high-resistance layer of the substrate of the gate associated transistor of grooved gate polysilicon structure and thickness are optimized to design very important.
Below, the anti-second breakdown ability of the gate associated transistor of grooved gate polysilicon structure that carrys out more several dual-layer high-resistance layers by calculating in the switching circuit application that adopts 110VAC power supply or 220VAC power supply.
The first dual-layer high-resistance layer: the resistivity 60 Ω cm on the upper strata of resistive formation, thickness 20 μ m, the resistivity 20 Ω cm of the lower floor of resistive formation, thickness is 40 μ m.This is the dual-layer high-resistance layer structure of prior art.
The second dual-layer high-resistance layer: the resistivity 20 Ω cm on the upper strata of resistive formation, thickness 27 μ m, the resistivity 2 Ω cm of the lower floor of resistive formation, thickness is 13 μ m.
The third dual-layer high-resistance layer: the resistivity 30 Ω cm on the upper strata of resistive formation, thickness 20 μ m, the resistivity 6 Ω cm of the lower floor of resistive formation, thickness is 40 μ m.
The 4th kind of dual-layer high-resistance layer: the resistivity 30 Ω cm on the upper strata of resistive formation, thickness 20 μ m, the resistivity 9 Ω cm of the lower floor of resistive formation, thickness is 40 μ m.
The resistivity of silicon substrate and impurity concentration have definite relation, by technical literature, can find: resistivity is that the donor impurity concentration of the N-type silicon of 2 Ω cm is 2.6E15/cm
3, resistivity is that the donor impurity concentration of the N-type silicon of 6 Ω cm is 7.0E14/cm
3, resistivity is that the donor impurity concentration of the N-type silicon of 9 Ω cm is 4.7E14/cm
3, resistivity is that the donor impurity concentration of the N-type silicon of 20 Ω cm is 2.3E14/cm
3, resistivity is that the donor impurity concentration of the N-type silicon of 30 Ω cm is 1.7E14/cm
3, resistivity is that the donor impurity concentration of the N-type silicon of 60 Ω cm is 7.5E13/cm
3.
According to above data and formula (1), do lower column count:
The first dual-layer high-resistance layer be the gate associated transistor of grooved gate polysilicon structure of the dual-layer high-resistance layer of prior art while there is snowslide second breakdown in the switch application of 110VAC in reduced width region, collector region the donor impurity total amount M of unit are be
(20-4)μm×7.5E13／cm
3+(40-5)μm×2.3E14／cm
3=9.25E11／cm
2
When the gate associated transistor of the grooved gate polysilicon structure of the second dual-layer high-resistance layer, in the switch application of 110VAC, snowslide second breakdown occurs, in reduced width region, collector region, the donor impurity total amount M of unit are is
(27-4)μm×2.3E14／cm
3+(13-5)μm×2.6E15／cm
3=2.609E12／cm
2
When the gate associated transistor of the grooved gate polysilicon structure of the second dual-layer high-resistance layer, in the switch application of 110VAC, snowslide second breakdown occurs, in reduced width region, collector region, the donor impurity total amount M of unit are is 2.8 times of the first.So, the gate associated transistor of the grooved gate polysilicon structure of the second dual-layer high-resistance layer than the gate associated transistor of the grooved gate polysilicon structure of the dual-layer high-resistance layer of prior art the avalanche resistance second breakdown ability in the switch application of 110VAC much better than.The second dual-layer high-resistance layer gross thickness 40 μ m, and the gross thickness 60 μ m of the first dual-layer high-resistance layer.The gross thickness of resistive formation is thinner, and the collector region of the gate associated transistor of grooved gate polysilicon structure is just thinner, and its maximum current Icm is just larger.And Icm is larger, the second breakdown ability that the gate associated transistor heat resistanceheat resistant of grooved gate polysilicon structure mechanism causes is just stronger.So, the gate associated transistor of the grooved gate polysilicon structure of the second dual-layer high-resistance layer than the gate associated transistor of the grooved gate polysilicon structure of the dual-layer high-resistance layer of prior art the heat resistanceheat resistant in the switch application of 110VAC to puncture the second breakdown ability that mechanism causes stronger.
The resistivity of the lower floor of dual-layer high-resistance layer neither be more low better, and the resistivity of silicon materials is lower, and the ceiling voltage that can bear is lower.The N-type silicon materials of resistivity 2 Ω cm can bear ceiling voltage be 145V.Consider that various inhomogeneities are as the inhomogeneities of silicon materials doping, inhomogeneities of electric current etc. in the inhomogeneities of processes and tube core, all can affect the voltage of actual generation snowslide second breakdown.The voltage that snowslide second breakdown occurs aforementioned estimation in the switch application of 110VAC is 100V, actual choose that silicon materials can bear ceiling voltage to reserve surplus, so the resistivity of the lower floor of dual-layer high-resistance layer should not be lower than 2 Ω cm.In addition, the thickness of the lower floor of dual-layer high-resistance layer should not be lower than 13 μ m.Adopt 110VAC power supply, the collector junction barrier width D while there is snowslide second breakdown has reached 5 μ m.When high resistant lower thickness 13 μ m, the width that high resistant lower floor opposing collector junction potential barrier is shunk only has 8 μ m.Consider various inhomogeneities, the anti-allowance for shrinkage of above-mentioned 8 μ m is to have reduced again.
The avalanche resistance second breakdown ability of the gate associated transistor of the grooved gate polysilicon structure of comparison the first and the third the 4th kind of dual-layer high-resistance layer in 220VAC switch application.
The first dual-layer high-resistance layer be the gate associated transistor of grooved gate polysilicon structure of the dual-layer high-resistance layer of prior art while there is snowslide second breakdown in the switch application of 220VAC in reduced width region, collector region the donor impurity total amount M of unit are be
(20-4)μm×7.5E13／cm
3+(40-10)μm×2.3E14／cm
3=8.1E11／cm
2
When the gate associated transistor of the grooved gate polysilicon structure of the third dual-layer high-resistance layer, in the switch application of 220VAC, snowslide second breakdown occurs, in reduced width region, collector region, the donor impurity total amount M of unit are is
(20-4)μm×1.7E14／cm
3+(40-10)μm×7.0E14／cm
3=2.372E12／cm
2
When the gate associated transistor of the grooved gate polysilicon structure of the 4th kind of dual-layer high-resistance layer, in the switch application of 220VAC, snowslide second breakdown occurs, in reduced width region, collector region, the donor impurity total amount M of unit are is
(20-4)μm×1.7E14／cm
3+(40-10)μm×4.7E14／cm
3=1.682E12／cm
2
When the gate associated transistor of the grooved gate polysilicon structure of the third the 4th kind of dual-layer high-resistance layer, in the switch application of 220VAC, snowslide second breakdown occurs, in reduced width region, collector region, the donor impurity total amount M of unit are is respectively 2.9 times and 2.1 times of the first, so, the gate associated transistor of the grooved gate polysilicon structure of the third the 4th kind of dual-layer high-resistance layer than the gate associated transistor of the grooved gate polysilicon structure of the dual-layer high-resistance layer structure of prior art the avalanche resistance second breakdown ability in the switch application of 220VAC much better than.
The resistivity of the lower floor of dual-layer high-resistance layer should not exceed 9 Ω cm, and the resistivity of lower floor is higher, and donor impurity concentration is lower, and it is more weak that anti-collector junction potential barrier shifts contractility.The thickness of the lower floor of dual-layer high-resistance layer should not be greater than 40 μ m, and lower floor is too thick can reduce maximum current Icm, and the second breakdown ability that makes gate associated transistor heat resistanceheat resistant puncture mechanism initiation weakens.
From another perspective, while there is snowslide second breakdown, in reduced width region, collector region, the donor impurity total amount M of unit are is higher, with regard to more resisting larger rush of current, snowslide second breakdown does not occur.Therefore, the gate associated transistor of the grooved gate polysilicon structure of the second dual-layer high-resistance layer can be done larger power than the gate associated transistor of the grooved gate polysilicon structure of the dual-layer high-resistance layer of prior art in the switch application of 110VAC.The gate associated transistor of the grooved gate polysilicon structure of the third the 4th kind of dual-layer high-resistance layer can be done larger power than the gate associated transistor of the grooved gate polysilicon structure of the dual-layer high-resistance layer of prior art in the switch application of 220VAC.
Summary of the invention
In view of above-mentioned, the object of the invention is to be for the deficiencies in the prior art, a kind of gate associated transistor of new two resistive formation grooved gate polysilicon structures is provided, and it can strengthen avalanche resistance second breakdown ability, increases the power of device, improves the reliability of device.
For completing object of the present invention, the technical scheme that the present invention takes is:
A gate associated transistor for pair resistive formation grooved gate polysilicon structure, Qi lower floor is N
+type low-resistivity layer, upper strata are that the upper surface of the silicon substrate film of N-type high resistivity layer has a plurality of N
+the emitter region of the high-dopant concentration of type, is connecting N above this emitter region
+the doped polysilicon layer of type, this doped polysilicon layer is connected with emitter metal layer, and there is the base of P type in the surrounding of each emitter region, and ining succession below the side of base, doping content is higher than base, the dark P of the depth ratio base degree of depth
+the flute profile grid region of type, the bottom surface of every groove in flute profile grid region and side are all covered with insulating barrier, grid region is connected with gate metal layer, the upper strata of silicon substrate film is positioned at below base and the part below grid region is collector region, the lower floor of silicon substrate film is collector electrode, the lower surface of collector electrode is connected with collector electrode metal layer, it is characterized in that:
The N-type high resistivity layer of described silicon substrate film is divided into two-layer up and down, and the resistivity on the upper strata of N-type high resistivity layer is higher than the resistivity of the lower floor of N-type high resistivity layer;
The resistivity of the lower floor of the N-type high resistivity layer of described silicon substrate film is 2-9 Ω cm;
The thickness of the lower floor of the N-type high resistivity layer of described silicon substrate film is 13-40 μ m.
In addition,
Described two adjacent flute profile grid regions are overlapping mutually.
The side insulation layer of described every groove extends to the upper surface of silicon substrate film.
The top of the side insulation layer of described every groove is in groove.
Compared with prior art, the invention has the beneficial effects as follows: can do higher power with less tube core, strong shock resistance, has the effect of high performance-price ratio and high reliability.
Accompanying drawing explanation:
Fig. 1 is the structural representation of one embodiment of the present of invention, and the side insulation layer of every groove of this embodiment extends to the upper surface of silicon substrate film.
Fig. 2 is the structural representation of an alternative embodiment of the invention, and two adjacent flute profile grid regions of this embodiment are overlapping mutually.
Fig. 3 is the structural representation of another embodiment of the present invention, and the top of the side insulation layer of every groove of this embodiment is in groove, equal with the top of groove.
Fig. 4 is the structural representation of another embodiment of the present invention, and the top of the side insulation layer of every groove of this embodiment is in groove, and the top of side insulation layer is lower than the top of groove.
Embodiment:
The present invention relates to the gate associated transistor of a kind of pair of resistive formation grooved gate polysilicon structure, Qi lower floor is N
+type low-resistivity layer, upper strata are that the upper surface of the silicon substrate film of N-type high resistivity layer has a plurality of N
+the emitter region of the high-dopant concentration of type, is connecting N above this emitter region
+the doped polysilicon layer of type, this doped polysilicon layer is connected with emitter metal layer, and there is the base of P type in the surrounding of each emitter region, and ining succession below the side of base, doping content is higher than base, the dark P of the depth ratio base degree of depth
+the flute profile grid region of type, the bottom surface of every groove in flute profile grid region and side are all covered with insulating barrier, grid region is connected with gate metal layer, the upper strata of silicon substrate film is positioned at below base and the part below grid region is collector region, the lower floor of silicon substrate film is collector electrode, and the lower surface of collector electrode is connected with collector electrode metal layer.Wherein:
The N-type high resistivity layer of described silicon substrate film is divided into two-layer up and down, and the resistivity on the upper strata of N-type high resistivity layer is higher than the resistivity of the lower floor of N-type high resistivity layer;
The resistivity of the lower floor of the N-type high resistivity layer of described silicon substrate film is 2-9 Ω cm;
The thickness of the lower floor of the N-type high resistivity layer of described silicon substrate film is 13-40 μ m.
Described two adjacent flute profile grid regions are overlapping mutually.
The side insulation layer of described every groove extends to the upper surface of silicon substrate film.
The top of the side insulation layer of described every groove is in groove.
Below in conjunction with accompanying drawing, describe in detail.
In the embodiment of the gate associated transistor of the grooved gate polysilicon structure shown in Fig. 1, the lower floor 42 of silicon substrate 4 is collector electrode, and it is the N of thickness 420 μ m resistivity 0.01 Ω cm
+type silicon, upper strata 41 is N-type dual-layer high-resistance layer: the resistivity 20 Ω cm on the upper strata 411 of resistive formation, thickness 27 μ m, the resistivity 2 Ω cm of the lower floor 412 of resistive formation, thickness is 13 μ m.The spacing that has many parallel 5, two adjacent slots 5 of strip groove at the upper surface of silicon substrate film 4 is 12 μ m, the wide 5 μ m of the dark 3 μ m of groove 5.Bottom land is also advanced and is formed P by B Implanted ion
+type high concentration flute profile grid region 6, the surface concentration of boron is 1E19-2E20/cm
3, junction depth 6 μ m.The upper surface on silicon substrate upper strata 41, by boron Implantation and diffusion, forms P type base 2, and in P type base 2, the surface concentration of boron is 1E17-3E18/cm
3, junction depth 4 μ m.The upper surface on silicon substrate upper strata 41 is covered with the phosphorous doped polysilicon layer 9 that thickness is 0.5-0.6 μ m, the insulating barrier 7 being formed by silicon dioxide, phosphorosilicate glass, silicon nitride or their compound across one deck between the bottom of phosphorous doped polysilicon layer 9 and groove 5 and side, insulating barrier 7 extends to the upper surface of silicon substrate film 4, the thickness of insulating barrier 7 is 1 μ m, and the upper surface on the silicon substrate upper strata 41 between two adjacent slots 5 has high phosphorus concentration N
+type emitter region 3, the surface concentration of phosphorus is up to 2-9E20/cm
3, N
+the degree of depth of type emitter region 3 is 1.5 μ m.N
+type emitter region 3 is by insulating barrier 7 perforates, and phosphorous doped polysilicon layer 9 is connected with the upper surface on silicon substrate upper strata 41, and by phosphorous doped polysilicon layer 9, phosphorus is diffused into the upper surface on silicon substrate upper strata 41 forms.Emitter metal layer 1 is that the thickness generating by sputter is the aluminium lamination of 4 μ m, and collector electrode metal layer 8 is that thickness is the AuCr-Au metal level of 1 μ m.
Adopt the silicon substrate film of 4 kinds of different dual-layer high-resistance layers, the complex light of the tube core of two kinds of different sizes is cut blocks for printing, by identical technique, do the gate associated transistor chip of the grooved gate polysilicon structure of 4 kinds of different dual-layer high-resistance layer substrates simultaneously, then scribing is packaged into pipe, packs electricity-saving lamp into and examines relatively.
The lower floor of these four kinds different dual-layer high-resistance layer silicon substrates is all the N of thickness 420 μ m resistivity 0.01 Ω cm
+type silicon.Upper strata is the N-type silicon of different dual-layer high-resistance layer.These four kinds different dual-layer high-resistance layers are:
The first dual-layer high-resistance layer: the resistivity 60 Ω cm on the upper strata of resistive formation, thickness 20 μ m, the resistivity 20 Ω cm of the lower floor of resistive formation, thickness is 40 μ m.This is the dual-layer high-resistance layer structure of prior art.
The second dual-layer high-resistance layer: the resistivity 20 Ω cm on the upper strata of resistive formation, thickness 27 μ m, the resistivity 2 Ω cm of the lower floor of resistive formation, thickness is 13 μ m.Substrate described in embodiment shown in Fig. 1 is the substrate with the second dual-layer high-resistance layer.
The third dual-layer high-resistance layer: the resistivity 30 Ω cm on the upper strata of resistive formation, thickness 20 μ m, the resistivity 6 Ω cm of the lower floor of resistive formation, thickness is 40 μ m.
The 4th kind of dual-layer high-resistance layer: the resistivity 30 Ω cm on the upper strata of resistive formation, thickness 20 μ m, the resistivity 9 Ω cm of the lower floor of resistive formation, thickness is 40 μ m.
The tube core of two kinds of different sizes, a kind of is 0.7 * 0.7mm
2, a kind of is 1.0 * 1.0mm
2, the latter's die area is the former twice.
Employing the first dual-layer high-resistance layer is size 0.7 * 0.7mm that the substrate of the dual-layer high-resistance layer of prior art is made
2the gate associated transistor die package of grooved gate polysilicon structure in T0-92 shell, be referred to as A1 pipe, by size 1.0 * 1.0mm
2be referred to as A2 pipe.Adopt the size 0.7 * 0.7mm of the substrate making of the second dual-layer high-resistance layer
2the gate associated transistor die package of grooved gate polysilicon structure in T0-92 shell, be referred to as B1 pipe, size 1.0 * 1.0mm
2be referred to as B2 pipe.Adopt the size 0.7 * 0.7mm of the substrate making of the third dual-layer high-resistance layer
2the gate associated transistor die package of grooved gate polysilicon structure in T0-92 shell, be referred to as C1 pipe, size 1.0 * 1.0mm
2be referred to as C2 pipe.Adopt the size 0.7 * 0.7mm of the substrate making of the 4th kind of dual-layer high-resistance layer
2the gate associated transistor die package of grooved gate polysilicon structure in T0-92 shell, be referred to as D1 pipe, size 1.0 * 1.0mm
2be referred to as D2 pipe.
Implementation result:
The comparison of the A1 of one prior art, A2 pipe and B1 of the present invention, B2 pipe
With low-voltage circuit, A1 manage, A2 pipe, B1 pipe, B2 pipe respectively fill 6 3U-110 electricity-saving lamps, then put 100 ℃ of baking ovens simultaneously into and carry out the impact of ladder boosted switch.Lamp power is the numerical value of at room temperature turning on light after 30 minutes with the voltage of 120VAC.Start lamp power and adjust lowlyer, voltage ladder is 110V-120V-130V-140V-150V, and the impact that each voltage ladder is turned off the light and turned on light 60 seconds for 10 seconds after lighting a lamp 60 minutes totally 20 times, by rear, enters next ladder switching surge.After by 150V20 switching surge, the power of electricity-saving lamp is tuned up, then repeat the switching surge of 110V to 150V.
Result: A1 pipe can be examined by 20W140V3-15 switching surge, A2 pipe can be examined by 24W150V5-16 switching surge.B1 pipe can be examined by 25W150V10-18 switching surge, and B2 pipe can be examined by 27W150V9-19 switching surge.
B1 die area is only 1/2 of A2 die area, and impact resistance is stronger.Contrast experiment proves, in the switch application of 110VAC, the cost performance of tube core of the present invention is more than the twice of tube core of prior art.
The comparison of the A1 of two prior arts, A2 pipe and C1 of the present invention, C2 pipe and D1, D2 pipe
Use normal pressure circuit, A1 manage, A2 pipe, C1 pipe, C2 pipe and D1, D2 pipe respectively fill 64 circle screw lamp electricity-saving lamps, put 100 ℃ of baking ovens simultaneously into and carry out the impact of ladder boosted switch.Lamp power is the numerical value of at room temperature turning on light after 30 minutes with the voltage of 230VAC.Start lamp power and adjust lowlyer, voltage ladder is 220V-240V-260V-280V-300V, and the impact that each voltage ladder is turned off the light and turned on light 60 seconds for 10 seconds after lighting a lamp 60 minutes totally 20 times, by rear, enters next ladder switching surge.After by 300V20 switching surge, the power of electricity-saving lamp is tuned up, then repeat the switching surge of 220V to 300V.
Result: A1 pipe can be examined by 21W280V3-15 switching surge, A2 pipe can be examined by 25W280V5-16 switching surge.C1 pipe can be examined by 26W300V10-18 switching surge, and C2 pipe can be examined by 28W300V11-19 switching surge.D1 pipe can be examined by 25W300V10-15 switching surge, and D2 pipe can be examined by 27W300V10-17 switching surge.
C1 die area and D1 die area are all 1/2 of A2 die areas, and impact resistance is stronger.Contrast experiment proves, in the switch application of 220VAC, the cost performance of the technology of the present invention tube core is more than the twice of prior art tube core.
Technical scheme of the present invention can be dwindled the distance in adjacent grooved grid region by layout design, by technological design, the junction depth in grooved grid region is deepened, side direction is widened simultaneously, make the adjacent lower base of mutual overlapping formation p type impurity concentration, two grooved grid regions, thereby reduce, a base photoetching and base inject and high temperature advances technique, have reduced significantly cost.Fig. 2 is two adjacent grid regions of the present invention structural representations of overlapping embodiment mutually.Fig. 2 and Fig. 1 difference are that the grooved grid region degree of depth reaches 10 μ m, the base 2 that does not carry out separately base boron Implantation and diffuse to form.Base is by mutual overlapping the forming in two adjacent grooved grid regions.
In the embodiment of the present invention shown in Fig. 3, the Yu Cao top, top of the side insulation layer of every groove is equal.In the embodiment of the present invention shown in Fig. 4, the top of the side insulation layer of every groove is lower than the top of groove.The common trait of above two kinds of embodiment is that the top of side insulation layer of every groove is in groove.And in embodiment illustrated in fig. 1, the side insulation layer of every groove extends to the upper surface of silicon substrate film.In embodiment illustrated in fig. 3 and embodiment illustrated in fig. 4, outside groove, the upper surface of silicon substrate does not have insulating barrier, the height of the polysilicon of the side of groove (being the distance between the upper surface of upper surface polysilicon outside groove of trench bottom polysilicon) has reduced the thickness of an insulating barrier than Fig. 1, make the thin aluminium lamination in side highly significant reduce, thereby be conducive to reduce the all-in resistance of emitter aluminum strip, increase the uniformity of tube core internal current.Emitter metal layer 1 is that the thickness generating by sputter is the aluminium lamination of 4 μ m.The feature of sputter is that the aluminium lamination of side of groove is much thinner than the aluminium lamination of the outer upper surface of groove.The aluminium lamination of the outer upper surface of groove is that the aluminium lamination of side of 4 μ m and groove is less than 1 μ m, so the sheet resistance of side aluminium lamination is more much bigger than the sheet resistance of front aluminium lamination.Emitter aluminum strip will reach tens even hundreds of bar grooved grid regions across crossing, and the aluminium lamination of the side of groove is much thinner than the outer positive aluminium lamination of groove, so the all-in resistance of the thin aluminium of the side of groove accounts for a big chunk of the all-in resistance of emitter aluminum strip, sometimes or even main part.The top of the side insulation layer of groove, in groove, has just reduced the height of the thin aluminium of side, thereby has reduced significantly the all-in resistance of emitter aluminum strip.
The shape of emitter region of the present invention can, for bar shaped, square, hexagon, circle or other shapes, adopt bar shaped conventionally.For easy, the many places of specification are described and adopted emitter region is bar shaped, and base is bar shaped, and groove is bar shaped, and the table top being surrounded by mutually orthogonal groove is bar shaped.This is a kind of finger fork configuration of common power transistor.
The surrounding of emitter region of the present invention is connected with P type base, in the situation that slot pitch is smaller, the window of emitter region is larger, the surrounding of emitter region also can be directly connected to the side wall insulating layer of the groove in flute profile grid region.Fig. 3 and Fig. 4 have represented that the surrounding of emitter region is directly connected to the situation of side wall insulating layer of the groove in flute profile grid region.
The resistivity of the lower floor of dual-layer high-resistance layer of the present invention can be inhomogeneous, only require that mean value is at 2-9 Ω cm, the upper resistors rate of dual-layer high-resistance layer of the present invention can be also inhomogeneous, only requires that the average resistivity on upper strata is higher than the average resistivity of lower floor.
What need statement is; above-described embodiment is only for the present invention will be described but not limit the invention; therefore; for a person skilled in the art; in the situation that not deviating from spirit and scope of the invention, it is carried out to various apparent changes, all should be within protection scope of the present invention.
Claims (4)
1. a gate associated transistor for two resistive formation grooved gate polysilicon structures, Qi lower floor is N
+type low-resistivity layer, upper strata are that the upper surface of the silicon substrate film of N-type high resistivity layer has a plurality of N
+the emitter region of the high-dopant concentration of type, is connecting N above this emitter region
+the doped polysilicon layer of type, this doped polysilicon layer is connected with emitter metal layer, and there is the base of P type in the surrounding of each emitter region, and ining succession below the side of base, doping content is higher than base, the dark P of the depth ratio base degree of depth
+the flute profile grid region of type, the bottom surface of every groove in flute profile grid region and side are all covered with insulating barrier, grid region is connected with gate metal layer, the upper strata of silicon substrate film is positioned at below base and the part below grid region is collector region, the lower floor of silicon substrate film is collector electrode, the lower surface of collector electrode is connected with collector electrode metal layer, it is characterized in that:
The N-type high resistivity layer of described silicon substrate film is divided into two-layer up and down, and the resistivity on the upper strata of N-type high resistivity layer is higher than the resistivity of the lower floor of N-type high resistivity layer;
The resistivity of the lower floor of the N-type high resistivity layer of described silicon substrate film is 2-9 Ω cm;
The thickness of the lower floor of the N-type high resistivity layer of described silicon substrate film is 13-40 μ m.
2. the gate associated transistor of as claimed in claim 1 pair of resistive formation grooved gate polysilicon structure, is characterized in that:
Described two adjacent flute profile grid regions are overlapping mutually.
3. the gate associated transistor of as claimed in claim 1 pair of resistive formation grooved gate polysilicon structure, is characterized in that:
The side insulation layer of described every groove extends to the upper surface of silicon substrate film.
4. the gate associated transistor of as claimed in claim 1 pair of resistive formation grooved gate polysilicon structure, is characterized in that:
The top of the side insulation layer of described every groove is in groove.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410152021.5A CN103956377A (en) | 2014-04-16 | 2014-04-16 | GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure |
| CN201410347507.4A CN104218076B (en) | 2014-04-16 | 2014-07-21 | Grating transistor of groove-shaped grate polycrystalline silicon structure with double high-resistance layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410152021.5A CN103956377A (en) | 2014-04-16 | 2014-04-16 | GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103956377A true CN103956377A (en) | 2014-07-30 |
Family
ID=51333628
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410152021.5A Withdrawn CN103956377A (en) | 2014-04-16 | 2014-04-16 | GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure |
| CN201410347507.4A Expired - Fee Related CN104218076B (en) | 2014-04-16 | 2014-07-21 | Grating transistor of groove-shaped grate polycrystalline silicon structure with double high-resistance layers |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410347507.4A Expired - Fee Related CN104218076B (en) | 2014-04-16 | 2014-07-21 | Grating transistor of groove-shaped grate polycrystalline silicon structure with double high-resistance layers |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN103956377A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762181A (en) * | 2016-03-04 | 2016-07-13 | 李思敏 | Polycrystalline silicon emitting electrode transistor and manufacturing method therefor |
| CN108155244A (en) * | 2017-12-25 | 2018-06-12 | 深圳市晶特智造科技有限公司 | Groove-shaped gate associated transistor and preparation method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106952965B (en) * | 2017-03-27 | 2020-12-15 | 河北普兴电子科技股份有限公司 | Silicon epitaxial wafer and method for producing the same |
-
2014
- 2014-04-16 CN CN201410152021.5A patent/CN103956377A/en not_active Withdrawn
- 2014-07-21 CN CN201410347507.4A patent/CN104218076B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762181A (en) * | 2016-03-04 | 2016-07-13 | 李思敏 | Polycrystalline silicon emitting electrode transistor and manufacturing method therefor |
| CN108155244A (en) * | 2017-12-25 | 2018-06-12 | 深圳市晶特智造科技有限公司 | Groove-shaped gate associated transistor and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104218076B (en) | 2017-01-18 |
| CN104218076A (en) | 2014-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103956377A (en) | GAT of double-high-resistance-layer groove shape gate polycrystalline silicon structure | |
| US8953290B2 (en) | Device for protecting an integrated circuit against overvoltages | |
| CN102867846A (en) | Semiconductor device | |
| CN104051540A (en) | Super junction device and manufacturing method thereof | |
| CN106601731B (en) | Semiconductor structure with ESD protection structure and manufacturing method thereof | |
| CN102789979A (en) | Schottky diode and method of formation of Schottky diode | |
| CN106024634B (en) | Power transistor with electrostatic discharge protection diode structure and manufacturing method thereof | |
| CN102254828A (en) | Method for making semiconductor device with super junction structure and rapid reverse recovery characteristic | |
| CN102623491B (en) | High-voltage withstanding device in bipolar low-voltage process and manufacturing method thereof | |
| CN102403337B (en) | Semiconductor device | |
| CN109585288B (en) | SCR component with temperature stability characteristic and manufacturing method thereof | |
| CN204348725U (en) | The low capacitor transient stage voltage suppressor device of a kind of single channel | |
| CN113140627A (en) | SCR device with low trigger voltage and preparation method thereof | |
| CN101552285B (en) | Gate associated transistor of trough arsenic-doped polysilicon structure | |
| CN116454083A (en) | Longitudinal thyristor and manufacturing method thereof | |
| CN103247694A (en) | Groove Schottky semiconductor device and manufacturing method thereof | |
| CN102751327A (en) | Voltage-withstanding termination structure of power device | |
| CN103972306A (en) | Schottky device structure with discontinuous grooves and manufacturing method of Schottky device structure | |
| CN107887427B (en) | High-voltage diode with adjustable field plate | |
| CN113161351B (en) | Device structure of bipolar transistor integrated high-voltage starting resistor and manufacturing method | |
| CN101527317A (en) | Gate associated transistor with grooved gate polysilicon structure | |
| TW201724536A (en) | Solar cell and method for manufacturing the same | |
| CN103383968A (en) | Interface charge compensation Schottky semiconductor device and manufacturing method for same | |
| CN102751321B (en) | Gate associated transistor of groove-shaped gate polycrystalline silicon structure | |
| CN204424267U (en) | Reduce the structure of back of the body passivating solar battery back side black line |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C04 | Withdrawal of patent application after publication (patent law 2001) | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20140730 |