CN108155244A - Groove-shaped gate associated transistor and preparation method thereof - Google Patents
Groove-shaped gate associated transistor and preparation method thereof Download PDFInfo
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- CN108155244A CN108155244A CN201711423827.3A CN201711423827A CN108155244A CN 108155244 A CN108155244 A CN 108155244A CN 201711423827 A CN201711423827 A CN 201711423827A CN 108155244 A CN108155244 A CN 108155244A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000407 epitaxy Methods 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 239000012535 impurity Substances 0.000 claims description 20
- 238000002513 implantation Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000001737 promoting effect Effects 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 238000004026 adhesive bonding Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000003344 environmental pollutant Substances 0.000 description 3
- 231100000719 pollutant Toxicity 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of groove-shaped gate associated transistors and preparation method thereof.The groove-shaped gate associated transistor includes N-type substrate, the N-type epitaxy layer formed in the N-type substrate, in the p-type base area that the N-type epitaxy layer surface is formed, multiple grooves through the p-type base area, in the p-type high-doped zone that the multiple trench wall is formed, in the TEOS oxide layers that the p-type base area and the highly doped surface of the p-type are formed, opening through the TEOS oxide layers and the corresponding p-type base area, it is formed in the groove and the polysilicon in the opening, in the n-type region that the surface of the p-type base area is formed, in the TEOS oxide layers, the front metal formed on the p-type high-doped zone and the polysilicon, and the back metal formed in the N-type substrate far from the N-type epitaxy layer side.
Description
【Technical field】
The present invention relates to semiconductor fabrication process technical field, particularly, be related to a kind of groove-shaped gate associated transistor and its
Production method.
【Background technology】
Groove-shaped gate associated transistor is also referred to as UPGAT, is a kind of novel power device, and groove-shaped gate associated transistor is same
When there is MOSFET and BJT, be mainly characterized in that：Conducting resistance is small, and dynamic loss is small, and switching speed is fast, secondary to hit
High pressure is worn, power capacity and safety operation area are big；With negative temperature coefficient, thermal stability is good, impact resistance and anti-height
Radio-frequency radiation ability is strong.
In the case of collector plus high-pressure, the space-charge region between the deep knot grid region of gate associated transistor and collecting zone
Occur extending transversely, by the raceway groove pinch off between deep grid region, play the role of electrostatic screen to base area, wearing for base area can be inhibited
Logical effect, so as to which gate associated transistor can have thinner lighter base area compared to more traditional high-voltage three-pole pipe, so as to more
Big current gain, higher characteristic frequency.
The UPGAT devices made of common process, pressure resistance may be up to more than 800V, and electric current can reach several amperes,
It can be widely applied to AC-DC field of power management.
One of groove-shaped gate associated transistor is typical to be characterized in the vertical proliferation of impurity is made deep using groove.
During the additional reversed bias voltage of collector, the N-EPI between p-type high-doped zone can be depleted quickly, play the electrostatic sheild to p-type base area
The effect covered, when p-type base area is very light very shallow, p-type base area will not break-through easily.More than reason is based on, device can obtain
Obtain the current gain of bigger.
But in chip actual production manufacturing process, the groove of large-sized big depth, which can make technique, to be brought
The trouble of row, may cause in some cases device gluing apply flower, in groove the chemical pollutants such as photoresist can not remove and
Lead to the integrity problems such as device breakdown creep degeneration.
【Invention content】
More than in view of, the present invention provide it is a kind of at least solve said one technical problem groove-shaped gate associated transistor and its
Production method.
A kind of production method of groove-shaped gate associated transistor, includes the following steps：
N-type substrate is provided, N-type epitaxy layer is formed in the N-type substrate, p-type base is formed on the N-type epitaxy layer surface
Area forms multiple grooves through the p-type base area, p-type high-doped zone is formed in the multiple trench wall, in the p-type
Base area and the highly doped surface of the p-type form TEOS oxide layers；
The TEOS oxide layers are performed etching using photoresist, are run through and right so as to be formed in the TEOS oxide layers
Answer the opening of the p-type base area；
The photoresist is removed, forms polysilicon in the TEOS oxide layers and on the p-type base area of the opening, institute
Polysilicon is stated with N-type impurity；
Planarization is carried out to the polysilicon, so as to remove the partial polysilicon on the outside of groove so that the groove
In be retained with the polysilicon in the opening；
To the N-type impurity in the polysilicon into line activating with promoting so that the N-type impurity diffuses to the p-type base
Area surface, so as to form n-type region on the surface of the p-type base area；
The part TEOS oxide layers removed on the p-type high-doped zone are performed etching using photoresist；
Front metal is formed on the TEOS oxide layers, the p-type high-doped zone and the polysilicon, in the N-type
Substrate forms back metal far from the N-type epitaxy layer side.
In one embodiment, the injection element of the p-type base area is B, and implantation dosage is generally every square centimeter 1
14 powers are between every square centimeter 1 15 powers, and Implantation Energy is between 50Kev-200Kev.
In one embodiment, the width of the groove is in the range of 3um to 10um, and depth is in 2um to 10um's
In the range of.
In one embodiment, the formation of the p-type high-doped zone includes carrying out p-type to the channel bottom and side wall
The step of adulterating and being promoted to p type impurity, wherein being less than the injectant to the bottom to the implantation dosage of the side wall
The half of amount, the propulsion temperature promote oxidization time at 1 hour to 6 in the range of 1000 degrees Celsius to 1200 degrees Celsius
In the range of hour, after being promoted, the junction depth of the p-type high-doped zone of the channel bottom is in the range of 2um to 10um, institute
The junction depth of trenched side-wall is stated in the range of 1.5um to 7.5um, the concentration of the p-type base area is less than the p-type high-doped zone
Concentration, after the completion of propulsion, the junction depth of the p-type base area is generally in the range of 1um to 4um.
In one embodiment, the TEOS oxide layers are grown by the way of LPCVD, thickness at 3000 angstroms extremely
In the range of 8000 angstroms.
In one embodiment, the polysilicon is grown using LPCVD modes, and the thickness of the polysilicon is more than
The half of the groove width so that the groove is filled；The growth thickness of the polysilicon is in the range of 2um to 7um；
The N-type impurity of the polysilicon includes P, and impurity gas includes hydrogen phosphide PH3.
In one embodiment, the step of removing the partial polysilicon on the outside of groove includes：It is flat using chemical machinery
Change technology is etched back to remove the partial polysilicon on the outside of the groove.
In one embodiment, the production method is additionally included in the step of the thinning back side before forming the back metal
Suddenly.
In one embodiment, the N-type substrate is the highly doped substrate of N-type, and the N-type epitaxy layer is low-doped for N-type
Epitaxial layer.
A kind of groove-shaped gate associated transistor, the N-type epitaxy layer formed including N-type substrate, in the N-type substrate,
P-type base area that the N-type epitaxy layer surface is formed, through multiple grooves of the p-type base area, in the multiple trench wall shape
Into p-type high-doped zone, formed on the p-type base area and the highly doped surface of the p-type TEOS oxide layers, through the TEOS
Oxide layer and the opening of the corresponding p-type base area, be formed in the groove in the opening polysilicon, in the p-type
N-type region that the surface of base area is formed is formed on the TEOS oxide layers, the p-type high-doped zone and the polysilicon
Front metal and the back metal formed in the N-type substrate far from the N-type epitaxy layer side.
Compared to the prior art, groove-shaped gate associated transistor of the present invention and preparation method thereof includes advantages below：It eliminates
Polysilicon lithography and etching reduces the cost of manufacture of device；After being planarized, subsequently gluing light can be done in plane
It carves, the risk that traditional handicraft bottom graph exposure can not expose open because glue is blocked up can be evaded；After being planarized, big groove is complete
It fills and leads up entirely, without having to worry about chemical pollutant is accumulated in groove, the problem of spending is applied without having to worry about follow-up gluing；Polysilicon in groove
It is disconnected with the emitter region polysilicon in opening, is not an entirety, this will substantially weaken polycrystalline silicon membrane and is answered to device is to be come
Power, and improve because of the element leakage caused by surface stress and less reliable the problem of.
【Description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow chart of the production method of the groove-shaped gate associated transistor of the present invention.
Fig. 2-Fig. 8 is the structure diagram of each step of the production method of groove-shaped gate associated transistor shown in Fig. 1.
【Specific embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
- Fig. 8 is please referred to Fig.1, Fig. 1 is the flow chart of the production method of the groove-shaped gate associated transistor of the present invention, and Fig. 2-Fig. 8 is
The structure diagram of each step of the production method of groove-shaped gate associated transistor shown in Fig. 1.The groove-shaped gate associated transistor
Production method includes the following steps.
Step S1 referring to Fig. 2, providing N-type substrate, forms N-type epitaxy layer, outside the N-type in the N-type substrate
Prolong layer surface and form p-type base area, form multiple grooves through the p-type base area, it is high to form p-type in the multiple trench wall
Doped region forms TEOS (ethyl orthosilicate) oxide layer in the p-type base area and the highly doped surface of the p-type.
Specifically, the injection element of the p-type base area be B, implantation dosage generally every square centimeter 1 14 powers to often
Between 15 powers of square centimeter 1, Implantation Energy is between 50Kev-200Kev.The width of the groove is in 3um to 10um's
In the range of, depth is in the range of 2um to 10um.The formation of the p-type high-doped zone is included to the channel bottom and side wall
The step of carrying out p-type doping and being promoted to p type impurity, wherein the implantation dosage to the side wall is less than to the bottom
The half of implantation dosage, the propulsion temperature promote oxidization time small 1 in the range of 1000 degrees Celsius to 1200 degrees Celsius
In the range of 6 hours, after being promoted, the junction depth of the p-type high-doped zone of the channel bottom is in the range of 2um to 10um
Interior, for the junction depth of the trenched side-wall in the range of 1.5um to 7.5um, the concentration of the p-type base area is highly doped less than the p-type
The concentration in miscellaneous area, after the completion of propulsion, the junction depth of the p-type base area is generally in the range of 1um to 4um.The p type impurity can be with
For element boron B.
Further, in the step S1, the TEOS oxide layers are grown by the way of LPCVD, and thickness exists
In the range of 3000 angstroms to 8000 angstroms.The TEOS oxide layers are grown by the way of LPCVD, thickness at 3000 angstroms extremely
In the range of 8000 angstroms.
Step S2, referring to Fig. 3, being performed etching using photoresist to the TEOS oxide layers, so as in the TEOS oxygen
Change the opening for being formed in layer and running through and correspond to the p-type base area.The opening is open for emitter region.
Step S3, referring to Fig. 4, remove the photoresist, in the TEOS oxide layers and the p-type base of the opening
Polysilicon is formed in area, the polysilicon has N-type impurity.The polysilicon uses LPCVD (low-pressure chemical vapor depositions
Method) mode grows, and the thickness of the polysilicon is more than the half of the groove width so that the groove is filled；Institute
The growth thickness of polysilicon is stated in the range of 2um to 7um；The N-type impurity of the polysilicon includes phosphorus P, and impurity gas includes
Hydrogen phosphide PH3。
Step S4, referring to Fig. 5, planarization is carried out to the polysilicon, it is more so as to remove part on the outside of groove
Crystal silicon so that be retained in the groove with the polysilicon in the opening.Specifically, the planarization can be chemistry
Mechanical planarization technology (CMP) is etched back to planarization.
Step S5, referring to Fig. 6, to the N-type impurity in the polysilicon into line activating with promoting so that the N-type is miscellaneous
Matter diffuses to the p-type base region surface, so as to form n-type region on the surface of the p-type base area.The N-type impurity can wrap
Include phosphorus P.
Step S6, referring to Fig. 7, performing etching the part TEOS oxygen removed on the p-type high-doped zone using photoresist
Change layer.
Step S7, referring to Fig. 8, being formed just on the TEOS oxide layers, the p-type high-doped zone and the polysilicon
Face metal forms back metal in the N-type substrate far from the N-type epitaxy layer side.In one embodiment, institute is being formed
Before stating back metal, the production method further includes the step of carrying out back thinning.
As shown in figure 8, the groove-shaped gate associated transistor that above-mentioned production method obtains includes N-type substrate, in the N-type substrate
The N-type epitaxy layer of upper formation, the N-type epitaxy layer surface formed p-type base area, through the p-type base area multiple grooves,
In the p-type high-doped zone that the multiple trench wall is formed, formed in the p-type base area and the highly doped surface of the p-type
TEOS oxide layers, through the TEOS oxide layers and the corresponding p-type base area opening, be formed in the groove and opened with described
Polysilicon in mouthful, the n-type region, highly doped in the TEOS oxide layers, the p-type formed on the surface of the p-type base area
The front metal that is formed in area and the polysilicon and at the back side that the N-type substrate is formed far from the N-type epitaxy layer side
Metal.
Compared to the prior art, groove-shaped gate associated transistor of the present invention and preparation method thereof includes advantages below：It eliminates
Polysilicon lithography and etching reduces the cost of manufacture of device；After being planarized, subsequently gluing light can be done in plane
It carves, the risk that traditional handicraft bottom graph exposure can not expose open because glue is blocked up can be evaded；After being planarized, big groove is complete
It fills and leads up entirely, without having to worry about chemical pollutant is accumulated in groove, the problem of spending is applied without having to worry about follow-up gluing；Polysilicon in groove
It is disconnected with the emitter region polysilicon in opening, is not an entirety, this will substantially weaken polycrystalline silicon membrane and is answered to device is to be come
Power, and improve because of the element leakage caused by surface stress and less reliable the problem of.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
It encloses.
Claims (10)
1. a kind of production method of groove-shaped gate associated transistor, it is characterised in that：The production method includes the following steps：
N-type substrate is provided, N-type epitaxy layer is formed in the N-type substrate, p-type base area is formed on the N-type epitaxy layer surface,
Multiple grooves through the p-type base area are formed, p-type high-doped zone are formed in the multiple trench wall, in the p-type base area
And the highly doped surface of p-type forms TEOS oxide layers；
The TEOS oxide layers are performed etching using photoresist, runs through so as to be formed in the TEOS oxide layers and corresponds to institute
State the opening of p-type base area；
The photoresist is removed, polysilicon is formed in the TEOS oxide layers and on the p-type base area of the opening, it is described more
Crystal silicon has N-type impurity；
To the polysilicon carry out planarization, so as to remove the partial polysilicon on the outside of groove so that in the groove with
Polysilicon in the opening is retained；
To the N-type impurity in the polysilicon into line activating with promoting so that the N-type impurity diffuses to p-type base area table
Face, so as to form n-type region on the surface of the p-type base area；
The part TEOS oxide layers removed on the p-type high-doped zone are performed etching using photoresist；
Front metal is formed on the TEOS oxide layers, the p-type high-doped zone and the polysilicon, in the N-type substrate
Back metal is formed far from the N-type epitaxy layer side.
2. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The note of the p-type base area
Enter element for B, implantation dosage is generally between every square centimeter 1 15 powers of 14 powers to every square centimeter 1, Implantation Energy
Between 50Kev-200Kev.
3. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The width of the groove exists
In the range of 3um to 10um, depth is in the range of 2um to 10um.
4. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The p-type high-doped zone
Formation the step of including carrying out the channel bottom and side wall p-type doping and promoting p type impurity, wherein to described
The implantation dosage of side wall is less than the half to the implantation dosage of the bottom, and the propulsion temperature is taken the photograph at 1000 degrees Celsius to 1200
In the range of family name's degree, oxidization time is promoted in the range of 1 hour to 6 hours, after being promoted, the p-type of the channel bottom
The junction depth of high-doped zone is in the range of 2um to 10um, and the junction depth of the trenched side-wall is in the range of 1.5um to 7.5um, institute
The concentration for stating p-type base area is less than the concentration of the p-type high-doped zone, and after the completion of propulsion, the junction depth of the p-type base area generally exists
In the range of 1um to 4um.
5. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The TEOS oxide layers are adopted
It is grown with the mode of LPCVD, thickness is in the range of 3000 angstroms to 8000 angstroms.
6. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The polysilicon uses
LPCVD modes are grown, and the thickness of the polysilicon is more than the half of the groove width so that the groove is filled；
The growth thickness of the polysilicon is in the range of 2um to 7um；The N-type impurity of the polysilicon includes P, and impurity gas includes
Hydrogen phosphide PH3。
7. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：Remove the portion on the outside of groove
The step of dividing polysilicon includes：Using chemical-mechanical planarization technology or it is etched back to remove part polycrystalline on the outside of the groove
Silicon.
8. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The production method is also wrapped
Include the thinning back side step before the back metal is formed.
9. the production method of groove-shaped gate associated transistor as described in claim 1, it is characterised in that：The N-type substrate is N-type
Highly doped substrate, the N-type epitaxy layer are the low-doped epitaxial layer of N-type.
10. a kind of groove-shaped gate associated transistor, it is characterised in that：The groove-shaped gate associated transistor includes N-type substrate, described
The N-type epitaxy layer that is formed in N-type substrate, the p-type base area formed on the N-type epitaxy layer surface, through the more of the p-type base area
A groove, the multiple trench wall formed p-type high-doped zone, in the p-type base area and the highly doped surface shape of the p-type
Into TEOS oxide layers, through the TEOS oxide layers and the corresponding p-type base area opening, be formed in the groove and institute
State opening in polysilicon, is formed on the surface of the p-type base area n-type region, the TEOS oxide layers, the p-type height
It the front metal that is formed on doped region and the polysilicon and is formed in the N-type substrate far from the N-type epitaxy layer side
Back metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711423827.3A CN108155244B (en) | 2017-12-25 | 2017-12-25 | Groove type grid-connected transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711423827.3A CN108155244B (en) | 2017-12-25 | 2017-12-25 | Groove type grid-connected transistor and manufacturing method thereof |
Publications (2)
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| CN109975904A (en) * | 2019-03-22 | 2019-07-05 | 无锡中微掩模电子有限公司 | A kind of reflective DOE diffractive optical element of high-precision and preparation method thereof |
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
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| CN108155244B (en) | 2021-10-01 |
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