JP2011146426A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide MOSFET capable of improving a channel mobility without degrading a gate threshold voltage. <P>SOLUTION: A silicon carbide semiconductor device 200 has: a silicon carbide substrate 10; a silicon carbide layer 20 formed on the silicon carbide substrate 10; a gate insulating film 30 formed on the silicon carbide layer 20; and a gate electrode 40 that is formed at a predetermined position on the silicon carbide layer 20 through the gate insulating film 30 and includes a polycrystalline silicon containing B, Al or Ga, which are a group III light element, as a p-type dopant. The p-type dopant contained in the gate electrode 40 is diffused in the vicinity of an interface between the silicon carbide layer 20 just below the gate electrode 40 and the gate insulating film 30, and an impurity level in the vicinity of the interface is passivated by the p-type dopant. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device made of silicon carbide and a method for manufacturing the same.

  In recent years, power devices using silicon carbide have been developed in order to overcome the physical property limitations of power devices using silicon. A silicon carbide MOSFET (Metal Oxide Field Effect Transistor), which is one of silicon carbide power devices and is mainly used as a switching element, has a carrier mobility (channel mobility) in the MOSFET channel portion to reduce on-resistance. It is required to be high.

  As a conventional silicon carbide MOSFET, the channel portion doping type is n-type and the gate electrode is formed of p-type polycrystalline silicon, thereby achieving both improvement in channel mobility and proper retention of the gate threshold voltage. Yes (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 2004-71750

  In a MOSFET using silicon carbide, a high-density interface state is generated at the interface between the gate insulating film and the silicon carbide semiconductor layer in the MOS structure, and the channel mobility is significantly reduced compared to the bulk mobility. For this reason, in the silicon carbide MOSFET, the on-resistance is increased, which is an obstacle to lowering the loss. Although the channel mobility can be increased by setting the doping type of the channel portion to n-type, the gate threshold voltage is lowered and this causes a problem in the safe operation of the device. In the silicon carbide MOSFET and the manufacturing method thereof disclosed in Patent Document 1, the gate threshold voltage is increased by about 1 V by changing the polycrystalline silicon gate electrode from the commonly used n-type to the p-type, thereby moving the channel. The trade-off between the power and the gate threshold voltage is improved, but the degree of improvement is slight.

  The present invention has been made to solve such problems, and provides a silicon carbide semiconductor device and a method for manufacturing the same that can improve channel mobility without lowering the gate threshold voltage.

  A silicon carbide semiconductor device according to the present invention includes a silicon carbide substrate, a silicon carbide layer formed on the silicon carbide substrate and including an epitaxial layer and an ion implantation region, and an insulating film formed on the silicon carbide layer. And a gate electrode made of polycrystalline silicon formed at a predetermined position on the silicon carbide layer via the insulating film, the gate electrode containing either B, Al or Ga as an impurity, The impurity is included in the vicinity of the interface between the silicon carbide layer directly below the gate electrode and the insulating film.

  A method for manufacturing a silicon carbide semiconductor device according to the present invention includes a step of forming a silicon carbide epitaxial layer on a silicon carbide substrate, a step of forming an ion implantation region in the silicon carbide epitaxial layer, and the silicon carbide epitaxial A step of forming an insulating film on a silicon carbide layer comprising a layer and the ion-implanted region, and a polycrystal containing B, Al or Ga as an impurity at a predetermined position on the silicon carbide layer via the insulating film A step of forming a gate electrode made of silicon, a diffusion step of diffusing the impurity in the vicinity of the interface between the silicon carbide layer directly below the gate electrode and the insulating film, and a step of performing annealing for activating the impurity Is included.

  According to the present invention, by introducing any of p-type dopants B, Al, or Ga into the interface between the gate insulating film and the silicon carbide semiconductor layer, the interface state existing at the interface is reduced. Further, since the gate electrode is made of p-type polycrystalline silicon having a high work function, the gate threshold voltage is kept high. As a result, it is possible to easily obtain a silicon carbide MOSFET that can improve channel mobility while maintaining a high gate threshold voltage.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is a figure which shows the relationship between the peak value of the effective channel mobility of the silicon carbide semiconductor device in Embodiment 1 of this invention, and a gate threshold with a comparative example. It is sectional drawing which shows the structure of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows a part of manufacturing process of the silicon carbide semiconductor device in Embodiment 2 of this invention.

Embodiment 1 FIG.
1 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention. 2 to 9 are cross sectional views showing a part of the process for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention.

  First, with reference to FIG. 1, the structure of the silicon carbide semiconductor device in Embodiment 1 is demonstrated.

In FIG. 1, silicon carbide MOSFET 100 which is a silicon carbide semiconductor device includes a silicon carbide substrate 10, a silicon carbide layer 20 formed on silicon carbide substrate 10, an insulating film 30 formed on silicon carbide layer 20, Gate electrode 40 formed on insulating film 30, and source electrode 50 and drain electrode 60 formed on silicon carbide layer 20 are included. The silicon carbide layer 20 includes a silicon carbide epitaxial layer 21, a p-type base region 22 that is an ion implantation region or an epitaxial layer, an n-type source region 23a that is an ion implantation region, an n-type drain region 23b, and a p-type base contact. p ⁺⁺ region 24 is formed.

Silicon carbide epitaxial layer 21 is formed on silicon carbide substrate 10, and p-type base region 22 is formed in the surface layer portion of silicon carbide epitaxial layer 21. Inside the p-type base layer 22, an n-type source region 23 a and an n-type drain region 23 b are formed so as to be in contact with the surface of the silicon carbide layer 20 at a predetermined interval. A p ⁺⁺ base contact p ⁺⁺ region 24 is formed at a position adjacent to the region 23a.

  A gate insulating film 30 is formed on the surface of the silicon carbide layer 20, and a gate electrode 40 is formed on the silicon carbide layer 20 via the gate insulating film 30. The gate electrode 40 is formed so as to cover part of the n-type source region 23a and the n-type drain region 23b with the insulating film 30 interposed therebetween. In addition, the gate electrode 40 contains any of group III light elements B, Al, or Ga as a p-type impurity.

Source electrode 50 and drain electrode 60 are formed on silicon carbide layer 20, source electrode 50 is n-type source region 23 a and p-type base contact p ⁺⁺ region 24, and drain electrode 60 is an n-type drain region. 23b, respectively.

  In the vicinity of the interface between the channel region formed in the silicon carbide layer 20 immediately below the gate electrode 40 and the gate insulating film 30, any of B, Al, or Ga that is a p-type impurity contained in the gate electrode 40 is present. Has been spread.

  Next, a method for manufacturing the silicon carbide semiconductor device in the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 2, a temperature of 1500 to 1800 ° C., an atmospheric pressure of 250 hPa (mbar), a carrier gas species: H ₂ , and a generated gas species: SiH are formed on the silicon carbide substrate 10 by a thermal CVD (Chemical Vapor Deposition) method. _4. A silicon carbide epitaxial layer 21 having a thickness of 0.3 μm or more is laminated under the condition of C ₃ H ₈ .

Next, as shown in FIG. 3, Al, B, or Ga having a depth of 0.5 to 3.0 μm and a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ is formed on the surface layer portion of the silicon carbide epitaxial layer 21. Ions are implanted to form the p-type base region 22. Alternatively, a p-type silicon carbide epitaxial layer may be further formed on silicon carbide epitaxial layer 21 to form p-type base region 22.

Next, a mask for selective ion implantation (not shown) is formed on the p-type base region layer 22, and as shown in FIG. 4, the n-type source region 23 a and the n-type drain region 23 b have a depth of 0. N, As, or P ions having a concentration of 1 to 2.0 μm and a concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ are implanted. After removing the selective ion implantation mask, a new selective ion implantation mask (not shown) is formed, and a depth of 0.1 to 2.0 μm and a concentration of 1 × are formed in the p ⁺⁺ region 24 for p-type base contact. 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ of Al, B, or Ga ions are implanted.

Then, after removing the selective ion implantation mask, activation annealing is performed at a temperature of 1300 to 2100 ° C., and the p-type base region 22, the n-type source region 23 a, the n-type drain region 23 b, and the p-type, which are ion implantation regions. The base contact p ⁺⁺ region 24 is electrically activated. Thereby, an n-type channel region is formed in p-type base region 22 which is silicon carbide layer 20 between n-type source region 23a and n-type drain region 23b.

  Next, as shown in FIG. 5, the gate insulating film 30 is formed on the entire surface of the silicon carbide layer 20 by surface thermal oxidation at a temperature of 800 to 1400 ° C. or a film lamination process by a CVD method.

  Next, as shown in FIG. 6, a polycrystalline silicon film 40a is laminated on the gate insulating film 30 by CVD without impurity doping. Alternatively, the p-type polycrystalline silicon film 40a may be laminated by introducing a doping gas containing Al, B, or Ga that is a group III light element when the polycrystalline silicon film 40a is laminated.

When the polycrystalline silicon film 40a is stacked without impurity doping in the above process, as shown in FIG. 7, B, Al, or Ga ions, which are group III light elements, are used as the p-type dopant. Inject into 40a. Note that the concentration of the p-type dopant is preferably about 10 ¹⁹ to 10 ²² cm ⁻³ .

  Next, as shown in FIG. 8, the polycrystalline silicon film 40a is formed into a shape in which the n-type source region 23a and the n-type drain region 23b are located at both ends via the gate insulating film 30 by lithography and etching techniques. Is molded. Thereafter, heat treatment is performed at a temperature of 600 to 1100 ° C. for 1 to 300 seconds, for example, and a p-type dopant composed of any of group III light elements B, Al, or Ga introduced into the polycrystalline silicon film 40a is formed on the polycrystalline silicon film. Diffusion is performed to the depth direction of 40a and to the vicinity of the gate insulating film 30 and the interface between the gate insulating film 30 and the silicon carbide layer 20. Thereby, the polycrystalline silicon film 40a becomes the gate electrode 40, and the p-type dopant diffused to the vicinity of the interface between the gate insulating film 30 and the silicon carbide layer 20 passivates the interface states existing in the vicinity of the interface.

  Here, the vicinity of the interface refers to a range in which the effect of passivating the interface states existing in the vicinity of the interface can be obtained. Specifically, the p-type dopant as an impurity is within a distance of 5 nm or less with respect to the interface. It is preferable that it exists in.

Next, as shown in FIG. 9, the gate insulating film 30 on the n-type source region 23a, the n-type drain region 23b and the p-type base contact p ⁺⁺ region 24 is removed by lithography and etching techniques, and the n-type source region 23a, n-type drain region 23b and p-type base contact p ⁺⁺ region 24 are exposed on the surface.

Then, Ni is laminated on part of the n-type source region 23a, n-type drain region 23b, and p-type base contact p ⁺⁺ region 24 exposed on the surface to form the source electrode 50 and the drain electrode 60. As a material for the contact electrode, in addition to Ni, Ti, Al, Mo, Cr, Pt, W, Si, TiC, or an alloy thereof may be used. Finally, in order to alloy the source electrode 50 and the drain electrode 60 with the silicon carbide in contact with the silicon carbide, the temperature is 950 to 1000 ° C., the treatment time is 20 to 60 seconds, and the temperature raising rate is 10 to 25. A heat treatment at 0 ° C./second is performed. Thereby, the main part of the element structure of silicon carbide MOSFET 100 as shown in FIG. 1 is completed.

  FIG. 10 shows the relationship between the peak value of effective channel mobility and the gate threshold value obtained from the lateral MOSFET fabricated in this manner. However, in FIG. 10, the plots indicated by “◯” are values of a conventional silicon carbide MOSFET having an n-type polycrystalline silicon gate electrode (the structure is the same as that shown in FIG. 1 except for the gate electrode 40). , The plots indicated by “Δ” are values of the silicon carbide MOSFET 100 manufactured by the manufacturing method of the present embodiment. The obtained effective channel mobility peak value is increased by applying the manufacturing method of the present embodiment, and is further increased by increasing the dose of the p-type dopant. This is due to the fact that the interface state is passivated with a higher density by increasing the impurity concentration that diffuses to the vicinity of the interface between the gate insulating film 30 and the silicon carbide layer 20. Further, since the gate electrode 40 is p-type, the gate threshold is kept high. As a result, the trade-off between channel mobility and gate threshold is greatly improved compared to MOSFETs fabricated by conventional methods.

  In the silicon carbide MOSFET described above, the impurity state is introduced into the interface between the gate insulating film and the silicon carbide semiconductor layer, whereby the interface state existing at the interface is reduced. As a result, the channel mobility is higher than that of the conventional n-type polycrystalline silicon gate electrode MOSFET (◯ plot), as shown by the Δ plot in FIG. Further, since the gate electrode 40 is made of p-type polycrystalline silicon having a high work function, the gate threshold is kept high. As a result, the tradeoff between channel mobility and gate threshold is greatly improved. The effect becomes more prominent as the concentration of the impurity dopant introduced into the interface between the p-type polycrystalline silicon electrode or the gate insulating film 30 and the silicon carbide layer 20 increases. In general, p-type gate MOSFETs using silicon cause problems when B or the like diffuses into the channel region. However, silicon carbide has a very low impurity diffusion coefficient, and thus becomes a problem with silicon MOSFETs. There is no problem.

  As described above, according to the present embodiment, the gate electrode 40 made of polycrystalline silicon is made p-type by doping any of the impurities of B, Al, or Ga, which are group III light elements, and the implanted dopant is further doped. A silicon carbide MOSFET that can increase the effective channel mobility easily while maintaining a high gate threshold by diffusing to the vicinity of the interface between the gate insulating film and the silicon carbide semiconductor layer by heat treatment and using it for passivation of the interface state It became possible to get to.

Embodiment 2. FIG.
FIG. 11 is a cross sectional view showing the structure of the silicon carbide semiconductor device in the second embodiment of the present invention. 12 to 19 are cross sectional views showing the steps for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention.

  First, with reference to FIG. 11, the structure of the silicon carbide semiconductor device in Embodiment 2 is demonstrated.

In FIG. 11, vertical MOSFET 200 that is a silicon carbide semiconductor device includes a silicon carbide substrate 10, a silicon carbide layer 20 formed on the surface of silicon carbide substrate 10, and a gate insulating film 30 formed on silicon carbide layer 20. A gate electrode 40 formed on the gate insulating film 30, a source / base common electrode 51 formed on the silicon carbide layer 20, a drain electrode 60 formed on the back surface of the silicon carbide substrate 10, and a gate electrode And an interlayer insulating film 70 formed on the substrate 40. The silicon carbide layer 20 includes a silicon carbide epitaxial layer 21, a p-type base region 22 that is an ion implantation region or an epitaxial layer, an n-type source region 23 that is an ion implantation region, and a p ⁺⁺ region 24 for p-type base contact. And a silicon carbide epitaxial additional growth layer 25.

Silicon carbide epitaxial layer 21 is formed on silicon carbide substrate 10, and p-type base region 22 is formed in the surface layer portion of silicon carbide epitaxial layer 21. A pair of p-type base regions 22 are formed in the surface layer portion of silicon carbide epitaxial layer 21 at intervals. An n-type source region 23 is formed at a predetermined position inside the pair of p-type base regions 22 so as to be in contact with the surface of the silicon carbide layer 20, and at a position adjacent to the n-type source region 23. A p ⁺⁺ region 24 for p-type base contact is formed. Silicon carbide epitaxial additional layer 25 is formed on the surface of silicon carbide layer 20, and silicon carbide epitaxial additional layer 25 includes silicon carbide epitaxial layer 21, p-type base region 22, and n-type source region. 23 is formed so as to cover a part of 23.

  A gate insulating film 30 is formed on the surface of the silicon carbide layer 20, and a gate electrode 40 is formed on the silicon carbide additional growth layer 25 via the gate insulating film 30. The gate electrode 40 is formed so as to cover a part of the n-type source region 24 with the insulating film 30 interposed therebetween. In addition, the gate electrode 40 contains any of group III light elements B, Al, or Ga as a p-type impurity.

A source / base common electrode 51 is formed on the silicon carbide layer 20, and the source / base common electrode 51 is connected to the n-type source region 23 and the p-type base contact p ^{+ +} region 24.

  In the present embodiment, in order to improve the channel mobility, silicon carbide epitaxial additional layer 25 is provided on the outermost surface of silicon carbide layer 20 immediately below gate electrode 40. This silicon carbide epitaxial additional layer 25 is provided. The gate insulating film 30 may be formed directly on the silicon carbide layer 20 without forming the gate.

  Then, any of p-type dopants of B, Al, or Ga contained in the gate electrode 40 is diffused in the vicinity of the interface between the silicon carbide layer 20 immediately below the gate electrode 40 and the gate insulating film 30.

  Next, a method for manufacturing the silicon carbide semiconductor device in the second embodiment will be described with reference to FIGS.

First, as shown in FIG. 12, a temperature of 1500 to 1800 ° C., an atmospheric pressure of 250 hPa (mbar), a carrier gas type: H ₂ , and a generated gas type: SiH ₄ are formed on a silicon carbide substrate 10 having an off angle by a thermal CVD method. The silicon carbide epitaxial layer 21 having a film thickness of 1.0 to 100 μm is stacked under the condition of C ₃ H ₈ .

Next, a selective ion implantation mask (not shown) is formed on the silicon carbide epitaxial layer 21, and as shown in FIG. 13, the p-type base region 22 has a depth of 0.5 to 3.0 μm and a concentration. Implant Al, B, or Ga ions of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ . After removing the selective ion implantation mask, a new selective ion implantation mask (not shown) is formed, and the n-type source region 23 has a depth of 0.1 to 2.0 μm and a concentration of 1 × 10 ¹⁸ to 1. ^Implant N, As, or P ions of × 10 ²⁰ cm ⁻³ . After removing the selective ion implantation mask, a new selective ion implantation mask is formed, and a depth of 0.1 to 2.0 μm and a concentration of 1 × 10 ¹⁹ to 1 × are formed in the p ⁺⁺ region 24 for p-type base contact. 10 ²¹ cm ⁻³ Al, B, or Ga ions are implanted.

After removing the mask for selective ion implantation, activation annealing is performed at a temperature of 1300 to 2100 ° C. to electrically activate the p-type base region 22, the n-type source region 23, and the p-type base contact p ⁺⁺ region 24. .

Next, as shown in FIG. 14, channel silicon carbide epitaxial additional layer 25 is formed on silicon carbide epitaxial layer 21 including p-type base region 22, n-type source region 23, and p-type base contact p ⁺⁺ region 24. The silicon carbide epitaxial layer 21 exposed between the pair of p-type base regions 22 is positioned in the center by lithography and RIE (relative ion etching) technology, and each of the p-type base region 22 and the n-type source region The shape is such that 23 is located at both ends. Alternatively, the next step may be performed without forming channel silicon carbide epitaxial additional layer 25. When channel silicon carbide epitaxial additional layer 25 is formed, an n-type channel region is formed in silicon carbide epitaxial additional layer 25.

  Then, after the surface is thermally oxidized at a temperature of 800 to 1400 ° C., the thermal oxide film is removed with hydrofluoric acid (sacrificial oxidation process), and the gate insulating film 30 is formed on the entire surface of the silicon carbide layer 20.

  Next, as shown in FIG. 15, a polycrystalline silicon film 40a is stacked without impurity doping by a thermal CVD process. Alternatively, the p-type polycrystalline silicon film 40a may be stacked by introducing a doping gas containing Al, B, or Ga that is a group III light element during stacking.

When the polycrystalline silicon film 40a is laminated without impurity doping in the above process, as shown in FIG. 16, the group III light element B, Al, or Ga ions are used as the p-type dopant. Inject into 40a.
Note that the concentration of the p-type dopant is preferably about 10 ¹⁹ to 10 ²² cm ⁻³ .

  Next, as shown in FIG. 17, the silicon carbide epitaxial layer 21 exposed between the pair of p-type base regions 22 is positioned in the center via the insulating film 30 by lithography and etching techniques, and the respective p-type bases. Polycrystalline silicon film 40a is formed in such a shape that region 22 and n-type source region 23 are located at both ends.

  Then, heat treatment is performed at a temperature of 600 to 1100 ° C. for 1 to 300 seconds, and impurity ions implanted into the polycrystalline silicon film 40a are converted into the depth direction of the polycrystalline silicon film 40a, the gate insulating film 30, and the gate insulating film 30. The silicon carbide layer 20 is diffused to the vicinity of the interface. Thereby, the polycrystalline silicon film 40a becomes the p-type gate electrode 40, and the impurity ions diffused to the vicinity of the interface between the gate insulating film 30 and the silicon carbide layer 20 passivate the interface state existing in the vicinity of the interface.

  Here, the vicinity of the interface refers to a range in which the effect of passivating the interface states existing in the vicinity of the interface can be obtained. Specifically, the p-type dopant as an impurity is within a distance of 5 nm or less with respect to the interface. It is preferable that it exists in.

  Next, as shown in FIG. 18, an interlayer insulating film 70 for electrically insulating the source and the gate is laminated on the entire surface of the element.

Next, as shown in FIG. 19, the gate insulating film 30 and the interlayer insulating film 70 on each n-type source region 23 and the p-type base contact p ⁺⁺ region 24 are removed by lithography and etching techniques, and the n-type source region is removed. 23 and p ⁺⁺ region 24 for p-type base contact are exposed on the surface.

Then, as shown in FIG. 19, Ni is stacked on the n-type source region 23 and the p-type base contact p ⁺⁺ region 24 exposed on the surface to form a source-base common contact electrode 50. As a material for the contact electrode, Ti, Al, Mo, Cr, Pt, W, Si, TiC, or an alloy thereof may be used.

  Next, drain electrode 60 is formed on the entire back surface of silicon carbide substrate 10. Thereafter, in order to alloy the source / base common electrode 51 and the drain electrode 60 with the silicon carbide in contact with the silicon carbide, the temperature is 950 to 1000 ° C., the treatment time is 20 to 60 seconds, and the temperature raising rate is increased. Heat treatment is performed at 10 to 25 ° C./second. Thereby, the main part of the element structure of the vertical MOSFET 200 as shown in FIG. 11 is completed.

  According to the present embodiment, the gate electrode 40 made of polycrystalline silicon is made to be p-type by doping impurities of any of group III light elements B, Al, or Ga, and further the implanted dopant is gate-insulated by heat treatment. By diffusing to the vicinity of the interface between the film and the silicon carbide semiconductor layer and using it for passivation of the interface state, the channel mobility can be increased while keeping the gate threshold voltage of the MOSFET sufficiently high. As a result, the on-resistance of the MOSFET can be greatly reduced while ensuring a safe operation as a power device.

Embodiment 3 FIG.
In the silicon carbide MOSFET that is the silicon carbide semiconductor device of the first embodiment and the second embodiment, the gate electrode is formed of polycrystalline silicon containing a p-type dopant composed of B, Al, and Ga that are group III light elements. The gate insulating film is formed of boron phosphorous glass, and boron or phosphorus contained in the gate insulating film may be diffused in the vicinity of the interface between the silicon carbide layer immediately below the gate electrode and the insulating film in the silicon carbide layer. Good.

  In this case, the gate insulating film is formed of boron phosphorous glass, and the gate electrode is different from the first and second embodiments in that the gate electrode does not need to contain an impurity composed of a group III light element. The manufacturing method is the same as in the first and second embodiments. Note that the boron phosphorous glass of the insulating film can be formed using a known manufacturing method.

  Also according to the configuration and the manufacturing method of the present embodiment, a silicon carbide MOSFET that can improve channel mobility can be easily obtained while maintaining a high gate threshold voltage, as in the first and second embodiments. .

  Note that the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications and developments are included within the scope of the technical idea of the present invention.

10 silicon carbide substrate, 20 silicon carbide layer, 21 silicon carbide epitaxial layer, 22 p-type base region, 23,23a n-type source region, 23b n-type drain region, 24 p ⁺⁺ region for p-type base contact, 25 silicon carbide epitaxial Additional growth layer, 30 gate insulating film, 40 gate electrode, 50 source electrode, 51 source / base common electrode, 60 drain electrode, 70 interlayer insulating film, 100,200 silicon carbide MOSFET.

Claims (8)

A silicon carbide substrate;
A silicon carbide layer formed on the silicon carbide substrate and comprising an epitaxial layer and an ion implantation region;
An insulating film formed on the silicon carbide layer;
A gate electrode made of polycrystalline silicon formed at a predetermined position on the silicon carbide layer via the insulating film;
The gate electrode contains either B, Al or Ga as an impurity,
A silicon carbide semiconductor device comprising the impurity in the vicinity of an interface between the silicon carbide layer immediately below the gate electrode and the insulating film. A silicon carbide substrate;
A silicon carbide layer formed on the silicon carbide substrate and comprising an epitaxial layer and an ion implantation region;
An insulating film made of boron phosphorous glass formed on the silicon carbide layer;
A gate electrode formed at a predetermined position on the silicon carbide layer via the insulating film,
A silicon carbide semiconductor device comprising B or P in the insulating film as an impurity in the silicon carbide layer and in the vicinity of an interface between the silicon carbide layer and the insulating film directly under the gate electrode.   3. The silicon carbide semiconductor device according to claim 1, wherein a silicon carbide epitaxial layer is formed on a surface layer immediately below the gate electrode of the silicon carbide layer.   4. The silicon carbide semiconductor device according to claim 1, wherein the impurity is present within a distance of 5 nm or less with respect to the interface. 5. Forming a silicon carbide epitaxial layer on the silicon carbide substrate;
Forming an ion implantation region in the silicon carbide epitaxial layer;
Forming an insulating film on the silicon carbide layer comprising the silicon carbide epitaxial layer and the ion implantation region;
Forming a gate electrode made of polycrystalline silicon containing B, Al or Ga as an impurity at a predetermined position on the silicon carbide layer via the insulating film;
A diffusion step of diffusing the impurities in the vicinity of the interface between the silicon carbide layer and the insulating film directly under the gate electrode;
And a step of performing annealing for activating the impurities. Forming a silicon carbide epitaxial layer on the silicon carbide substrate;
Forming an ion implantation region in the silicon carbide epitaxial layer;
Forming an insulating film made of boron phosphorous glass on the silicon carbide layer made of the silicon carbide epitaxial layer and the ion implantation region;
Forming a gate electrode at a predetermined position on the silicon carbide layer via the insulating film;
A diffusion step of diffusing B or P in the insulating film in the silicon carbide layer and in the vicinity of an interface between the insulating film and the silicon carbide layer;
And a step of performing annealing for activating the impurities.   The silicon carbide semiconductor device according to claim 5, further comprising a step of forming a silicon carbide epitaxial layer as an outermost layer of the silicon carbide layer after the step of forming the ion implantation region. Production method.   8. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein in the diffusion step, the impurity is diffused to a distance of 5 nm or less with respect to the interface.

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