CN105679940A - Bipolar polymer field effect transistor and preparation method and application thereof - Google Patents
Bipolar polymer field effect transistor and preparation method and application thereof Download PDFInfo
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- CN105679940A CN105679940A CN201610244436.4A CN201610244436A CN105679940A CN 105679940 A CN105679940 A CN 105679940A CN 201610244436 A CN201610244436 A CN 201610244436A CN 105679940 A CN105679940 A CN 105679940A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/10—Organic polymers or oligomers
- H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
- H10K85/113—Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
Abstract
The invention discloses a bipolar polymer field effect transistor and a preparation method and an application thereof. The bipolar polymer field effect transistor comprises a substrate, source and drain electrodes, a semiconductor layer, an insulating layer and a grid electrode. The material of the insulating layer is polymethyl methacrylate. The preparation method comprises the following steps of: 1) depositing the source and drain electrodes with patterns on the substrate; 2) coating the substrate, on which the source and drain electrodes are deposited, with a polymer semiconductor in a spinning manner, and obtaining a polymer semiconductor layer; 3) coating the semiconductor layer with polymethyl methacrylate in a spinning manner, and obtaining the insulating layer; 4) depositing the grid electrode on the insulating layer, and obtaining the bipolar polymer field effect transistor. The bipolar polymer field effect transistor is applied to organic electronics and processing of an integrated circuit. According to the invention, the migration rates of both the electrons and the cavities are increased, and the preparation method is simple and easy.
Description
Technical field
The present invention relates to a kind of Bipolar Polymer field-effect transistor and preparation method thereof and application, belong to organic electronics field.
Background technology
Organic/polymer field effect transistor is owing to it is in flexible electronic paper, the huge applications prospect of the aspect such as intelligent cards and flat pannel display, the concern of extremely domestic and international vast researcher. From 1980, organic/polymer semiconducting material, as the important component part of organic/polymer field effect transistor, was always up the emphasis of everybody research. Along with the fast development of donor-receiver conjugated polymer, its hole mobility has reached unprecedented level. But, current most of organic polymer semiconductor material only shows unipolarity, and only seldom a part can be tested to bipolarity; Bipolar semiconductor polymeric material research by the urgent need to because it is very little in logic circuit energy consumption.
It addition, the development of device preparation technology also drives organic/polymer field effect transistor to improve its performance, even show good bipolarity. Consider that the dissolubility of polymer semiconducting material is good, it is possible to the processing preparation of large area solwution method, it has played very critical effect in high performance field effect transistors device and circuit. It is known that the interface between insulating barrier and semiconductor layer is the key point of organic/polymer field effect transistor device performance; Researcher great majority are all go to improve interface (H.Yan from semi-conducting material angle, Z.H.Chen, Y.Zheng, C.Newman, J.R.Quinn, F.Dotz, M.Kastler, A.Facchetti, Nature457 (2009) 679-686), in fact going to change interface from insulating layer material angle is also a good way. Existing seminar attempts using different insulating layer materials to prepare organic/polymer field effect transistor device in the world, although they can unilaterally improve the mobility of a kind of carrier (electronics or hole) by this method, but the mobility (K.J.Baeg of another kind of carrier (hole or electronics) can be reduced to some extent, D.Khim, S.W.Jung, M.Kang, I.K.You, D.Y.Kim, A.Facchetti, Y.Y.Noh, Adv.Mater.24 (2012) 5433-5439;E.J.Meijer, D.M.DeLeeuw, S.Setayesh, E.VanVeenendaal, B.H.Huisman, P.W.M.Blom, J.C.Hummelen, U.Scherf, T.M.Klapwijk, Nat.Mater.2 (2003) 678-682). At present, existing method all can not accomplish to improve the bipolar transmission performance of organic/polymer field effect transistor, namely all can not accomplish that electronics and hole mobility are all improved simultaneously.
Summary of the invention
It is an object of the invention to provide a kind of Bipolar Polymer field-effect transistor and preparation method thereof and application. The electronics of Bipolar Polymer field-effect transistor of the present invention and the mobility in hole are obtained for raising, and its preparation method is simple.
The invention provides a kind of Bipolar Polymer field-effect transistor, it is followed successively by substrate, source-drain electrode, semiconductor layer, insulating barrier, gate electrode from the bottom to top;
The material of described insulating barrier is polymethyl methacrylate.
In above-mentioned transistor, the material of described substrate is silicon chip and/or glass;
The material of described source-drain electrode is gold;
The thickness of described source-drain electrode can be 20～30 nanometers, concretely 20 nanometers or 20～28 nanometers.
In above-mentioned transistor, the thickness of described semiconductor layer can be 30～50 nanometers, concretely 30 nanometers or 30～45 nanometers;
The material of described semiconductor layer is the polymeric material with bipolar nature, specifically, the described polymeric material with bipolar nature is poly-[2, double, two (the 2-octyldodecyl)-1 of 6-, 4, 5, 8-naphthalimide-alt-5, 5 '-two (1, 1 '-Lian two thiophene) thiophene] copolymer and poly-[2, double, two (the 2-octyldodecyl)-1 of 6-, 4, 5, 8-naphthalimide-alt-5, 5 '-two (thiophene-2-bases)-2, 2 '-(trans)-2-(2-(thiophene-2-base) vinyl) thiophene] copolymer, it is called for short P (NDI2OD-T2) and PNVT-8 respectively,
The weight average molecular weight of the material of described semiconductor layer can be 10～100 kilodaltons, concretely 40～70 kilodalton; P (NDI2OD-T2) that described polymer semiconductor specifically adopts and weight average molecular weight respectively 43.4 kilodaltons of PNVT-8 and 64.1 kilodaltons;
The thickness of described insulating barrier can be 850～1000 nanometers, concretely 1000 nanometers or 900～1000 nanometers;
The weight average molecular weight of described polymethyl methacrylate can be 120～1000 kilodaltons, concretely 120 kilodaltons, 550 kilodaltons, 1000 kilodaltons, 120～550 kilodaltons or 550～1000 kilodaltons;
The thickness of described gate electrode can be 80～100 nanometers, concretely 85～100 nanometers or 100 nanometers;
The material of described gate electrode is gold and/or aluminum.
The preparation method that present invention also offers above-mentioned Bipolar Polymer field-effect transistor, comprises the steps: 1) at the figuratum source-drain electrode of deposited on substrates band;
2) in step 1) in deposition have spin on polymers quasiconductor on the substrate of source-drain electrode, obtain polymer semiconductor's layer;
3) in step 2) described in spin coating polymethyl methacrylate on polymer semiconductor's layer, obtain polymethyl methacrylate layers;
4) in step 3) described in gate electrode in polymethyl methacrylate layers, namely obtain Bipolar Polymer field-effect transistor.
In above-mentioned preparation method, step 1) in, described deposition adopts vacuum deposition method; The vacuum of described vacuum evaporation can be 5 × 10-4～8 × 10-4Pa, concretely 8 × 10-4Pa or 6 × 10-4～8 × 10-4Pa;
The speed of described deposition can be 0.5～1.5 angstrom per second, concretely 1 angstrom per second, 0.5～1 angstrom per second or 1～1.5 angstrom per second.
In above-mentioned preparation method, step 1) in, also included described substrate successively through the step of deionized water, ethanol and acetone ultrasonic cleaning post-drying before depositing described source-drain electrode;
Step 1) also include afterwards cleaning with EtOH Sonicate, the step then dried up with high pure nitrogen air gun.
In above-mentioned preparation method, step 2) and 3) in all adopt quasiconductor described in solwution method spin coating and described polymethyl methacrylate, described quasiconductor and described polymethyl methacrylate to be all dissolved in n-butyl acetate.
In the present invention, the preparation of described semiconductor layer and the preparation process of described insulating barrier all complete in the glove box of High Purity Nitrogen atmosphere.
In above-mentioned preparation method, step 2) and 3) in all include the step to described semiconductor layer and described insulating barrier annealing drying, the temperature of described annealing drying can be 90～100 DEG C, concretely 100 DEG C, the time of described annealing drying can be 30～40min, concretely 30min or 30～36min.
In above-mentioned preparation method, step 4) in, described deposition adopts vacuum deposition method; The vacuum of described vacuum evaporation can be 5 × 10-4～8 × 10-4Pa, concretely 8 × 10-4Pa or 5 × 10-4～8 × 10-4Pa;
The speed of described deposition can be 1.5～2.5 angstroms per second, concretely 2 angstroms per second, 1.5～2 angstroms per second or 2～2.5 angstroms per second.
Bipolar Polymer field-effect transistor of the present invention is applied in organic electronics and integrated circuit processing, is particularly applicable in flexible electronic paper, intelligent cards and/or flat faced display.
The invention have the advantages that
1, the present invention has selected the polymethyl methacrylate insulating layer material as preparation polymer field effect transistor device of different molecular weight, and wide material sources and cost are low, thus further reducing the cost of polymer field effect transistor device;
2, the present invention adopts n-butyl acetate as the solvent of polymethyl methacrylate solution; Owing to organic semiconducting materials is not had solvability by n-butyl acetate, it is possible to reach the effect of well " orthogonal solvents ".
3, the preparation method binding soln method process technology of Bipolar Polymer field-effect transistor of the present invention and vacuum evaporation technology, preparation technology is simple, it is easy to preparation processing.
4, the characteristic-bipolarity (i.e. the mobility in electronics and hole) of the polymer field effect transistor prepared by the present invention is obtained for raising.
Accompanying drawing explanation
Fig. 1 is the device architecture schematic diagram adopted in the embodiment of the present invention 1 and embodiment 2.
Fig. 2 is the chemical molecular formula of the P (NDI2OD-T2) in the embodiment of the present invention 1 and polymethyl methacrylate (PMMA), the chemical molecular formula that wherein Fig. 2 a) is P (NDI2OD-T2), the chemical molecular formula that Fig. 2 b) is PMMA.
Fig. 3 by the embodiment of the present invention 2 the chemical molecular formula of employing PNVT-8.
Fig. 4 tests, based on the polymer field effect transistor of P (NDI2OD-T2), the transfer curve obtained in the embodiment of the present invention 1. The transfer curve of polymer field effect transistor test when a molecular weight that () and (b) is polymethyl methacrylate is 120 kilodalton; The transfer curve of polymer field effect transistor test when c molecular weight that () and (d) is polymethyl methacrylate is 550 kilodalton; The transfer curve of polymer field effect transistor test when e molecular weight that () and (f) is polymethyl methacrylate is 1000 kilodalton.
Fig. 5 tests, based on the polymer field effect transistor of PNVT-8, the transfer curve obtained in the embodiment of the present invention 2. The transfer curve of organic field effect tube test when a molecular weight that () and (b) is polymethyl methacrylate is 120 kilodalton; The transfer curve of polymer field effect transistor test when c molecular weight that () and (d) is polymethyl methacrylate is 550 kilodalton; The transfer curve of polymer field effect transistor test when e molecular weight that () and (f) is polymethyl methacrylate is 1000 kilodalton.
Detailed description of the invention
The experimental technique used in following embodiment if no special instructions, is conventional method.
Material used in following embodiment, reagent etc., if no special instructions, all commercially obtain.
The organic field effect tube that embodiment 1, P (NDI2OD-T2) are polymer semiconductor's layer
The first step, the preparation of source-drain electrode:
After corning glass substrate sequentially passes through deionized water, ethanol and acetone ultrasonic cleaning and dries, adopt metal mask method, metal mask plate is covered on corning glass substrate, puts in vacuum coating equipment, vacuum is evacuated to 8 × 10-4Under Pa, the then gold on heating tungsten filament frame evaporation source so that it is, on deposition rate 1 angstrom per second to the corning glass substrate being stamped metal mask plate, to form the golden source-drain electrode that thickness is 20 ran.
Second step, the preparation of polymer semiconductor's layer:
Deposition is had the corning glass substrate of source-drain electrode, dry up after cleaning with EtOH Sonicate, then in the glove box of High Purity Nitrogen atmosphere, utilize sol evenning machine by the o-dichlorobenzene solution of the P (NDI2OD-T2) of 8 milligrams every milliliter, it is spun on its surface with the rotating speed of 2000 rpms, after the thorough spin coating of solution is paved with corning glass substrate, putting into temperature in glove box is anneal 5 minutes in the thermal station of 200 degrees Celsius of constant temperature, then take off and natural cooling, obtain polymer semiconductor's layer that thickness is 30 nanometers.
3rd step, the preparation of insulating barrier (i.e. polymethyl methacrylate layers):
Deposition is had on three corning glass substrates of same source-drain electrode and organic semiconductor layer, utilize sol evenning machine rejection film respectively by the n-butyl acetate solution of polymethyl methacrylate that molecular weight is 120 kilodaltons, 550 kilodaltons and 1000 kilodaltons, it is spun on organic semiconductor layer with the rotating speed of 2000 rpms, putting into temperature in glove box is anneal 30 minutes in the thermal station of 100 degrees Celsius of constant temperature, then take off and natural cooling, obtain the insulating barrier that thickness is 1000 nanometers.
4th step, the preparation of gate electrode:
Adopt masking method to prepare gate electrode, vacuum is evacuated to 8 × 10-4Under Pa, the then aluminum on heating tungsten filament frame evaporation source so that it is, on deposition rate 2 angstroms per second to the corning glass substrate being stamped mask plate, to form the aluminium gate electrode that thickness is 100 nanometers; Namely obtaining with P (NDI2OD-T2) for the Bipolar Polymer field-effect transistor of contact at the bottom of the top-gated of organic semiconductor layer, its structural representation is as shown in Figure 1.
Bipolar Polymer FET device of the present invention is tested:
Under Keithley4200 semi-conductor test instrument, field effect test is carried out with P (NDI2OD-T2) for the Bipolar Polymer field-effect transistor of contact at the bottom of the top-gated of organic semiconductor layer by what prepare; Source-drain voltage is-60 volts, gate voltage is from 10 volts, being scanned according to the grid voltage of (a), (c) in Fig. 4, (e) each curve, test obtains with P (NDI2OD-T2) for contacting the P-channel transfer curve of field-effect transistor at the bottom of the top-gated of semiconductor layer;Source-drain voltage is 60 volts, gate voltage is from-10 volts, being scanned according to the grid voltage of (b), (d) in Fig. 4, (f) each curve, test obtains with P (NDI2OD-T2) for contacting the N-channel transfer curve of field-effect transistor at the bottom of the top-gated of semiconductor layer.
Can be calculated by Fig. 4 and learn that its result data is as shown in table 1 with P (NDI2OD-T2) for contacting the situation of field-effect transistor electronics and hole mobility at the bottom of the top-gated of semiconductor layer.
Table 1P (NDI2OD-T2) is for contacting field-effect transistor electronics and hole mobility at the bottom of the top-gated of semiconductor layer
By table 1 it follows that when using the polymethyl methacrylate of different molecular weight as insulating barrier, increase along with the molecular weight of polymethyl methacrylate, electron mobility and the hole mobility of the polymer field effect transistor prepared based on polymethyl methacrylate and P (NDI2OD-T2) material have raising in various degree all simultaneously, and namely its bipolarity performance is very significantly improved simultaneously.
Embodiment 2, PNVT-8 are the polymer field effect transistor of semiconductor layer
The first step, the preparation of source-drain electrode:
After corning glass substrate sequentially passes through deionized water, ethanol and acetone ultrasonic cleaning and dries, adopt metal mask method, metal mask plate is covered on corning glass substrate, puts in vacuum coating equipment, vacuum is evacuated to 8 × 10-4Under Pa, the then gold on heating tungsten filament frame evaporation source so that it is, on deposition rate 1 angstrom per second to the corning glass substrate being stamped metal mask plate, to form the golden source-drain electrode that thickness is 20 ran.
Second step, the preparation of polymer semiconductor's layer:
Deposition is had the corning glass substrate of source-drain electrode, dry up after cleaning with EtOH Sonicate, then in the glove box of High Purity Nitrogen atmosphere, utilize sol evenning machine by the o-dichlorobenzene solution of the PNVT-8 of 8 milligrams every milliliter, being spun on its surface with the rotating speed of 2000 rpms, after the thorough spin coating of solution is paved with corning glass substrate, putting into temperature in glove box is anneal 5 minutes in the thermal station of 200 degrees Celsius of constant temperature, then take off and natural cooling, obtain polymer semiconductor's layer that thickness is 30 nanometers.
3rd step, the preparation of insulating barrier (i.e. polymethyl methacrylate layers):
Deposition is had on three corning glass substrates of same source-drain electrode and organic semiconductor layer, utilize sol evenning machine rejection film respectively by the n-butyl acetate solution of polymethyl methacrylate that molecular weight is 120 kilodaltons, 550 kilodaltons and 1000 kilodaltons, it is spun on polymer semiconductor's layer with the rotating speed of 2000 rpms, putting into temperature in glove box is anneal 30 minutes in the thermal station of 100 degrees Celsius of constant temperature, then take off and natural cooling, obtain the insulating barrier that thickness is 1000 nanometers.
4th step, the preparation of gate electrode:
Adopt masking method to prepare gate electrode, vacuum is evacuated to 8 × 10-4Under Pa, the then aluminum on heating tungsten filament frame evaporation source so that it is, on deposition rate 2 angstroms per second to the corning glass substrate being stamped mask plate, to form the aluminium gate electrode that thickness is 100 nanometers; Namely obtain with PNVT-8 for the Bipolar Polymer field-effect transistor of contact at the bottom of the top-gated of semiconductor layer.
Inventive polymers FET device is tested:
Under Keithley4200 semi-conductor test instrument, field effect test is carried out with PNVT-8 for the Bipolar Polymer field-effect transistor of contact at the bottom of the top-gated of semiconductor layer by what prepare; Source-drain voltage is-60 volts, gate voltage is from 10 volts, being scanned according to the grid voltage of (a), (c) in Fig. 5, (e) each curve, test obtains with PNVT-8 for contacting the P-channel transfer curve of field-effect transistor at the bottom of the top-gated of semiconductor layer;Source-drain voltage is 60 volts, gate voltage is from-10 volts, being scanned according to the grid voltage of (b), (d) in Fig. 5, (f) each curve, test obtains with PNVT-8 for the N-channel transfer curve of the Bipolar Polymer field-effect transistor of contact at the bottom of the top-gated of semiconductor layer.
Can be calculated by Fig. 5 and learn that its result data is as shown in table 2 with PNVT-8 for contacting the situation of field-effect transistor electronics and hole mobility at the bottom of the top-gated of semiconductor layer.
Table 2 is with PNVT-8 for contacting field-effect transistor electronics and hole mobility at the bottom of the top-gated of semiconductor layer
As can be seen from Table 2: when using the polymethyl methacrylate of different molecular weight as insulating barrier, increase along with the molecular weight of polymethyl methacrylate, electron mobility and the hole mobility of the polymer field effect transistor prepared based on polymethyl methacrylate and PNVT-8 material have raising in various degree all simultaneously, and namely its bipolarity performance is very significantly improved simultaneously.
Claims (10)
1. a Bipolar Polymer field-effect transistor, it is characterised in that: it is followed successively by substrate, source-drain electrode, semiconductor layer, insulating barrier, gate electrode from the bottom to top;
The material of described insulating barrier is polymethyl methacrylate.
2. transistor according to claim 1, it is characterised in that: the material of described substrate is silicon chip and/or glass;
The material of described source-drain electrode is gold;
The thickness of described source-drain electrode is 20～30 nanometers.
3. transistor according to claim 1 and 2, it is characterised in that: the thickness of described semiconductor layer is 30～50 nanometers;
The material of described semiconductor layer is the polymeric material with bipolar nature, specifically, the described polymeric material with bipolar nature is poly-[2, double; two (the 2-octyldodecyl)-1 of 6-, 4,5,8-naphthalimide-alt-5,5 '-two (1,1 '-Lian two thiophene) thiophene] copolymer and poly-[2, double; two (the 2-octyldodecyl)-1 of 6-, 4,5,8-naphthalimide-alt-5,5 '-two (thiophene-2-base)-2,2 '-(trans)-2-(2-(thiophene-2-base) vinyl) thiophene] copolymer;
The weight average molecular weight of the material of described semiconductor layer is 10～100 kilodaltons;
The thickness of described insulating barrier is 850～1000 nanometers;
The weight average molecular weight of described polymethyl methacrylate is 120～1000 kilodaltons;
The thickness of described gate electrode is 80～100 nanometers;
The material of described gate electrode is gold and/or aluminum.
4. the preparation method of the Bipolar Polymer field-effect transistor according to any one of claim 1-3, comprises the steps: 1) at the figuratum source-drain electrode of deposited on substrates band;
2) in step 1) in deposition have spin coating semi-conducting material on the substrate of source-drain electrode, obtain semiconductor layer;
3) in step 2) described in spin coating polymethyl methacrylate on semiconductor layer, obtain insulating barrier;
4) in step 3) described in gate electrode on insulating barrier, namely obtain Bipolar Polymer field-effect transistor.
5. preparation method according to claim 4, it is characterised in that: step 1) in, described deposition adopts vacuum deposition method; The vacuum of described vacuum evaporation is 5 × 10-4～8 × 10-4Pa;
The speed of described deposition be 0.5～1.5 angstrom per second.
6. the preparation method according to claim 4 or 5, it is characterised in that: step 1) in, also included described substrate successively through the step of deionized water, ethanol and acetone ultrasonic cleaning post-drying before depositing described source-drain electrode;
Step 1) also include afterwards cleaning with EtOH Sonicate, the step then dried up with high pure nitrogen air gun.
7. the preparation method according to any one of claim 4-6, it is characterized in that: step 2) and 3) in all adopt quasiconductor described in solwution method spin coating and described polymethyl methacrylate, described quasiconductor and described polymethyl methacrylate to be all dissolved in n-butyl acetate.
8. the preparation method according to any one of claim 4-7, it is characterized in that: step 2) and 3) in all include the step to described semiconductor layer and described insulating barrier annealing drying, the temperature of described annealing drying is 90～100 DEG C, and the time of described annealing drying is 30～40min.
9. the preparation method according to any one of claim 4-8, it is characterised in that: step 4) in, described deposition adopts vacuum deposition method; The vacuum of described vacuum evaporation is 5 × 10-4～8 × 10-4Pa;
The speed of described deposition be 1.5～2.5 angstroms per second.
10. the application in organic electronics and integrated circuit are processed of the Bipolar Polymer field-effect transistor according to any one of claim 1-3.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108288672A (en) * | 2018-01-16 | 2018-07-17 | 华东师范大学 | A kind of preparation method of Organic Thin Film Transistors |
| CN108288672B (en) * | 2018-01-16 | 2020-01-07 | 华东师范大学 | Preparation method of organic thin film transistor |
| CN114300616A (en) * | 2022-01-05 | 2022-04-08 | 南京邮电大学 | Integrated power device based on copolymer organic semiconductor |
| WO2023131037A1 (en) * | 2022-01-05 | 2023-07-13 | 南京邮电大学 | Integrated power device based on copolymer organic semiconductor |
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