WO2023131037A1

WO2023131037A1 - Integrated power device based on copolymer organic semiconductor

Info

Publication number: WO2023131037A1
Application number: PCT/CN2022/143104
Authority: WO
Inventors: 张珺; 郭宇锋; 姚佳飞; 陈静; 李曼
Original assignee: 南京邮电大学; 南京邮电大学南通研究院有限公司
Priority date: 2022-01-05
Filing date: 2022-12-29
Publication date: 2023-07-13
Also published as: CN114300616B; CN114300616A

Abstract

Provided in the present invention is an integrated power device based on a copolymer organic semiconductor. A two-dimensional carrier deceleration area structure is introduced between a gate electrode and a drain electrode, so as to reduce the speed of carriers in a deceleration area in bipolar conduction, such that the probability of the carrier transition between organic molecules is reduced, and the carrier multiplication effect in the copolymer organic semiconductor is inhibited, thereby significantly improving the voltage resistance of a copolymer organic semiconductor device, and increasing a breakdown voltage. During an actual manufacture process, only a source electrode, a drain electrode and a gate electrode require thermal evaporation deposition or magnetron sputtering, and a copolymer organic semiconductor layer and an organic gate dielectric layer can both be prepared by means of spin-coating, such that a process flow is simplified, the preparation is simple, and the cost is low. A copolymer organic semiconductor material serving as a semiconductor layer and an organic dielectric material serving as a gate dielectric layer are decomposed into water and carbon dioxide at a high temperature, and the gate dielectric layer material and the copolymer semiconductor material are non-toxic and harmless, and environmentally friendly, and do not cause secondary pollution of the environment.

Description

An integrated power device based on a copolymer organic semiconductor

technical field

The invention relates to the field of electronic technology, in particular to an integrated power device based on a copolymer organic semiconductor.

Background technique

With the relentless pursuit of power module integration in recent years, power integrated circuits (Power Integrated Circuit, PIC) have also achieved considerable development. Power integrated circuits have gradually developed into power system on chip (Power System On a Chip, PSOC). As a symbolic feature of PIC and PSOC, the performance of power devices has a decisive effect on the frequency characteristics, impedance and power consumption of the entire system. However, traditional integrated power devices based on inorganic semiconductor materials have problems such as high cost, environmental pollution, and high cost of batch processing. Therefore, the preparation of organic power devices with low cost, low pollution, simple process and easy mass production will promote the development of power integrated circuits and power modules.

At present, it is difficult to achieve a good trade-off relationship among cost, performance, environmental pressure and process complexity for integrated power devices based on traditional inorganic semiconductor materials. At the same time, due to the limitations and differences in the working mechanism, material properties and carrier transport mechanism, the traditional withstand voltage technology and structure based on inorganic semiconductor materials and devices cannot be directly transplanted into organic power devices. Specifically, the main reasons are (1) the carrier transport mechanism is different and (2) the impact ionization and withstand voltage mechanisms are different. (1) Since the carrier transport in traditional inorganic semiconductor materials is mainly based on the shared movement of carriers, it means that inorganic materials rely on the order and periodicity of their crystal lattices to make carriers move throughout the semiconductor transmission. In contrast, due to the disorder of copolymer organic semiconductor materials, there are two basic processes in the transport of carriers: intramolecular sharing movement and intermolecular transition movement. For the communalization movement in polymers, the mechanism is similar to that of inorganic materials. However, the transition between molecules is affected by the carrier concentration and speed. In order to ensure that the device has good conduction characteristics, it is necessary to maintain a high carrier, which can only be achieved by reducing the speed. (2) Copolymer organic semiconductor materials are different from the impact ionization process of traditional inorganic semiconductor materials. In traditional inorganic semiconductor impact ionization, electron-hole pairs are generated and further accelerated by the collision of carriers accelerated in the electric field with the crystal lattice. However, the similar lattice structure of inorganic semiconductors does not exist in copolymer semiconductors, so the impact ionization process is more complicated. At the same time, traditional inorganic semiconductor power devices mainly achieve withstand voltage through the depletion of PN junction and low-doped drift region, while copolymer organic semiconductor devices have no stable doping, so they cannot rely on impurity gradients to form PN junctions. Therefore, the withstand voltage structure and technology in traditional inorganic semiconductor devices cannot be directly transplanted to copolymer organic semiconductor devices. Current copolymer organic semiconductor devices still use the traditional field-effect transistor structure, which relies on the channel region to bear the semiconductor withstand voltage, so the withstand voltage performance is far from meeting the application requirements.

Contents of the invention

In view of this, the present invention provides an integrated power device based on a copolymer organic semiconductor, which can greatly improve the withstand voltage performance of the device, surpass the theoretical limit of existing inorganic materials, and enable the device to work stably under high voltage.

The purpose of the present invention is achieved through the following technical solutions:

The invention provides an integrated power device based on a copolymer organic semiconductor, comprising a gate metal electrode (1), a gate dielectric layer (2), an organic semiconductor layer (4), a source metal electrode (3), a drain metal electrode (6) and substrate (5);

Wherein, the material of the gate dielectric layer (2) is an organic insulating material with chemical stability at room temperature, and the material of the organic semiconductor layer (4) is an organic semiconductor copolymer material with chemical stability at room temperature.

The improvement of the present invention is that a part of the organic semiconductor layer (4) constitutes a semiconductor two-dimensional carrier deceleration region (7), specifically, the semiconductor two-dimensional carrier deceleration region (7) refers to In the organic semiconductor layer (4), there is a certain area between the gate metal electrode (1) and the drain metal electrode (6). Therefore, the thickness and length of the semiconductor two-dimensional carrier deceleration region (7) are determined by The organic semiconductor layer (4) where it is located is determined by the thickness and length, and the width is determined by the distance between the gate metal electrode (1) and the drain metal electrode (6).

It should be noted that the PMMA is polymethyl methacrylate, the PS is polystyrene, the PC is polycarbonate, and the NAS is a styrene acrylic acid copolymer;

It should be noted that the P3HT is poly(3-hexylthiophene), the DPPT-TT is polydithiophene-diketopyrrolopyrrole; the N2200 is polynaphthalene-bithiophene;

Preferably, the material of the gate dielectric layer (2) is any one of organic insulating materials PMMA, PS, PC, and NAS;

Preferably, the material of the organic semiconductor layer (4) is any one of P3HT, DPPT-TT, N2200, and pentacene;

Further, the gate metal electrode (1), source metal electrode (3) and drain metal electrode (6) are made of any one of gold, copper, aluminum, nickel, titanium metal materials;

Further, the gate dielectric layer (2) and the organic semiconductor layer (4) are prepared by spin coating or printing.

Further, the substrate (5) is made of glass, flexible plastic, PET flexible substrate, polyimide film, bulk silicon, SOI, silicon carbide, gallium nitride, gallium arsenide, indium phosphide or silicon germanium any of the.

Further, from the perspective of functional classification, the power devices based on copolymer organic semiconductor materials include: lateral field effect transistors, lateral PIN diodes, and lateral Schottky diodes.

The power devices based on copolymer organic semiconductor materials include but are not limited to the following device types in terms of the distribution structure of each functional layer of the device:

As shown in FIG. 1 , it is a three-dimensional structure diagram of an organic power device with a top gate and a bottom contact provided by the present invention. As can be seen from the figure, it deposits a source (3) and a drain (6) on a substrate (5), and spin-coats a semiconductor layer (4) on the source (3) and drain (6). , preparing a gate dielectric layer (2) by spin coating on the semiconductor layer (4), and depositing a grid (1) on the gate dielectric layer (2).

As shown in Figure 2, under the condition that the basic structure remains unchanged, a flexible design is carried out, which is a three-dimensional structure diagram of a top-gate top-contact organic power device. As can be seen from the figure, it first spin-coats the semiconductor layer (4) on the substrate (5), then deposits the source (3) and the drain (6) on the semiconductor layer (4), and the source ( 3) and the drain (6) are spin-coated to prepare a gate dielectric layer (2), and a gate (1) is deposited on the gate dielectric layer (2).

As shown in Figure 3, under the condition that the basic structure remains unchanged, a flexible design is carried out, which is a three-dimensional structure diagram of a bottom-gate and bottom-contact organic power device. As can be seen from the figure, it first deposits the gate (1) on the substrate (5), spin-coats the gate dielectric layer (2) on the gate (1), and deposits the source on the gate dielectric layer (2). The electrode (3) and the drain (6) are spin-coated on the source (3) and the drain (6) to prepare the semiconductor layer (4).

As shown in Figure 4, under the condition that the basic structure remains unchanged, a flexible design is carried out, which is a three-dimensional structure diagram of a bottom-gate top-contact organic power device. As can be seen from the figure, it first deposits the grid (1) on the substrate (5), spin-coats the gate dielectric layer (2) on the grid (1), spin-coats the gate dielectric layer (2) A semiconductor layer (4) is prepared, and a source (3) and a drain (6) are deposited on the semiconductor layer (4).

The main advantages of the present invention are:

1. The two-dimensional carrier deceleration region provided by the present invention can significantly improve the withstand voltage capability of the device. The two-dimensional carrier deceleration region uses the characteristics of different degrees of self-assembly between the interior and the surface of the copolymer organic body, so that it can be close to the substrate surface and far away from the substrate surface. The copolymer semiconductor at the surface of the substrate exhibits different properties in terms of conductivity and withstand voltage, thus introducing a two-dimensional withstand voltage effect, which reduces the carrier transition probability between polymers near the surface through the two-dimensional charge sharing effect , which reduces the impact ionization rate, reduces the reverse leakage current in the case of shutdown, and improves the breakdown voltage and FOM value.

2. The structure of the two-dimensional carrier deceleration region effectively suppresses the bipolar conduction effect of the copolymer organic semiconductor during forward conduction, and avoids the reverse shutdown caused by bipolar conduction in traditional organic field effect transistors. Obvious leakage when off.

3. The metal electrode is prepared by thermal evaporation deposition method or magnetron sputtering method, and the gate dielectric layer and semiconductor layer are prepared by spin coating method. Compared with traditional organic field effect transistors, no additional mask plate is required, no high-temperature process technology is required, the process flow is simplified, the preparation is simple, and the material cost and process manufacturing cost are low.

4. The semiconductor layer and the gate dielectric material are organic matter, which decomposes into water and carbon dioxide at high temperature, which is environmentally friendly and will not cause secondary pollution.

Description of drawings

Figure 1 is a three-dimensional structure diagram of an organic power device with a top-gate-bottom contact provided by the present invention, in Figure 1: 1-gate metal, 2-gate dielectric layer, 3-source metal, 4-semiconductor layer, 5-substrate Bottom, 6-drain metal, 7-semiconductor two-dimensional carrier deceleration region;

Fig. 2 is a three-dimensional structure diagram of an organic power device with top gate and top contact provided by the present invention;

In Figure 2: 1-gate metal, 2-gate dielectric layer, 3-source metal, 4-semiconductor layer, 5-substrate, 6-drain metal, 7-semiconductor two-dimensional carrier deceleration region;

Fig. 3 is a three-dimensional structure diagram of an organic power device with a bottom gate and a top contact provided by the present invention,

In Figure 3: 1-gate metal, 2-gate dielectric layer, 3-source metal, 4-semiconductor layer, 5-substrate, 6-drain metal, 7-semiconductor two-dimensional carrier deceleration region;

Fig. 4 is a three-dimensional structure diagram of an organic power device with bottom gate and bottom contact provided by the present invention,

In Figure 4: 1-gate metal, 2-gate dielectric layer, 3-source metal, 4-semiconductor layer, 5-substrate, 6-drain metal, 7-semiconductor two-dimensional carrier deceleration region;

Fig. 5 is the breakdown characteristic graph of the device prepared in the embodiment 1-4 of the present invention and comparative example;

Fig. 6 is the transfer characteristic graph of the device prepared in the embodiment of the present invention 1-4 and comparative example;

Fig. 7 is a SEM picture of the interface between PMMA and DPPT-TT layer in Example 1 of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but the present invention is not limited to these embodiments. The present invention covers any alternatives, modifications, equivalent methods and schemes made on the spirit and scope of the present invention. In order for the public to have a thorough understanding of the present invention, specific details are specified in the following embodiments of the present invention, and those skilled in the art can fully understand the present invention without the description of these details.

Example 1:

As shown in FIG. 1 , it is a three-dimensional structure diagram of an organic power device with top-gate and bottom-contact provided by the present invention. It can be seen from the figure that the source electrode 3 and the drain electrode 6 are deposited on the substrate 5, the material used for the source and drain is nickel aluminum alloy, and the substrate material is a glass substrate produced by Corning Corporation of the United States. The semiconductor layer 4 is prepared by spin coating on the source 3 and the drain 6, the gate dielectric layer 2 is prepared by spin coating on the semiconductor layer 4, the gate 1 is deposited on the gate dielectric layer 2, and the gate 1 is realized by photolithography overlay. The precise control of the distance between the drain electrode 6 and the drain electrode 6 forms a two-dimensional carrier deceleration region with a width of 7.6 microns, that is, L _d =7.6 μm;

Specifically, the preparation process of an organic power device with a top-gate-bottom contact in Example 1 is as follows:

The raw materials are butyl acetate solvent (NBA) and 1-2 dichlorobenzene solvent (DCB) from Sigma Aldrich, DPPT-TT from Nanjing Zhiyan Technology Co., Ltd., ultrafine PMMA powder from Shanghai Hansi Chemical Co., Ltd.; PMMA solution The concentration is 80mg/ml, and the solvent is NBA. The concentration of DPPT-TT solution is 5mg/ml, and the solvent is DCB.

The rotation speed of the DPPT-TT solution spin coating is configured as follows: 500 rotations per minute for 10 seconds, and then 1500 rotations per minute for 60 seconds. The annealing temperature is 80°C for 5 minutes, then 150°C for 1 hour;

The rotation speed of PMMA solution spin coating is configured as follows: 500 rotations per minute for 3 seconds, and then 1500 rotations per minute for 60 seconds. The annealing temperature is 80° C. for 2 hours.

The thickness of DPPT-TT is 50nm, and the thickness of PMMA is 800nm.

Fig. 7 is the SEM image of the interface between PMMA and DPPT-TT layer formed by the device prepared according to embodiment 1. As shown in Fig. 7, the surface morphology of this section is better, and the copolymer organic semiconductor material at the surface and in the body Anisotropic.

Example 2:

Except that the length of the two-dimensional carrier deceleration region is different, other structures are exactly the same as in embodiment 1. In embodiment 2, the two-dimensional carrier deceleration region is a two-dimensional carrier deceleration region with a width of 10.4 microns, that is, L _d =10.4 μm. area; and except that the layout structure used in the photolithographic overlay step is different, other manufacturing steps are the same as in Embodiment 1.

Example 3:

Except that the length of the two-dimensional carrier deceleration region is different, the other structures are exactly the same as in embodiment 1. In embodiment 2, the two-dimensional carrier deceleration region is a two-dimensional carrier deceleration region with a width of 11.2 microns, that is, L _d =11.2 μm. area; and except that the layout structure used in the photolithographic overlay step is different, other manufacturing steps are the same as in Embodiment 1.

Example 4:

Except that the length of the two-dimensional carrier deceleration region is different, the other structures are exactly the same as in embodiment 1. In embodiment 2, the two-dimensional carrier deceleration region is a two-dimensional carrier deceleration region with a width of 20.2 microns, that is, L _d =20.2 μm. area; and except that the layout structure used in the photolithographic overlay step is different, other manufacturing steps are the same as in Embodiment 1.

Comparative example 1:

Except that there is no two-dimensional carrier deceleration zone, that is, L _d =0 μm, the other structures are exactly the same as in Example 1; and except that the layout structure used in the photolithography step is different, other manufacturing steps are the same as in Example 1.

Test case 1:

Fig. 5 is the breakdown characteristic curve diagram of the organic power device of the top gate bottom contact prepared in Example 1-4 and Comparative Example 1; As can be seen from Fig. 5, with the increase of the length of the two-dimensional carrier deceleration region , the withstand voltage of the device is significantly improved.

This test is a slide test, the semiconductor test analyzer used is keysight B1505A, and the probe station is Taiwan Yiye CG-196 high and low temperature probe station. Tests were performed at room temperature. The test software is the self-contained software of the semiconductor test analyzer.

Test case 2:

FIG. 6 is a graph showing the transfer characteristics of top-gate and bottom-contact organic power devices prepared in Examples 1-4 and Comparative Example 1. FIG. It can be seen from Figure 6 that with the appearance of the two-dimensional carrier deceleration region, the ambipolar conduction of the copolymer semiconductor material is suppressed, so that the leakage current under the reverse gate voltage is significantly suppressed. This test is a slide test, the semiconductor test analyzer used is keysight B1505A, and the probe station is Taiwan Yiye CG-196 high and low temperature probe station. Tests were performed at room temperature. The test software is the self-contained software of the semiconductor test analyzer.

Working principle of the present invention:

Taking the device structure in Fig. 1 as an example, the working mechanism of the present invention is analyzed. As can be seen from Figure 5, comparing the two-dimensional carrier deceleration region without semiconductor, the two-dimensional carrier deceleration region with 7.6 microns, the two-dimensional carrier deceleration region with 10.4 microns, and the two-dimensional carrier The breakdown voltage of the deceleration zone and the five devices with a 20.2-micron two-dimensional carrier deceleration zone, except for the length of the two-dimensional carrier deceleration zone, all three devices have the same size. The breakdown voltage of the device without semiconductor two-dimensional carrier deceleration region is about 280V, the breakdown voltage of the device with 7.6 micron two-dimensional carrier deceleration region is about 850V, and the breakdown voltage of the device with 10.4 micron is about 1250V, with The device breakdown voltage of the 11.2-micron two-dimensional carrier deceleration region is about 1370V, and the device breakdown voltage of the 20.2-micron two-dimensional carrier deceleration region is about 2280V.

When there is no two-dimensional carrier deceleration region, the carrier multiplication effect will occur in the organic semiconductor region under high voltage, thereby generating a large number of electron-hole pairs, which are accelerated by the external electric field and further produce avalanche breakdown, resulting in It is difficult for the device to withstand large voltages. When the semiconductor two-dimensional carrier deceleration region is added, a two-dimensional withstand voltage structure is introduced into the gate and drain, affected by the two-dimensional charge sharing effect, the avalanche multiplication effect in the drift region is significantly suppressed, and the device withstand voltage The performance is improved. As the distance and thickness of the drift region increase, the breakdown voltage also increases.

The present invention introduces a two-dimensional carrier deceleration region into the semiconductor layer of the device to increase the area between the gate and the drain, thereby suppressing the avalanche multiplication effect, greatly increasing the withstand voltage performance of the device, and improving the reverse voltage of the device. breakdown voltage. In the device fabrication process, only the source-drain electrodes and gate electrodes need to be deposited by thermal evaporation, and the semiconductor layer and gate dielectric layer can be prepared by spin coating, which has the advantages of simple process and low cost.

Claims

An integrated power device based on a copolymer organic semiconductor, comprising a gate metal electrode (1), a gate dielectric layer (2), an organic semiconductor layer (4), a source metal electrode (3), and a drain metal electrode (6) and the substrate (5); the material of the gate dielectric layer (2) is an organic insulating material with chemical stability at room temperature; the material of the organic semiconductor layer (4) is an organic semiconductor with chemical stability at room temperature Copolymer material; it is characterized in that part of the organic semiconductor layer (4) constitutes a semiconductor two-dimensional carrier deceleration region (7), specifically, the semiconductor two-dimensional carrier deceleration region (7) refers to A certain area in the organic semiconductor layer (4) is located between the gate metal electrode (1) and the drain metal electrode (6).
An integrated power device based on a copolymer organic semiconductor according to claim 1, wherein the material of the gate dielectric layer (2) is any one of organic insulating materials PMMA, PS, PC, and NAS kind.
An integrated power device based on a copolymer organic semiconductor according to claim 1, wherein the material of the organic semiconductor layer (4) is copolymer P3HT, DPPT-TT, N2200, pentacene any kind.
A kind of integrated power device based on copolymer organic semiconductor according to claim 1, characterized in that, the material of the gate metal electrode (1) source metal electrode (3) and drain metal electrode (6) Any one of gold, copper, aluminum, nickel, titanium metal materials.
An integrated power device based on a copolymer organic semiconductor according to claim 1, wherein the substrate (5) is made of glass, flexible plastic, PET flexible substrate, polyimide film, bulk silicon , SOI, silicon carbide, gallium nitride, gallium arsenide, indium phosphide or any one of silicon germanium materials.
An integrated power device based on a copolymer organic semiconductor according to claim 1, wherein the specific form of the integrated power device includes a lateral field effect transistor, a lateral PIN diode, and a lateral Schottky diode.
An integrated power device based on a copolymer organic semiconductor according to claim 1, characterized in that the width of the semiconductor two-dimensional carrier deceleration region (7) ranges from 7.6 microns to 20.2 microns.
An integrated power device based on a copolymer organic semiconductor according to claim 7, characterized in that the width of the two-dimensional carrier deceleration region (7) of the semiconductor is 11.2 microns.
An integrated power device based on a copolymer organic semiconductor according to claim 7, characterized in that the width of the two-dimensional carrier deceleration region (7) of the semiconductor is 10.4 microns.
An integrated power device based on a copolymer organic semiconductor according to claim 1, wherein the integrated power device is an organic power device with a top-gate-bottom contact, and the gate dielectric layer (2) is located on the gate metal Below the electrode (1), the organic semiconductor layer (4) is located below the gate dielectric layer (2), the source metal electrode (3) and the drain metal electrode (6) are located in the organic semiconductor layer (4), and the bottom is Substrate (5).