CN110265548B - Indium-doped N-type organic thin film transistor and preparation method thereof - Google Patents
Indium-doped N-type organic thin film transistor and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an indium-doped N-type organic thin film transistor and a preparation method thereof. The preparation method comprises the steps of firstly preparing a layer of gold as a source electrode and a drain electrode on a glass substrate through a mask, then preparing a layer of indium as a doping layer on a gold electrode, then forming an N-type organic semiconductor active layer on the surface of a sample with the prepared electrode by a sol-gel method, spin-coating a layer of dielectric material on the active layer to serve as an insulating layer, and finally preparing aluminum on the surface of the insulating layer through the mask to form a gate electrode. Compared with the traditional organic thin film transistor, the organic thin film transistor prepared by the method has the advantages that the switching ratio and the carrier mobility are obviously improved, and the sub-threshold swing amplitude and the threshold voltage of the device are greatly reduced. The invention improves the electrical property of the N-type organic thin film transistor with the top-gate bottom-contact structure, and has the characteristics of low cost, simple process steps and wide application in the N-type organic thin film transistor.
Description
Technical Field
The invention relates to the fields of microelectronic materials and device technology, information display and the like, in particular to an indium-doped N-type organic thin film transistor and a preparation method thereof.
Background
The use of organic semiconductors as active layers in thin film transistors has gained widespread interest over the last three decades, and organic thin film transistors with conjugated polymers, oligomers and fused aromatics as the semiconducting material have particular advantages over field effect transistors using inorganic semiconductors, such as the fabrication of new thin film transistors that are large area, flexible, low temperature processing (near room temperature), low cost and transparent. The organic thin film transistor can be applied to the fields of active matrix flat panel display, organic electroluminescent diode and 'electronic paper' display, attachable sensors, radio frequency identification tags and the like.
Since organic semiconductor materials are difficult to inject electrons and are easily interfered by moisture and oxygen in the air, the development of N-type organic semiconductor materials is far behind that of P-type organic semiconductor materials. P-type organic transistors have higher on-off ratios and mobilities, as well as lower sub-threshold swings, threshold voltages, and contact resistances compared to N-type organic transistors. However, the lack of N-type semiconductor materials with high mobility, air stability, and solution-fabricable processes has greatly limited the development of organic thin film transistor-based flexible electronic devices and organic integrated circuits.
The preparation of N-type organic thin film transistors with excellent performance is a crucial step in the development of organic thin film transistors. The method for changing the molecular structure or replacing chemical elements of organic semiconductor materials is generally adopted internationally to improve the performance of the N-type organic semiconductor, the method can enable the electrical performance of the N-type organic thin film transistor to be close to that of a P-type organic thin film transistor, the process is simple, the cost is low, the applicability is wide, and the development of the N-type organic thin film transistor is greatly promoted.
Disclosure of Invention
In view of this, the present invention provides an indium-doped N-type organic thin film transistor and a method for fabricating the same. The organic thin film transistor applicable to the preparation method is of a top-gate-bottom contact structure, and the transistor sequentially comprises a gate electrode, a dielectric layer, an N-type semiconductor active layer, a source/drain electrode and a substrate from top to bottom. According to the method, after the preparation of the source/drain electrode of the organic thin film transistor is finished, the doping layer is formed on the surface of the source/drain electrode in a mask alignment mode, and the N-type organic thin film transistor is subjected to contact doping through the doping layer, so that the electrical property of the N-type organic thin film transistor is improved.
The invention provides a preparation method of an indium-doped N-type organic thin film transistor, which comprises the following specific steps of:
step 1: preparation of the solution
A1: preparation of semiconductor solution
Preparing an N-type organic semiconductor material and an organic solvent according to the mass-to-volume ratio of 8 mg/ml; wherein the N-type organic semiconductor material is: [ N, N ' -bis (2-octyldodecyl) -1,4,5, 8-naphthalimide-2, 6-diyl-and-5, 5 ' - (2,2 ' -bithiophene) ] polymer (N2200); the organic solvent is chlorobenzene or p-dichlorobenzene;
a2: preparation of insulating layer solution
Preparing an insulating layer material and a high-solubility organic solvent according to a mass-volume ratio of 80 mg/ml; wherein the insulating layer is made of high molecular polymer; the high-solubility organic solvent is acetic acid or methyl acetate;
a3: dissolution of the solution
Respectively placing the prepared semiconductor solution and the insulating layer solution on a heating plate, standing and dissolving for 24 hours at 60 ℃;
step 2: preparation of devices
B1: cleaning of substrates
Selecting an insulating substrate, sequentially placing the substrate in deionized water, acetone and alcohol, respectively cleaning for 10 minutes by using an ultrasonic cleaning machine, and then drying by using a nitrogen gun;
b2: preparation of source-drain electrode
Adopting vacuum thermal evaporation coating technology, and performing vacuum 10-5～10-4Under the condition of Pa, gold with the thickness of 30 nanometers is evaporated on the substrate by using a stainless steel mask as a source drain electrode; wherein the thermal evaporation current is 100-160A, and the speed is 0.01-0.05 nm/s;
b3: preparation of doped layers
Adopting vacuum thermal evaporation coating technology, and performing vacuum 10-5～10-4Under the condition of Pa, evaporating and plating indium with the thickness of 5-15 nanometers on the surface of the source and drain electrodes by using a stainless steel mask as a doping layer; wherein the thermal evaporation current is 60-100A, and the speed is 0.01-0.02 nm/s.
B4: preparation of semiconductor thin films
Spreading the prepared semiconductor solution on the upper surface of the substrate by a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm by using a spin coater and then for 40-80 seconds at the rotating speed of 2000 rpm; placing the sample on a heating plate to be heated and annealed at 110 ℃ for 20 minutes in a pure argon environment, wherein the semiconductor layer is coated in a spinning mode in the step; the thickness range of the prepared semiconductor film is 35-45 nanometers, and the semiconductor film is an active layer.
B5: preparation of insulating layer film
Spreading the prepared insulating layer solution on the upper surface of the semiconductor film through a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm and then 60 seconds at the rotating speed of 2000rpm by adopting a spin coater; placing the sample with the insulating layer coated in a spinning mode in the step on a heating plate in a pure argon environment, and heating and annealing the sample for 2 hours at the temperature of 80 ℃;
b6: preparation of grid electrode
And through the calibration of an optical microscope, enabling the opening position of the stainless steel mask plate to correspond to a channel between the source electrode and the drain electrode, and preparing aluminum with the thickness of 60 nanometers on the upper surface of the insulating layer by utilizing a vacuum thermal evaporation coating technology to serve as a gate electrode to obtain the indium-doped N-type organic thin film transistor.
In step A2, the high molecular polymer is polymethacrylate, polystyrene or perfluoro (1-butyl vinyl ether) polymer, and has a contact angle of at least 90 degrees with water.
In step B1, the insulating substrate is glass, silicon dioxide or poly-p-phthalic plastic.
Compared with the traditional organic thin film transistor, the organic thin film transistor prepared by the method has the advantages that the on-off ratio and the carrier mobility of the device are obviously improved, and the sub-threshold swing amplitude and the threshold voltage of the device are greatly reduced. The invention improves the electrical property of the N-type organic thin film transistor with the top-gate bottom-contact structure, and has the characteristics of low cost, simple process steps and wide application in the N-type organic thin film transistor.
Drawings
FIG. 1 is a schematic cross-sectional structure of a comparative example N-type organic thin film transistor;
FIG. 2 is a schematic cross-sectional structure diagram of an indium-doped N-type organic thin film transistor fabricated by the method of the present invention;
FIG. 3 is a graph comparing transfer characteristics of an undoped conventional method and an N-type organic thin film transistor fabricated by the method of the present invention.
Detailed Description
According to the invention, a dense indium doped layer with controllable thickness is prepared on the upper surface of the electrode under the self-alignment of the mask by the traditional electrode preparation process. The indium can effectively reduce the Schottky barrier height formed by the contact of the source electrode, the drain electrode and the N-type organic semiconductor because of the lower work function of the indium, is favorable for the transmission of electrons between interfaces, and can carry out electron doping on a semiconductor active layer on the premise of not damaging the molecular structure of the semiconductor active layer, thereby increasing the carrier concentration of an N-type organic semiconductor film, so that the on-off ratio and the mobility of the organic film transistor are obviously improved, and the subthreshold swing amplitude and the threshold voltage of the organic film transistor are obviously reduced. Therefore, the electrical property of the N-type organic thin film transistor can be greatly improved through the invention.
The invention is further explained below with reference to the drawings and the embodiments.
The following description of the preferred embodiments of the present invention is provided for illustration, but should not be construed as limiting the invention to the embodiments set forth herein, and all equivalent changes and modifications that fall within the spirit and scope of the present invention are intended to be embraced therein.
Fig. 2 is a schematic diagram of an idealized embodiment of the present invention, which should not be considered limited to the specific shape of the regions shown in the figures. In the present embodiments, all are represented by rectangles, and the representation in the figures is schematic, but this should not be construed as limiting the scope of the invention.
Comparative example
Undoped conventional organic thin film transistor fabrication
A1: preparation of semiconductor solution
Preparing an N-type organic semiconductor material and an organic solvent according to the mass-to-volume ratio of 8 mg/ml; wherein the N-type organic semiconductor material is: [ N, N ' -bis (2-octyldodecyl) -1,4,5, 8-naphthalimide-2, 6-diyl-and-5, 5 ' - (2,2 ' -bithiophene) ] polymer (N2200); the organic solvent is chlorobenzene;
a2: preparation of insulating layer solution
Preparing an insulating layer material and a high-solubility organic solvent according to a mass-volume ratio of 80 mg/ml; wherein the insulating layer material is Polymethacrylate (PMMA); the high-solubility organic solvent is methyl acetate;
a3: dissolution of the solution
Respectively placing the prepared semiconductor solution and the insulating layer solution on a heating plate, standing and dissolving for 24 hours at 60 ℃;
step 2: preparation of devices
B1: cleaning of substrates
Selecting an insulating substrate, sequentially placing the substrate in deionized water, acetone and alcohol, respectively cleaning for 10 minutes by using an ultrasonic cleaning machine, and then drying by using a nitrogen gun;
b2: preparation of source-drain electrode
Adopts a vacuum thermal evaporation coating technology under the vacuum condition (10)-4Pa) evaporating gold with the thickness of 30 nanometers on the substrate by using a stainless steel mask as a source-drain electrode; wherein the thermal evaporation current is 100-160A, and the speed is 0.01-0.05 nm/s;
b3: preparation of semiconductor thin films
Spreading the prepared semiconductor solution on the upper surface of the substrate by a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm by using a spin coater and then for 40-80 seconds at the rotating speed of 2000 rpm; placing the sample on a heating plate to be heated and annealed at 110 ℃ for 20 minutes in a pure argon environment, wherein the semiconductor layer is coated in a spinning mode in the step; the thickness range of the prepared semiconductor film is 35-45 nanometers, and the semiconductor film is an active layer.
B4: preparation of insulating layer film
Spreading the prepared insulating layer solution on the upper surface of the semiconductor film through a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm and then 60 seconds at the rotating speed of 2000rpm by adopting a spin coater; placing the sample with the insulating layer coated in a spinning mode in the step on a heating plate in a pure argon environment, and heating and annealing the sample for 2 hours at the temperature of 80 ℃;
b5: preparation of grid electrode
And (3) by calibrating an optical microscope, enabling the opening position of the stainless steel mask plate to correspond to a channel between the source electrode and the drain electrode, and preparing aluminum with the thickness of 60 nanometers on the upper surface of the insulating layer by utilizing a vacuum thermal evaporation coating technology to serve as a gate electrode to obtain the traditional N-type organic thin film transistor.
As shown in fig. 1, fig. 1 is a schematic cross-sectional structure of a conventional N-type organic thin film transistor manufactured according to a comparative example.
Examples
A1: preparation of semiconductor solution
Preparing an N-type organic semiconductor material and an organic solvent according to the mass-to-volume ratio of 8 mg/ml; wherein the N-type organic semiconductor material is: [ N, N ' -bis (2-octyldodecyl) -1,4,5, 8-naphthalimide-2, 6-diyl-and-5, 5 ' - (2,2 ' -bithiophene) ] polymer (N2200); the organic solvent is chlorobenzene;
a2: preparation of insulating layer solution
Preparing an insulating layer material and a high-solubility organic solvent according to a mass-volume ratio of 80 mg/ml; wherein the insulating layer material is Polymethacrylate (PMMA); the high-solubility organic solvent is methyl acetate;
a3: dissolution of the solution
Respectively placing the prepared semiconductor solution and the insulating layer solution on a heating plate, standing and dissolving for 24 hours at 60 ℃;
step 2: preparation of devices
B1: cleaning of substrates
Selecting an insulating substrate, sequentially placing the substrate in deionized water, acetone and alcohol, respectively cleaning for 10 minutes by using an ultrasonic cleaning machine, and then drying by using a nitrogen gun;
b2: preparation of source-drain electrode
Adopts a vacuum thermal evaporation coating technology under the vacuum condition (10)-4Pa) evaporating gold with the thickness of 30 nanometers on the substrate by using a stainless steel mask as a source-drain electrode; wherein the thermal evaporation current is 100-160A, and the speed is 0.01-0.05 nm/s;
b3: preparation of doped layers
Adopts a vacuum thermal evaporation coating technology under the vacuum condition (10)-4Pa) utilization ofThe method comprises the following steps that indium with the thickness of 5-15 nanometers is evaporated on the surface of a source electrode and a drain electrode by a stainless steel mask plate to serve as a doping layer; wherein the thermal evaporation current is 60-100A, and the speed is 0.01-0.02 nm/s.
B4: preparation of semiconductor thin films
Spreading the prepared semiconductor solution on the upper surface of the substrate by a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm by using a spin coater and then for 40-80 seconds at the rotating speed of 2000 rpm; placing the sample on a heating plate to be heated and annealed at 110 ℃ for 20 minutes in a pure argon environment, wherein the semiconductor layer is coated in a spinning mode in the step; the thickness range of the prepared semiconductor film is 35-45 nanometers, and the semiconductor film is an active layer.
B5: preparation of insulating layer film
Spreading the prepared insulating layer solution on the upper surface of the semiconductor film through a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm and then 60 seconds at the rotating speed of 2000rpm by adopting a spin coater; placing the sample with the insulating layer coated in a spinning mode in the step on a heating plate in a pure argon environment, and heating and annealing the sample for 2 hours at the temperature of 80 ℃;
b6: preparation of grid electrode
And (3) enabling the opening position of the stainless steel mask plate to correspond to a channel between the source electrode and the drain electrode through calibration of an optical microscope, and preparing aluminum with the thickness of 60 nanometers on the upper surface of the insulating layer by utilizing a vacuum thermal evaporation coating technology to serve as a gate electrode to obtain the indium-doped N-type organic thin film transistor.
As shown in fig. 2, fig. 2 is a schematic cross-sectional structure diagram of the indium-doped N-type organic thin film transistor prepared in the present embodiment;
FIG. 3 is a graph comparing the transfer characteristics in the saturation region of the organic thin film transistors obtained in the comparative example and the example. Referring to fig. 3, the transistor prepared according to the embodiment has a greatly improved saturation region transfer characteristic. To account for the changes in specific electrical parameters, table 1 lists the electrical parameters of the switching ratio, mobility, subthreshold swing, and threshold voltage of the two devices. For an undoped conventional organic thin film transistor, the switching ratio is 104Mobility of 0.116 square centimeter/(volt-second) and subthreshold swing of2.67 volts per unit order of magnitude, with a threshold voltage of 7.25 volts, and a switching ratio of 2 x 10 for doped organic thin film transistors5The mobility was 0.356 square centimeters/(volt · s), the subthreshold swing was 0.87 volts per unit order of magnitude, and the threshold voltage was 0.18 volts. Therefore, the core electrical parameter indexes of the four transistors can be observed, the electrical performance of the N-type organic thin film transistor prepared by the method is obviously improved, and the method has very important significance for further development of the N-type organic thin film transistor.
The contact regulation effect of the indium doped layer on the source/drain electrodes and the N-type semiconductor active layer and the electron injection effect on the N-type organic semiconductor are main reasons for promoting the optimization of the transistor performance. In fact, the N-type semiconductor material with high mobility, air stability and solution-based preparation is in short supply, and the performance of the undoped traditional N-type organic thin film transistor is obviously lagged behind that of the P-type organic thin film transistor, thereby greatly limiting the development of flexible electronic devices and organic integrated circuits based on the organic thin film transistor. The electrode surface work function of the N-type organic thin film transistor doped by the method is close to the LUMO energy level of the N-type organic semiconductor, so that the Schottky barrier between a source electrode and a drain electrode and the semiconductor is reduced, and the electron drift is facilitated; and the indium has the function of electron doping injection to the semiconductor, so that the carrier concentration in a channel is increased, and the electrical property of the N-type organic thin film transistor is remarkably improved. Referring to table 1, it can be seen that the carrier mobility of the transistor switch prepared by the present invention is improved to 3 times that of the conventional device compared to 20 times that of the device prepared by the conventional method, and the sub-threshold swing and the threshold voltage of the transistor switch are both significantly reduced.
Therefore, the invention can solve the problem that the performance of the N-type organic thin film transistor is far behind that of the P-type organic thin film transistor, greatly improves various electrical properties of the N-type organic thin film transistor, and has very important significance for realizing large-scale commercial application of the organic thin film transistor.
TABLE 1
| Electrical parameters of organic thin film transistor | Before doping | After doping |
| On-off ratio | 104 | 2×105 |
| Mobility (square centimeter/(volt second) | 0.116 | 0.356 |
| Subthreshold swing (volt/unit magnitude) | 2.67 | 0.87 |
| Threshold voltage (volt) | 7.25 | 1.18 |
Claims (2)
1. A preparation method of an indium-doped N-type organic thin film transistor is characterized by comprising the following specific steps:
step 1: preparation of the solution
A1: preparation of semiconductor solution
Preparing an N-type organic semiconductor material and an organic solvent according to the mass-to-volume ratio of 8 mg/ml; wherein the N-type organic semiconductor material is: [ N, N ' -bis (2-octyldodecyl) -1,4,5, 8-naphthalimide-2, 6-diyl-and-5, 5 ' - (2,2 ' -bithiophene) ] polymer (N2200); the organic solvent is chlorobenzene or p-dichlorobenzene;
a2: preparation of insulating layer solution
Preparing an insulating layer material and a high-solubility organic solvent according to a mass-volume ratio of 80 mg/ml; the insulating layer is made of high-molecular polymer, and the high-solubility organic solvent is acetic acid or methyl acetate;
a3: dissolution of the solution
Respectively placing the prepared semiconductor solution and the insulating layer solution on a heating plate, standing and dissolving for 24 hours at 60 ℃;
step 2: preparation of devices
B1: cleaning of substrates
Selecting an insulating substrate, sequentially placing the substrate in deionized water, acetone and alcohol, respectively cleaning for 10 minutes by using an ultrasonic cleaning machine, and then drying by using a nitrogen gun;
b2: preparation of source-drain electrode
Adopting vacuum thermal evaporation coating technology, and performing vacuum 10-5~10-4 Under the condition of Pa, gold with the thickness of 30 nanometers is evaporated on the substrate by using a stainless steel mask as a source drain electrode; wherein the thermal evaporation current is 100-160A, and the speed is 0.01-0.05 nm/s;
b3: preparation of doped layers
Adopting vacuum thermal evaporation coating technology, and performing vacuum 10-5~10-4 Under the condition of Pa, evaporating and plating indium with the thickness of 5-15 nanometers on the surface of the source and drain electrodes by using a stainless steel mask as a doping layer; wherein, the thermal evaporation current is 60-100A, and the speed is 0.01-0.02 nm/s;
b4: preparation of semiconductor thin films
Spreading the prepared semiconductor solution on the upper surface of the substrate by a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm by using a spin coater and then for 40-80 seconds at the rotating speed of 2000 rpm; placing the sample on a heating plate to be heated and annealed at 110 ℃ for 20 minutes in a pure argon environment, wherein the semiconductor layer is coated in a spinning mode in the step; the thickness range of the prepared semiconductor film is 35-45 nanometers, and the semiconductor film is an active layer;
b5: preparation of insulating layer film
Spreading the prepared insulating layer solution on the upper surface of the semiconductor film through a liquid transfer gun, and homogenizing for 5 seconds at the rotating speed of 500rpm and then 60 seconds at the rotating speed of 2000rpm by adopting a spin coater; placing the sample with the insulating layer coated in a spinning mode in the step on a heating plate in a pure argon environment, and heating and annealing the sample for 2 hours at the temperature of 80 ℃;
b6: preparation of grid electrode
Through the calibration of an optical microscope, enabling the opening position of the stainless steel mask plate to correspond to a channel between a source electrode and a drain electrode, and then preparing aluminum with the thickness of 60 nanometers on the upper surface of the insulating layer by using a vacuum thermal evaporation coating method to serve as a gate electrode to obtain the indium-doped N-type organic thin film transistor; wherein:
in the step A2, the high molecular polymer is polymethacrylate, polystyrene or perfluoro (1-butyl vinyl ether) polymer, and has a contact angle of at least 90 degrees with water;
in step B1, the insulating substrate is glass, silicon dioxide or poly-p-phthalic plastic.
2. An indium-doped N-type organic thin film transistor made by the method of claim 1.
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