CN105679699A - 层转移工艺 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 239000000463 material Substances 0.000 claims description 36
- 239000011521 glass Substances 0.000 claims description 19
- 239000000126 substance Substances 0.000 claims description 15
- 238000007669 thermal treatment Methods 0.000 claims description 13
- 230000003313 weakening effect Effects 0.000 claims description 12
- 238000013022 venting Methods 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- JOXCDOKKASTCHR-UHFFFAOYSA-N [Si](O)(O)(O)O.[P] Chemical compound [Si](O)(O)(O)O.[P] JOXCDOKKASTCHR-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229960001866 silicon dioxide Drugs 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 239000013626 chemical specie Substances 0.000 abstract 1
- 230000007704 transition Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 238000000280 densification Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000001272 nitrous oxide Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
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Abstract
本发明涉及一种层转移工艺。用于转移有用层(40)的工艺包括下列步骤：a)提供施主衬底(10)，所述施主衬底包括中间层(30)、承载衬底(20)和有用层(40)，中间层(30)适于变软；b)提供受主衬底(50)；c)组装受主衬底(50)和施主衬底(10)；以及d)对受主衬底(50)和施主衬底(10)进行热处理，该热处理在高于第一温度的第二温度下进行，所述工艺的特征在于，中间层(30)不含易于放气的物质，而且，形成了附加层(60)，所述附加层(60)包括适于在步骤d)中扩散到中间层(30)中并在中间层中形成弱化区(31)的化学物质。
Description
技术领域
本发明涉及一种用于将有用层转移至受主衬底的工艺。
背景技术
现有技术已知且在法国专利FR2860249中描述的一种用于将有用层转移至受主衬底的工艺包括下列步骤：
a)提供施主衬底1，该施主衬底包括位于承载衬底2与有用层4之间的中间层3，中间层3适于在第一温度下变软；
b)提供受主衬底5；
c)组装受主衬底5和施主衬底1；以及
d)在步骤c)后对受主衬底5和施主衬底1进行热处理，该热处理在高于第一温度的第二温度下进行。
中间层3可以是包括玻璃材料的层。
中间层3通常包括选自下述材料中的至少一种材料：硅酸磷玻璃(PSG)和硼磷硅玻璃(BPSG)。
中间层3以第一温度(一般被称为其玻璃化转变温度)为特征，中间层3在第一温度下变软并且能够弹性变形。
步骤d)在高于玻璃化转变温度的第二温度下进行，在步骤d)中，在中间层3中形成了微气泡或微腔。
在步骤d)中形成的微气泡和微腔源于中间层3中存在的化学物质。所述化学物质在步骤d)转变为气体。因为中间层3和有用层4被夹在承载衬底2与受主衬底5之间，所以转变为气体的化学物质被限制在中间层3中。
因此，转变为气体的化学物质通过奥斯瓦尔德熟化(Oswaldripening)机制而聚积，使得中间层3变成多孔的，从而形成弱化区。
于是在中间层3上施加力即足以将承载衬底2与在组装步骤c)中形成的结构分开，并从而将有用层4转移至受主衬底5。
但是，该工艺并不令人满意。
具体而言，在组装步骤c)之前，不能对施主衬底1进行包括(易于在中间层3中产生弱化区的)温度升高的加工步骤。这可能会产生有用层4在转移之前性能退化的后果。
进行这样的热退火步骤尤其是为了通过软化中间层3来使得在有用层4中预先存在的应力得到松弛。作为示例，有用层4可以是GaN层。
因此，本发明的一个目标是提供能够保留有用层4的完整性的工艺。
发明内容
本发明的目标在于解决上述问题，并且提供一种用于将有用层转移至受主衬底的工艺，该工艺包括下列步骤：
a)提供施主衬底，所述施主衬底包括位于承载衬底与有用层之间的中间层，中间层适于在第一温度下变软；
b)提供受主衬底；
c)组装受主衬底和施主衬底，使得有用层和中间层被夹在承载衬底与受主衬底之间；以及
d)在步骤c)之后对受主衬底和施主衬底进行热处理，该热处理在高于第一温度的第二温度下进行，
所述工艺的特征在于，中间层不含易于放气的物质，所述工艺的特征还在于，形成了附加层，所述附加层包括适于在步骤d)中扩散到中间层中并在中间层中形成弱化区的化学物质。
从而，中间层不含易于放气的物质，有用层不会在步骤a)中性能退化。
另外，通过形成附加层，仍然能够形成弱化区。
此外，本发明提供替换现有技术提出的方法的用于形成弱化层的方法。
根据一个实施方案，在步骤d)之后，沿弱化区进行分离步骤e)，从而将有用层转移至受主衬底。
根据一个实施方案，附加层被夹在中间层与承载衬底之间。
根据一个实施方案，在步骤a)中，将附加层置于有用层的自由表面上。
根据一个实施方案，附加层形成在受主衬底上。
根据一个实施方案，有用层包括由凹槽分开的多个区域，所述凹槽延伸贯穿有用层的厚度。
这使得在有用层被夹在中间层与附加层之间的情况下，包含在附加层中的化学物质能够更容易地向中间层扩散。
根据一个实施方案，中间层包括玻璃。
根据一个实施方案，所述玻璃包括选自下列材料中的至少一种材料：硅酸磷玻璃和硼磷硅玻璃。
根据一个实施方案，包含在附加层中的化学物质包括选自下列元素中的至少一种元素：氢、氮、氦和氩。
根据一个实施方案，附加层是含氢的二氧化硅。
根据一个实施方案，承载衬底包括选自下列材料中的至少一种材料：硅、锗、碳化硅和蓝宝石。
根据一个实施方案，有用层包括选自下列材料中的至少一种材料：GaN和InxGa1-xN。
根据一个实施方案，受主衬底包括下列材料中的至少一种材料：硅、锗、碳化硅和蓝宝石。
附图说明
通过下面的本发明的一个具体的且非限制性的实施方案的描述，本发明将得到更好的理解，该描述是参考所附附图给出的，在附图中：
-图1是根据本发明的一个实施方案的施主衬底的示意性截面图；
-图2a、图2b和图2c是根据本发明的一个实施方案的施主衬底的示意图；
-图3a、图3b、图3c和图3d是根据本发明的各个实施方案的示意性截面图；
-图4是根据本发明的一个实施方案的组装步骤的示意视图；以及
-图5是根据本发明的一个实施方案的热处理步骤d)的示意视图。
具体实施方式
对于各个实施的方法，出于简化描述的目的，对于相同的元素或提供相同功能的元素使用了相同的附图标记。
步骤a)包括提供施主衬底10。
如图1所示，施主衬底10从其背面到其正面可以包括承载衬底20、中间层30以及有用层40。
承载衬底20可以包括选自下列材料中的至少一种材料：硅、锗、碳化硅以及蓝宝石。
中间层30是适于在被加热至高于第一温度的温度时弹性变形的层。
表述“弹性变形”应当被理解为是指，使得中间层30软化并易于蠕变的变形。
于是中间层30可以是能够在第一温度(也称为其玻璃化转变温度)下进行玻璃化转变的玻璃。
术语“玻璃”应当被理解为是指，在低于玻璃化转变温度的任何温度下保持为固态、而在高于玻璃化转变温度的任何温度下粘性逐渐减小的材料。
中间层30可以包括选自下述材料中的至少一种材料：硅酸磷玻璃(PSG)和硼磷硅玻璃(BPSG)。
第一温度可以包括在300℃与1000℃之间，并且一般是600℃。
在施主衬底10的制造期间，中间层30可以通过等离子体增强化学气相沉积(PECVD)技术形成在承载衬底20上。
例如，中间层30可以包括通过涉及到例如前驱体正硅酸乙酯(TEOS)的PECVD方法形成的硼磷硅玻璃。沉积温度可以是400℃。
因此，中间层30的厚度可以包括在200nm与5μm之间，例如是1μm。
另外，第一温度可以包括在300℃与1000℃之间
优选地，中间层30不含在其形成后易于放气的物质。
然而，在其形成期间，中间层30可以包含易于放气的物质。
因此，在施主衬底10的制造期间，可以对中间层30进行包括温度上升的致密化热处理，以使得所述中间层30致密。
所述中间层30的热处理在中间层包含易于放气的物质时尤其有益。
对于硅酸磷玻璃或硼磷硅玻璃尤其如此。
所述易于放气的物质一般是中间层30的沉积反应所产生的副产物。
中间层30的沉积反应所产生的副产物可以包括烷基和水。
从而，在进行了所述致密化热处理之后，中间层30不含易于放气的物质。但是，中间层30保留了在被加热至高于第一温度的温度时弹性变形的能力。
致密化热处理可以在包括在600℃与900℃之间的温度下进行60min至300min。
对于包括硼磷硅玻璃的中间层30，致密化热处理可以在氧气和/或水汽气氛下在850℃的温度下进行60min。
有用层40可以通过转移工艺形成在中间层30上。
例如，有用层40可以通过SMARTCUTTM工艺形成。对此，本领域技术人员可以参考文献FR2681472。
在有用层40的转移工艺期间，经常要利用包括温度上升的处理，例如如同前述文献所提出的固化键合界面的步骤。
使得在这样的步骤期间中间层30中没有易于放气的物质，从而能够避免有用层40的性能退化和劣化。
有用层40可以是应变层，例如可以是拉伸应变层或压缩应变层。在有用层40包括InxGa1-xN时尤其如此。
特别地，合金InxGa1-xN一般是通过在GaN衬底上进行外延生长得到的，并因此具有应变。
从而，在将包括InxGa1-xN的层转移至中间层30以形成有用层40时，InxGa1-xN中的应变得以保留。
当有用层40具有应变时，所述应变可以通过在高于第一温度的温度下进行的热处理而得到松弛。所述热处理使得中间层30能够蠕变。
因为中间层30不含易于放气的物质，所以不会形成例如在法国专利FR2860249中观察到的微气泡或微腔。所以，不存在有用层40在高于第一温度的温度下的热处理期间性能退化或劣化的风险。
有用层40可以包括被凹槽42分开的多个区域41，凹槽42贯穿有用层40的厚度。
可以通过使用本领域技术人员所熟知的技术来刻蚀有用层40以产生凹槽42。
从而，图2a和图2b分别从截面和上方显示了有用层40的多个区域41。
区域41可以是任意形状的，例如可以是边长100μm至2000μm的正方形。
根据本发明的工艺的步骤b)包括提供受主衬底50。
受主衬底50可以包括选自下列材料中的至少一种材料：硅、锗、碳化硅以及蓝宝石。
转移工艺还包括形成附加层60。
附加层60包括适于在高于第一温度的第二温度下进行的热处理期间扩散到中间层30中的化学物质。
附加层60可以被置于承载衬底20与中间层30之间(图3a)，或者中间层30与有用层40之间(图3b)，或者在有用层40的自由表面上(图3c)，或者甚至受主衬底50上(图3d)。
附加层60中包含的化学物质可以包括选自下列元素中的至少一种元素：氢、氮、氦、氩和氧。
附加层60可以包括以OH或H离子或者水分子H2O的形式含有氢的二氧化硅(SiO2)，但还可以包括含碳副产物(例如CH3OH或CH3CH2OH)。
附加层60可以通过等离子体增强化学气相沉积(PECVD)技术形成。在形成附加层60时使用的前驱体可以包括稀释在一氧化二氮(N2O)流或氧气(O2)流中的硅烷(SiH4)。附加层60在包括于200℃与500℃之间的温度(例如，300℃)下进行沉积。
在附加层被夹在承载衬底20与中间层30之间或者中间层30与有用层40之间时，附加层60可以在施主衬底10的制造期间形成。
附加层60也可以形成在有用层40的自由表面上。
例如图2c所示，当凹槽42形成为穿过有用层40的厚度时，附加层60还填充所述凹槽。
例如图4所示，转移工艺的步骤c)包括将施主衬底10和受主衬底50组装。
进行组装使得有用层40、中间层30以及附加层60被夹在承载衬底20与受主衬底50之间。
步骤c)可以包括直接键合步骤。
步骤d)包括在高于第一温度(或玻璃化转变温度)的第二温度下进行的热处理。
在步骤d)中，中间层30软化。换言之，中间层30变软。此外，包含在附加层60中的化学物质通过菲克扩散从附加层60向中间层30扩散。因为中间层30是软的，所以在中间层30中可能会形成微气泡或微腔。从而，所述微气泡和/或微腔弱化中间层30，并因而在中间层30的整个范围形成弱化区31(图5)。
当附加层60形成在有用层40的自由表面上时，附加层60中包含的化学物质首先扩散穿过有用层40，然后进入中间层30。
在凹槽形成为穿过有用层40的厚度的情况下，包含在附加层60中的化学物质还穿过所述凹槽以到达中间层30。
可以在被包括在700℃与1100℃之间的温度(例如，800℃)下进行热处理。
受主衬底50的存在使得在形成弱化区31的步骤d)中结构得到固化。
还可以进行附加步骤e)，其包括使中间层30沿弱化区31断裂，从而将有用层40转移至受主衬底50。
断裂可以通过向组装体施加力来实现，例如通过在组装体界面插入刀刃。
因此，根据本发明，能够通过注入原本包含在附加层60中的化学物质来在中间层30中形成弱化区31。根据本发明的在中间层30中的弱化区31的形成防止了待转移至受主衬底50的有用层40性能退化。
对于在从第一衬底向第二衬底转移具有极性的有用层40的情况，本发明尤其有益。
Claims (13)
1.一种用于将有用层(40)转移至受主衬底(50)的工艺，所述工艺包括下列步骤：
a)提供施主衬底(10)，所述施主衬底包括位于承载衬底(20)与有用层(40)之间的中间层(30)，中间层(30)适于在第一温度下变软；
b)提供受主衬底(50)；
c)组装受主衬底(50)和施主衬底(10)，使得有用层(40)和中间层(30)被夹在承载衬底(20)与受主衬底(50)之间；以及
d)在步骤c)之后对受主衬底(50)和施主衬底(10)进行热处理，该热处理在高于第一温度的第二温度下进行，
所述工艺的特征在于，中间层(30)不含易于放气的物质，所述工艺的特征还在于，形成了附加层(60)，所述附加层(60)包括适于在步骤d)中扩散到中间层(30)中并在中间层中形成弱化区(31)的化学物质。
2.根据权利要求1所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，在步骤d)之后，沿弱化区(31)进行分离步骤e)，从而将有用层(40)转移至受主衬底(50)。
3.根据权利要求1或2所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，附加层(60)被夹在中间层(30)与承载衬底(20)之间。
4.根据权利要求1或2所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，在步骤a)中，将附加层(60)置于有用层(40)的自由表面上。
5.根据权利要求1或2所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，附加层(60)形成在受主衬底(50)上。
6.根据权利要求1至5中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，有用层(40)包括被凹槽(42)分开的多个区域(41)，所述凹槽延伸贯穿有用层(40)的厚度。
7.根据权利要求1至6中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，中间层(30)包括玻璃。
8.根据权利要求7所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，所述玻璃包括选自下列材料中的至少一种材料：硅酸磷玻璃和硼磷硅玻璃。
9.根据权利要求1至8中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，包含在附加层(60)中的化学物质包括选自下列元素中的至少一种元素：氢、氮、氦和氩。
10.根据权利要求1至9中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，附加层(60)是含氢的二氧化硅。
11.根据权利要求1至10中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，承载衬底(20)包括选自下列材料中的至少一种材料：硅、锗、碳化硅和蓝宝石。
12.根据权利要求1至11中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，有用层(40)包括选自下列材料中的至少一种材料：GaN和InxGa1-xN。
13.根据权利要求1至12中的任一项所述的用于将有用层(40)转移至受主衬底(50)的工艺，其中，受主衬底(50)包括下列材料中的至少一种材料：硅、锗、碳化硅和蓝宝石。
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