CN105634548B - A kind of method based on microprocessor control signals conditioning chip - Google Patents
A kind of method based on microprocessor control signals conditioning chip Download PDFInfo
- Publication number
- CN105634548B CN105634548B CN201510992574.6A CN201510992574A CN105634548B CN 105634548 B CN105634548 B CN 105634548B CN 201510992574 A CN201510992574 A CN 201510992574A CN 105634548 B CN105634548 B CN 105634548B
- Authority
- CN
- China
- Prior art keywords
- signal
- signal condition
- chip
- microprocessor
- condition chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/32—Reducing cross-talk, e.g. by compensating
Abstract
The invention discloses a kind of method based on microprocessor control signals conditioning chip, including：Microprocessor and signal condition chip after communication is connected, is associated setting to microprocessor and signal condition chip, the information of the source file with signal condition chip is imported into the project file of microprocessor；According to the transmission path situation of signal, microprocessor carries out parameter setting to signal condition chip, so as to call the source file of the signal condition chip imported in the project file of microprocessor, to establish the system of signal condition chip calling and program execution environments, and realize the signal condition function of signal condition chip；Complete the operation that the signal condition chip after parameter setting to the high speed signal of input eliminate distorted signals.The present invention solves the problems, such as to carry out signal condition to the high speed signal of such as OC192 speed, 10GE speed or higher rate to eliminate distorted signals.
Description
Technical field
The present invention relates to signal control technology field, more particularly to it is a kind of based on microprocessor control signals conditioning chip
Method.
Background technology
In backbone network access device, carrier wave optical signal slave device enters, and carrier wave electricity is converted to by the optical module in equipment
Signal, optical signal is converted electrical signals to send after the processing of equipment, then by optical module.Here high speed signal
Speed is including 1Gbps, 2.5Gbps, 9.95328Gbps and 10.3125Gbps etc..Wherein, the electric signal of 1Gbps speed, which corresponds to, carries
Ripple is the speed of gigabit Ethernet, and the electric signal of 2.5Gbps speed corresponds to the speed that carrier wave is 2.5Gbps, 9.95328Gbps speed
The electric signal of rate corresponds to the speed that carrier wave is OC192 (Optical Carrier 192), the electric signal of 10.3125Gbps speed
The speed that corresponding carrier wave is 10GE (ten thousand mbit ethernets).
High speed signal can produce signal reflex, crosstalk after connector due to impedance mismatch, cause distorted signals.
Crosstalk refers to the interaction between two different electrical properties, and crosstalk is the coupling between two signal lines, when signal exists
Transmission line uploads sowing time, and the mutual inductance and mutual tolerance between signal wire cause the undesirable noise on line.Excessive crosstalk may draw
The false triggering of circuit is played, causes system not work normally.Cause many because being known as of impedance mismatch, mainly walked including PCB
Line processing, backplane connector and welding procedure etc..
For distorted signals, at this time need to be adjusted high speed signal by signal condition mode, that is, pass through signal
Conditioning mode is amplified the high speed signal of input, filter and the operation such as clock and data recovery is converted into next stage signal processing
The signal of the convenient processing of unit.As shown in Figure 1, the schematic diagram of signal transmission path.
Currently letter can be carried out to the signal of 1Gbps and 2.5Gbps speed by FPGA (field programmable gate array) modes
Number conditioning can eliminate distorted signals, and FPGA is (for the progress of such as signal of OC192 speed, 10GE speed or higher rate etc.
Signal condition cannot then eliminate the distortion of signal, while FPGA prices are high, cause use cost larger.
Therefore, how a kind of technical solution of signal condition is provided, is solved to such as OC192 speed, 10GE speed or higher
The high speed signal of speed carries out signal condition to eliminate distorted signals, becomes and is currently needed for solving the problems, such as.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of side based on microprocessor control signals conditioning chip
Method, carries out signal condition to eliminate distorted signals with the high speed signal solved to such as OC192 speed, 10GE speed or higher rate
The problem of.
To solve the above-mentioned problems, the present invention provides a kind of method based on microprocessor control signals conditioning chip,
Including：
Microprocessor and signal condition chip after communication is connected, microprocessor and signal condition chip are associated
Set, the information of the source file with signal condition chip is imported into the project file of microprocessor, wherein source file bag
Include and called for the system of signal condition chip and with the relevant suffix of program execution environments for the file of c and for signal condition
The suffix of the signal condition function of chip is the file of c；
According to the transmission path situation of signal, microprocessor carries out parameter setting to signal condition chip, so as to call micro-
The source file of the signal condition chip imported in the project file of processor, to establish the system of signal condition chip calling and journey
Sort run environment, and realize the signal condition function of signal condition chip；
Complete the operation that the signal condition chip after parameter setting to the high speed signal of input eliminate distorted signals.
Further, the above method may also include：The microprocessor and signal condition chip are carried out after communication is connected, right
The step of microprocessor is associated setting with signal condition chip, further includes：
Header file corresponding with the source file of signal condition chip is imported into the project file of microprocessor, header file
The file for being h for suffix.
Further, the above method may also include：The microprocessor carries out signal condition chip the step of parameter setting
Suddenly, further include：
According to the transmission path situation of signal, microprocessor carries out parameter setting to signal condition chip, is by head text
Part loads the source file of corresponding signal condition chip, so that the signal condition core imported in calling the project file of microprocessor
The source file of piece.
Further, the above method may also include：The system for signal condition chip is called and run with program
The suffix of environmental correclation is that the function of the file of c further includes：The function of delay, printing and string processing；
The suffix of the signal condition function for signal condition chip is that the function of the file of c includes：Equipment restarts,
Rule setting, rule perform, adjacent arranged in a crossed manner, winding is set and/or ucode loading functions.
Further, the above method may also include：The height of signal condition chip after the completion parameter setting to input
In the step of fast signal carries out eliminating the operation of distorted signals, further include：
After signal condition chip input reference clock, signal condition chip is according to the rate calculations of the high speed signal of input
Go out frequency multiplication or Frequency Dividing Factor, complete the use of signal, wherein, the scope of reference clock is 100MHZ~200MHZ.
Further, the above method may also include：The signal condition chip includes the amplification control of sequentially connected front end
Unit, electronic dispersion compensation unit, clock data recovery unit and pre-emphasis unit, the signal condition chip pass through each unit
Processing realize the operation for the high speed signal of input eliminate distorted signals.
Further, the above method may also include：The microprocessor carries out communication with signal condition chip and is connected, and is
Refer to：Communicated between microprocessor and signal condition chip by I2C buses, wherein microprocessor and signal condition chip it
Between communication mechanism be I2C buses polling mechanism, by every restarting I2C buses for a period of time, after solving software restarting operation,
Bus is set to recover normal.
Further, the above method may also include：The transmission path situation according to signal, microprocessor is to signal tune
Manage in the step of chip carries out parameter setting, further comprise：
If after judging the transmission path situation of signal to be transmitted by coaxial cable, select EDC signal processing moulds
Formula is CS_HSIO_EDC_MODE_CX1 patterns；
If after judging the transmission path situation of signal as short-distance transmission, it is CS_ to select EDC signal processing models
HSIO_EDC_MODE_SR patterns；
If after judging the transmission path situation of signal as long distance transmission, it is CS_ to select EDC signal processing models
HSIO_EDC_MODE_ZR patterns；
If after judging the transmission path situation of signal to be transmitted by backboard, according to the difference of signal transmission rate, choosing
It is respectively CS_HSIO_EDC_MODE_10G_BP patterns, CS_HSIO_EDC_MODE_15G_BP moulds to select EDC signal processing models
Formula, CS_HSIO_EDC_MODE_5G_BP patterns, CS_HSIO_EDC_MODE_7p5G_BP patterns, CS_HSIO_EDC_MODE_
8p5G_BP patterns, CS_HSIO_EDC_MODE_FCAN patterns or CS_HSIO_EDC_MODE_15G_BP_27dB patterns.
Further, the above method may also include：Further comprise：It is right after the signal condition chip connection Error Detector
Signal link carries out sectionalization test, wherein setting function to test section communication path to be measured by the winding of signal condition chip
Loss of signal situation.
Further, the above method may also include：Further comprise：It is right after the signal condition chip connection Error Detector
Signal link carries out sectionalization test, wherein carrying out the communication path of adjacency channel by the interleaving function of signal condition chip
Contrast test.
Compared with prior art, with the application of the invention, signal for such as OC192 speed, 10GE speed or higher rate, disappears
Except distorted signals effect is good, and the operation complexity of operating personnel is reduced, bring good user experience, pass through at the same time
The mode of microprocessor control signals conditioning chip, reduces cost, facilitates business application.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the schematic diagram of signal transmission path；
Fig. 2 is the structure diagram of the signal condition chip of the present invention；
Fig. 3 is the flow chart of the method based on microprocessor control signals conditioning chip of the present invention；
Schematic diagrames of the Fig. 4 for Stm32 in the example of the present invention to 4343 chip controls.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment, belongs to the scope of protection of the invention.
The central scope of the present invention：Signal condition chip is controlled by microprocessor in the present invention, realization pair
The high speed signal (such as signal of OC192 speed, 10GE speed or higher rate) of input is amplified, filter and clock data is extensive
It is multiple to wait operation, to eliminate distorted signals.It eliminates signal and loses for the signal of such as OC192 speed, 10GE speed or higher rate
True effect is good, and reduces the operation complexity of operating personnel, brings good user experience, while pass through microprocessor
The mode of control signal conditioning chip, reduces cost, facilitates business application.
Fig. 2 is the structure diagram of signal condition chip, and signal condition chip includes the amplification control of sequentially connected front end
(AGC) unit, electronic dispersion compensation (EDC) unit, clock and data recovery (CDR) unit and preemphasis (Pre-emph) unit；
Signal condition chip internal needs to provide reference clock (i.e. to signal condition chip input reference clock), chip internal outside chip
Frequency multiplication or Frequency Dividing Factor can be calculated according to the speedometer of pending signal, complete the use of signal.Wherein, the scope of reference clock
For 100MHZ~200MHZ.
Microprocessor can using no operating system working method, microprocessor and signal condition chip by I2C buses into
Row communication.The communication mechanism of I2C buses includes：Interrupt mechanism, polling mechanism or direct memory access (DMA) mechanism.Wherein,
Under the interrupt mechanism of I2C buses, after implementing software restarting operation to I2C buses, I2C buses can not be made to recover normal；I2C buses
DMA mechanism be suitable for chunk data transmission, and due to the present invention application in need to read and write multiple and different registers, because
This DMA mechanism is not suitable for this application scenarios；The polling mechanism of I2C buses can solve the feelings of bus exception after software restarting
Condition, wherein by every restarting I2C buses for a period of time, therefore can solve software restarting by way of time-out judges and operate
Afterwards, bus is made to recover normal.The optional scope 100Kbps~1Mbps of I2C speed, wherein, due to being every time signal condition chip
EDC unit loading algorithms are required for the long period, in order to balance stability and efficiency, can select I2C speed as 400kbps.
SysTick Timer are provided by stm32.
In the present invention, microprocessor using no operating system working method, it is not necessary to operating system is understood, for letter
Single setting can directly carry out bottom setting, convenient for users closer to the realization of concrete function, while avoid
Complexity in the course of work due to operating system causes inoperable problem when there is the situation of system self problem.Certainly
Microprocessor can also use the working method for having operating system, but need to carry out more understanding to the content of operating system, together
When be not avoided that operating system self problem causes inoperable situation to occur.
Microprocessor can use Stm32 chips (i.e. the chip of ARM Cortex-M kernels), more than ARM9 kernels
Chip is all applied to the present invention.
Signal condition chip can use K2 family chips (i.e. 4343 chips), and 4343 chips can be that each passage is same
When provide a specific frequency synthesizer, and divide it is more accurate, chip reference clock alternative is much larger.Moreover, 4343
Chip also provides a specific signal condition unit for each passage.So each passage can transmit different-format
Signal, meets the requirement of equipment processing multiple format signal.
As shown in figure 3, the method based on microprocessor control signals conditioning chip of the present invention, comprises the following steps：
After step 310, microprocessor and signal condition chip carry out communication connection, to microprocessor and signal condition chip
Setting is associated, the information of the source file with signal condition chip is imported into the project file of microprocessor, wherein
Source file for the file of c and is used for including the system calling for signal condition chip and with the relevant suffix of program execution environments
The suffix of the signal condition function of signal condition chip is the file of c；
Wherein, the file for the system calling of signal condition chip and with the relevant suffix of program execution environments for c, such as
Cs_rtos.c files, contain all system call and with program execution environments are relevant grand and general utility functions (including：Prolong
When, the function such as printing and string processing).Partial function in this file is needed to be modified or realized to adapt to present procedure
Running environment.Such as delay function, because stm32 simulates 1 using the working method of no operating system by program execution time
Microsecond realizes CS_UDELAY functions (delay of 1 microsecond)；1 millisecond time-delay function CS_ is realized by SysTick Timer
MDELAY (1 millisecond time-delay).
The file that suffix for the signal condition function of signal condition chip is c, such as cs4224_api.c files, comprising
The built-in functions of 4343 chips.It realizes the various functions of chip, including equipment is restarted, rule setting, rule perform, are adjacent
Arranged in a crossed manner, winding is set and/or ucode loads function etc., and above-mentioned function is finally read and write by the register of the bottom to complete.
Read-write for register, built-in function are not provided with, merely provide interface, and removing selection SPI by user, (serial peripheral connects
Mouthful) or I2C complete concrete implementation.I2C communication modes are employed herein, with reference to the communication protocol provided in document, realize
Register read-write interface supplies library function call.
The microprocessor and signal condition chip after communication is connected, microprocessor and signal condition chip are carried out
The step of association is set, further includes：Header file corresponding with the source file of signal condition chip is imported into the work of microprocessor
In journey file, header file is the file that suffix is h.
In the present invention, it is necessary to by cs_rtos.c, cs_rtos.h, cs4224_api.c, the file of cs4224_api.h
It is added in stm32 project files.
Step 320, the transmission path situation according to signal, microprocessor carry out parameter setting to signal condition chip, from
And the source file of the signal condition chip imported in the project file of microprocessor is called, to establish the system of signal condition chip
Calling and program execution environments, and realize the signal condition function of signal condition chip；
The step of microprocessor carries out parameter setting to signal condition chip, further includes：According to the transmission road of signal
Footpath situation, microprocessor carry out parameter setting to signal condition chip, are to load corresponding signal condition chip by header file
Source file so that the source file of the signal condition chip imported in calling the project file of microprocessor.
The microprocessor carries out communication with signal condition chip and is connected, and refers to：Microprocessor and signal condition chip it
Between communicated by I2C buses, wherein communication mechanism uses the polling mechanism of I2C buses, by every restarting I2C for a period of time
Bus, after solving software restarting operation, makes bus recover normal.Software restarting is avoided by the polling mechanism of I2C buses to grasp
After work, I2C buses are occupied always, the problem of causing cisco unity malfunction.
The step of transmission path situation according to signal, microprocessor carries out parameter setting to signal condition chip
In, further comprise：
If after judging the transmission path situation of signal to be transmitted by coaxial cable, select EDC signal processing moulds
Formula is CS_HSIO_EDC_MODE_CX1 patterns；
If after judging the transmission path situation of signal as short-distance transmission, it is CS_ to select EDC signal processing models
HSIO_EDC_MODE_SR patterns；
If after judging the transmission path situation of signal as long distance transmission, it is CS_ to select EDC signal processing models
HSIO_EDC_MODE_ZR patterns；
If after judging the transmission path situation of signal to be transmitted by backboard, according to the difference of signal transmission rate, choosing
It is respectively CS_HSIO_EDC_MODE_10G_BP patterns, CS_HSIO_EDC_MODE_15G_BP moulds to select EDC signal processing models
Formula, CS_HSIO_EDC_MODE_5G_BP patterns, CS_HSIO_EDC_MODE_7p5G_BP patterns, CS_HSIO_EDC_MODE_
8p5G_BP patterns, CS_HSIO_EDC_MODE_FCAN patterns or CS_HSIO_EDC_MODE_15G_BP_27dB patterns.According to
The different transmission path situation of signal, sets corresponding EDC signal processing models, and the distortion for eliminating high speed signal has been brought
The effect of benefit.
Specifically, a basic application journey is generated according to the software public_cs_explorer_1_7_1 provided
Sequence.The rough flow of program be hardware restart->Establish a default rule->The ginseng included according to user demand alteration ruler
Number configuration (EDC mode, balanced preemphasis, clock division etc.)->Executing rule.
By taking OC192 signals as an example, Host sides and Line sides all EDC moulds in reference clock selection 156.25MHZ, EDC configuration
Formula have selected CS_HSIO_EDC_MODE_CX1 patterns, Driver Trace Loss selections CS_HSIO_TRACE_LOSS_2dB.
After being provided with, you can generation respective code.But these settings might not can solve the problems, such as distorted signals, it is still necessary to
Configured according to the concrete condition of PCB (printed wiring board).
According to different application scenarios, there is provided several EDC signal processing models:CS_HSIO_EDC_MODE_CX1,CS_
HSIO_EDC_MODE_SR,CS_HSIO_EDC_MODE_ZR,CS_HSIO_EDC_MODE_DWDM,CS_HSIO_EDC_MODE_
10G_BP,CS_HSIO_EDC_MODE_15G_BP,CS_HSIO_EDC_MODE_5G_BP,CS_HSIO_EDC_MODE_7p5G_
BP,CS_HSIO_EDC_MODE_8p5G_BP,CS_HSIO_EDC_MODE_FCAN,CS_HSIO_EDC_MODE_15G_BP_
27dB.Above-mentioned pattern is respectively suitable for solving what signal was introduced by the mode that coaxial cable, short distance, long range or backboard transmit
Distorted signals.In practice, it is necessary to choose suitable EDC mode and attenuation compensation according to application scenarios.Wherein, Equalizer
Trace Loss (balanced device tracking loss) front end isostatic compensation, the decay of signal, Driver Trace are received for compensating
Loss (driving tracking loss) rear end preemphasis compensation, signal is sent in case the loss of signal of delivery section for compensating.
Signal condition chip after step 330, completion parameter setting carries out elimination distorted signals to the high speed signal of input
Operation.
Further include：After signal condition chip input reference clock, signal condition chip is according to the high speed signal of input
Speedometer calculates frequency multiplication or Frequency Dividing Factor, completes the use of signal, wherein, the scope of reference clock is 100MHZ~200MHZ.
Further comprise：After the signal condition chip connection Error Detector, sectionalization test is carried out to signal link, wherein logical
The winding for crossing signal condition chip sets function to test the loss of signal situation in section communication path to be measured；Pass through signal condition
The interleaving function of chip carries out the contrast test of the communication path of adjacency channel.By microprocessor to signal condition chip
Control, since signal condition chip has the function of winding setting and interleaving function, conveniently determines the bit error rate of high speed signal, and
The concrete condition of the convenient link investigation distorted signals to high speed signal.
With reference to instantiation, the invention will be further described.
As shown in figure 4, control processes of the Stm32 to 4343 chips：Wherein reference clock selected as 156.25MHZ；4343
Chip provides many built-in functions, is contained in cs_rtos.c, cs_rtos.h, cs4224_api.c, cs4224_api.h files
In.Visual customized user demand can be realized by software.After the good parameters of user configuration, generation is clicked on, you can
Obtain a power function.Its required function is incorporated herein, its realization is all from numerous built-in functions.In this way, just make for user
Provided a great convenience with 4343 chips, user need not pay close attention to which the specific deposit for the practical operation mentioned in document
Device, it is only necessary to be concerned about the function of chip.The power function that this is generated is added to stm32 programs by user together with built-in function
In, call this function to can be operated chip and complete specific function.But for bottom operation (namely the register of each platform
Read-write operation), it is necessary to user's self-developing.Realized in the present invention by I2C buses according to the communication protocol that chip provides
Communication between stm32 and 4343 chips.
Quality of the optical signal after equipment is monitored to complete by Error Detector.Error Detector serve as a light source to
It is outer to shine, by will be received back the optical signal that comes and with transmission signal fusing, to determine the bit error rate.Because signal is by signal
All once signal lives again that (it is exactly to be organized into best waveform to send to live again, certainly at this time when processing unit
Waveform may distortion because having judged to have judged into 0) into 1 or 10, need paragraph by paragraph (at signal
Reason node is dealt into next signal processing node and receives) investigate distortion phenomenon.
4343 chips have the function of winding and adjacent intersection, this is just convenient to sectionalization test signal link.We can be with
By winding come the loss of signal situation of part of detecting communication path, the contrast of adjacency channel can be carried out by interleaving function
Test.The realization of this partial function, can by referring to datasheet, by calling corresponding function library to complete, finally by
Stm32 performs this section of program code.
Each embodiment in this specification is generally described by the way of progressive, and what each embodiment stressed is
With the difference of other embodiment, between each embodiment identical similar part mutually referring to.
The application can be described in the general context of computer executable instructions, such as program
Module or unit.Usually, program module or unit can include performing particular task or realize particular abstract data type
Routine, program, object, component, data structure etc..In general, program module or unit can be by softwares, hardware or both
Combination realize.The application can also be put into practice in a distributed computing environment, in these distributed computing environment, by passing through
Communication network and connected remote processing devices perform task.In a distributed computing environment, program module or unit can
With in the local and remote computer-readable storage medium including storage device.
In the specification that this place provides, numerous specific details are set forth.It is to be appreciated, however, that the implementation of the present invention
Example can be put into practice in the case of these no details.In some instances, known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this description.Provided herein algorithm and display not with any certain computer, virtual
System or miscellaneous equipment are inherently related.Various general-purpose systems can also be used together with teaching based on this.According to above
Description, the structure required by constructing this kind of system is obvious.In addition, the present invention is not also directed to any certain programmed language
Speech.It should be understood that the content of invention described herein can be realized using various programming languages, and above to language-specific
The description done is to disclose the preferred forms of the present invention.
Similarly, it will be appreciated that in order to simplify the disclosure and help to understand one or more of each inventive aspect,
Above in the description to the exemplary embodiment of the present invention, each feature of the invention is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：I.e. required guarantor
The application claims of shield features more more than the feature being expressly recited in each claim.It is more precisely, such as following
Claims reflect as, inventive aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following embodiment are expressly incorporated in the embodiment, wherein each claim is in itself
Separate embodiments all as the present invention.
Those skilled in the art, which are appreciated that, to carry out adaptively the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.Can be the module or list in embodiment
Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or
Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it can use any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, summary and attached drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification (including adjoint power
Profit requires, summary and attached drawing) disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation
Replace.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included some features rather than further feature, but the combination of the feature of different embodiments means in of the invention
Within the scope of and form different embodiments.For example, in the following claims, embodiment claimed is appointed
One of meaning mode can use in any combination.
The all parts embodiment of the present invention can be with hardware realization, or to be run on one or more processor
Software module realize, or realized with combinations thereof.It will be understood by those of skill in the art that it can use in practice
Microprocessor or digital signal processor (DSP) are realized in webpage according to embodiments of the present invention in the playing device of video
Some or all components some or all functions.The present invention is also implemented as being used to perform side as described herein
The some or all equipment or program of device (for example, computer program and computer program product) of method.It is such
Realizing the program of the present invention can store on a computer-readable medium, or can have the shape of one or more signal
Formula.Such signal can be downloaded from internet website and obtained, and either be provided or with any other shape on carrier signal
Formula provides.
It should be noted that the present invention will be described rather than limits the invention for above-described embodiment, and ability
Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims,
Any reference symbol between bracket should not be configured to limitations on claims.Word "comprising" does not exclude the presence of not
Element or step listed in the claims.Word "a" or "an" before element does not exclude the presence of multiple such
Element.The present invention can be by means of including the hardware of some different elements and being come by means of properly programmed computer real
It is existing.In if the unit claim of equipment for drying is listed, several in these devices can be by same hardware branch
To embody.The use of word first, second, and third does not indicate that any order.These words can be explained and run after fame
Claim.
Claims (9)
1. a kind of method based on microprocessor control signals conditioning chip, including：
Microprocessor and signal condition chip after communication is connected, microprocessor is associated with signal condition chip and is set
Put, the information of the source file with signal condition chip is imported into the project file of microprocessor, wherein source file includes
System for signal condition chip is called and with the relevant suffix of program execution environments for the file of c and for signal condition core
The suffix of the signal condition function of piece is the file of c；
According to the transmission path situation of signal, microprocessor carries out parameter setting to signal condition chip, so as to call microprocessor
The source file of the signal condition chip imported in the project file of device, to establish, the system of signal condition chip is called and program is transported
Row environment, and realize the signal condition function of signal condition chip；
Complete the operation that the signal condition chip after parameter setting to the high speed signal of input eliminate distorted signals；
In the step of transmission path situation according to signal, microprocessor carries out parameter setting to signal condition chip, into
One step includes：
If after judging the transmission path situation of signal to be transmitted by coaxial cable, select EDC signal processing models for
CS_HSIO_EDC_MODE_CX1 patterns；
If after judging the transmission path situation of signal as short-distance transmission, it is CS_HSIO_ to select EDC signal processing models
EDC_MODE_SR patterns；
If after judging the transmission path situation of signal as long distance transmission, it is CS_HSIO_ to select EDC signal processing models
EDC_MODE_ZR patterns；
If after judging the transmission path situation of signal to be transmitted by backboard, according to the difference of signal transmission rate, select EDC
Signal processing model is respectively CS_HSIO_EDC_MODE_10G_BP patterns, CS_HSIO_EDC_MODE_15G_BP patterns, CS_
HSIO_EDC_MODE_5G_BP patterns, CS_HSIO_EDC_MODE_7p5G_BP patterns, CS_HSIO_EDC_MODE_8p5G_BP
Pattern, CS_HSIO_EDC_MODE_FCAN patterns or CS_HSIO_EDC_MODE_15G_BP_27dB patterns.
2. the method as described in claim 1, it is characterised in that
The microprocessor and signal condition chip after communication is connected, microprocessor and signal condition chip are associated
The step of setting, further include：
Header file corresponding with the source file of signal condition chip is imported into the project file of microprocessor, after header file is
Sew the file for h.
3. method as claimed in claim 2, it is characterised in that
The step of microprocessor carries out parameter setting to signal condition chip, further includes：
According to the transmission path situation of signal, microprocessor carries out parameter setting to signal condition chip, is added by header file
The source file of corresponding signal condition chip is carried, so that the signal condition chip imported in calling the project file of microprocessor
Source file.
4. the method as described in claim 1, it is characterised in that
The system for signal condition chip call and with the function of file that the relevant suffix of program execution environments is c also
Including：The function of delay, printing and string processing；
The suffix of the signal condition function for signal condition chip is that the function of the file of c includes：Equipment is restarted, rule
Set, rule performs, adjacent arranged in a crossed manner, winding is set and/or ucode loading functions.
5. the method as described in claim 1, it is characterised in that
Signal condition chip after the completion parameter setting to the high speed signal of input eliminate the operation of distorted signals
In step, further include：
After signal condition chip input reference clock, signal condition chip calculates again according to the speedometer of the high speed signal of input
Frequency or Frequency Dividing Factor, complete the use of signal, wherein, the scope of reference clock is 100MHZ~200MHZ.
6. the method as described in claim 1, it is characterised in that
The signal condition chip includes sequentially connected front end amplification control unit, electronic dispersion compensation unit, clock data
Recovery unit and pre-emphasis unit, the signal condition chip are realized by the processing of each unit and the high speed signal of input are carried out
Eliminate the operation of distorted signals.
7. the method as described in claim 1, it is characterised in that
The microprocessor carries out communication with signal condition chip and is connected, and refers to：Lead between microprocessor and signal condition chip
Cross I2C buses to be communicated, wherein the communication mechanism between microprocessor and signal condition chip is the poll machine of I2C buses
System, by every restarting I2C buses for a period of time, after solving software restarting operation, making bus recover normal.
8. method as claimed in claim 4, it is characterised in that
Further comprise：After the signal condition chip connection Error Detector, sectionalization test is carried out to signal link, wherein passing through letter
The winding of number conditioning chip sets function to test the loss of signal situation in section communication path to be measured.
9. method as claimed in claim 4, it is characterised in that
Further comprise：After the signal condition chip connection Error Detector, sectionalization test is carried out to signal link, wherein passing through letter
The interleaving function of number conditioning chip carries out the contrast test of the communication path of adjacency channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510992574.6A CN105634548B (en) | 2015-12-23 | 2015-12-23 | A kind of method based on microprocessor control signals conditioning chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510992574.6A CN105634548B (en) | 2015-12-23 | 2015-12-23 | A kind of method based on microprocessor control signals conditioning chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105634548A CN105634548A (en) | 2016-06-01 |
| CN105634548B true CN105634548B (en) | 2018-05-08 |
Family
ID=56049150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510992574.6A Active CN105634548B (en) | 2015-12-23 | 2015-12-23 | A kind of method based on microprocessor control signals conditioning chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105634548B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1578183A (en) * | 2003-07-29 | 2005-02-09 | 鸿富锦精密工业（深圳）有限公司 | System and method for improving waveform distortion during signal transmission process |
| CN102799114A (en) * | 2012-08-23 | 2012-11-28 | 北京经纬恒润科技有限公司 | Signal conditioning equipment |
| CN104166639A (en) * | 2014-05-23 | 2014-11-26 | 中国人民解放军国防科学技术大学 | 10 GSps 8 bit high-speed signal real-time acquisition, transmission, storage and playback system |
| CN104281550A (en) * | 2013-07-11 | 2015-01-14 | 鸿富锦精密工业（深圳）有限公司 | Signal retransmission device and signal retransmission method |
| CN204145459U (en) * | 2014-09-22 | 2015-02-04 | 中国科学院国家授时中心 | A kind of Sampling for Wide-Band Signal and conversion equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101987284B1 (en) * | 2012-12-13 | 2019-06-10 | 삼성전자주식회사 | Apparatus and method for setting threshold for detecting received symbol adaptively in a ook receiver |
-
2015
- 2015-12-23 CN CN201510992574.6A patent/CN105634548B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1578183A (en) * | 2003-07-29 | 2005-02-09 | 鸿富锦精密工业（深圳）有限公司 | System and method for improving waveform distortion during signal transmission process |
| CN102799114A (en) * | 2012-08-23 | 2012-11-28 | 北京经纬恒润科技有限公司 | Signal conditioning equipment |
| CN104281550A (en) * | 2013-07-11 | 2015-01-14 | 鸿富锦精密工业（深圳）有限公司 | Signal retransmission device and signal retransmission method |
| CN104166639A (en) * | 2014-05-23 | 2014-11-26 | 中国人民解放军国防科学技术大学 | 10 GSps 8 bit high-speed signal real-time acquisition, transmission, storage and playback system |
| CN204145459U (en) * | 2014-09-22 | 2015-02-04 | 中国科学院国家授时中心 | A kind of Sampling for Wide-Band Signal and conversion equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105634548A (en) | 2016-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109388530B (en) | Blade server-oriented automatic test platform and test method | |
| US8898358B2 (en) | Multi-protocol communication on an I2C bus | |
| CN106598903B (en) | Method and device for adjusting parameters of driver chip | |
| US9146823B2 (en) | Techniques for testing enclosure management controller using backplane initiator | |
| CN103246588B (en) | Controller and implementation method for self-checking serial bus | |
| CN103631688A (en) | Method and system for testing interface signal | |
| CN104516838A (en) | Management path determining method and device | |
| CN103201990A (en) | Adjustable finite impulse response transmitter | |
| EP2991234A1 (en) | Method, apparatus, and system for configuring high-speed serial bus parameter | |
| CN103105895A (en) | Computer system and display cards thereof and method for processing graphs of computer system | |
| CN114611304A (en) | Excitation signal generation method and device for signal integrity simulation | |
| CN105634548B (en) | A kind of method based on microprocessor control signals conditioning chip | |
| CN218938947U (en) | JTAG interface adapting board and system based on hardware simulation accelerator | |
| CN104915496A (en) | Method for wiring differential signal wires and device | |
| CN105956230B (en) | A kind of electric parameter compensation method and device | |
| CN105916303A (en) | PCB and method for producing same | |
| CN116306474A (en) | Method, device, equipment and storage medium for verifying access of network on chip | |
| TWI459874B (en) | A method for circuit layout and a device using the same | |
| CN103716200A (en) | Cassette optical line terminal equipment multiple passive optical fiber network card chip number identification method | |
| CN209132718U (en) | A kind of power supply jig of standard PCIE subcard and OCP subcard | |
| CN114328045A (en) | I2C debugging method, system and device for BMC and computer readable storage medium | |
| CN103793574B (en) | Method and device for laying copper foils on single plate | |
| CN102446132B (en) | Method and device for performing board-level management by simulating local bus | |
| CN112000189A (en) | Server mainboard based on S2500 processor | |
| CN109542702A (en) | A kind of test equipment and test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |