CN105590867A - Manufacturing method of wafer-level chip scale packaging structure - Google Patents
Manufacturing method of wafer-level chip scale packaging structure Download PDFInfo
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- CN105590867A CN105590867A CN201410579555.6A CN201410579555A CN105590867A CN 105590867 A CN105590867 A CN 105590867A CN 201410579555 A CN201410579555 A CN 201410579555A CN 105590867 A CN105590867 A CN 105590867A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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Abstract
The invention relates to a manufacturing method of a wafer-level chip scale packaging structure. The manufacturing method comprises: a wafer including a plurality of semiconductor elements is provided, wherein the half of the semiconductor elements have active sides and back sides, active regions and external regions are defined on the active sides, first electrodes and second electrodes are arranged in the active regions, and the external regions are divided into cutting parts and channel parts; patterned protection layers are formed on the active sides, wherein the patterned protection layers are provided with a plurality of openings to expose the first electrodes, the second electrodes, and the channel parts; thinning manufacturing processing is carried out on the back sides; back electrodes are formed on the back sides; selective etching processing is carried out to form grooves in the channel parts, and the back electrode layers are exposed; a conductive structure connecting the back electrode layers is formed by the grooves; and cutting processing is carried out along the cutting parts.
Description
Technical field
The present invention relates to a kind of semiconductor packages manufacturing process, relate in particular to a kind of wafer stage chipThe manufacture method of size packaging structure.
Background technology
In many decades in the past, semiconductor fabrication process and encapsulation technology, have very significantProgressive. But for power component, major part is still used traditional encapsulation to makeJourney, for example, with TO, little outer transistor npn npn (SOT), small size paster encapsulation (SOP), fourSide's plane is without packaged types such as pin package (QFN). In these packaged types, also mostTo utilize metal wire, as aluminium, copper or gold, to be electrically connected other outer members, recycling ringEpoxy resins is wrapped in chip in plastic-sealed body.
For example, but conventional package technology is more derivative problems also, cause resistance, parasitic capacitanceIncrease with inductance, so that make chip produce larger heat energy in the time of running, and these heat energyAnd cannot be removed in real time, thereby affect the performance of chip. Secondly, plastic-sealed body itself also can increaseAdd component size, do not meet semiconductor element towards requirement light, thin, short, little future development.In addition, in above-mentioned mentioned multiple encapsulation manufacturing process, major part is all with single chipsEncapsulate, therefore production efficiency is lower and packaging cost is higher.
Crystal wafer chip dimension encapsulation (WaferLevelChipScalePackaging) is a kind ofNovel encapsulated technology. After encapsulation, the size of finished product is equal to or completely less times greater than chip size,And be to carry out batch encapsulation with whole wafer. Therefore, with crystal wafer chip dimension encapsulation skillArt encapsulates power component, is the technology of industry utmost point wish development now.
Summary of the invention
Technical problem to be solved by this invention is, provides for the deficiencies in the prior artA manufacture method for wafer level chip scale package structure, it is by means of the passage at cutting areaIn portion, configure conductive structure, connect the dorsum electrode layer of semiconductor element. In addition, cutting part alsoNot configuring conductive structure, in the time carrying out cutting step, is along cutting part cutting, many to separateIndividual encapsulating structure.
Technical problem to be solved by this invention is achieved by the following technical solution:
A kind of manufacture method of wafer level chip scale package structure comprises the following steps; First,One wafer is provided, and wafer comprises multiple semiconductor elements, wherein one in multiple semiconductor elementsThe first semiconductor element has an active surface and a back side, and active surface has an active region and oneOutside area, described active region is provided with the first electrode and the second electrode, and described outside area divides into oneCutting part and a channel part; Follow-up, form patterning protective layer on active surface, wherein patternChange the multiple openings of protective layer tool to expose the first electrode, the second electrode and channel part; Then,Thinning manufacturing process is carried out in the first semiconductor element back side, then dorsum electrode layer is formed to firstThe back side of semiconductor element; Carry out selective etch manufacturing process, to form a ditch at channel partGroove, to expose dorsum electrode layer; Then, form conductive structure to connect back of the body electricity by described grooveUtmost point layer; Carry out cutting step along described cutting part.
Beneficial effect of the present invention is, the crystal wafer chip dimension that the embodiment of the present invention providesThe manufacture method of encapsulating structure, it forms groove by means of the channel part at outside area, and formsConductive structure connects dorsum electrode layer. Dorsum electrode layer can be electrically connected at by means of conductive structureOther electronic components.
In addition, in the time carrying out cutting step, be to cut along cutting part. That is to say,In the time utilizing cutting machine to cut the outside portion of cutting area, the cutter of cutting machine is half-and-half to leadBody material cuts with thinner dorsum electrode layer, but not directly thick metal material is cutCut, can reduce the coefficient of losses of cutter.
In order further to understand feature of the present invention and technology contents, refer to following relevantDetailed description of the present invention and accompanying drawing, but accompanying drawing only provides reference and explanation use, is not used forThe claims in the present invention protection domain is limited.
Brief description of the drawings
Fig. 1 is the manufacture method of the wafer level chip scale package structure of the embodiment of the present invention oneFlow chart;
Fig. 2 A is the top view of wafer;
Fig. 2 B is the first semiconductor element in Fig. 2 A and the enlarged drawing of the second semiconductor element;
Fig. 2 C is the generalized section of Fig. 2 B along I-I hatching;
Fig. 3 is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1In partial cutaway schematic;
Fig. 4 is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1In partial cutaway schematic;
Fig. 5 is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1In partial cutaway schematic;
Fig. 6 is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1In partial cutaway schematic;
Fig. 7 A is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1Partial cutaway schematic in rapid;
Fig. 7 B is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1In local schematic top plan view;
Fig. 8 A is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1Partial cutaway schematic in rapid;
Fig. 8 B is that the wafer level chip scale package structure of the embodiment of the present invention one is in the step of Fig. 1In local schematic top plan view;
Fig. 9 is the manufacture method of the wafer level chip scale package structure of the embodiment of the present invention twoFlow chart;
Figure 10 A is the schematic top plan view of the first semiconductor element;
Figure 10 B is the generalized section of Figure 10 A along H-H hatching;
The wafer level chip scale package structure that Figure 10 C to Figure 10 J is the embodiment of the present invention is at figureGeneralized section in 9 step;
Figure 10 K is cuing open of wafer level chip scale package structure after the cutting of the embodiment of the present inventionFace schematic diagram;
Figure 10 L is after the wafer level chip scale package structure of one embodiment of the invention cutsSchematic top plan view;
Figure 11 is that the encapsulating structure of the embodiment of the present invention after cutting is positioned over overlooking of lead frameSchematic diagram.
[description of reference numerals]
Wafer 100
The first semiconductor element 1,1 '
The second semiconductor element 2,2 '
Active surface 10
The back side 11,11 '
The first electrode 103,203
The second electrode 104,204
Outside area 101,201
Groove 101h
Active region 102,202
Cutting part 101a
Channel part 101b
Patterning protective layer 12
Opening 12a～12e
Dorsum electrode layer 13
Conductive structure 20
The first weld pad 21,21 '
The second weld pad 22,22 '
Metal rib layer 14
Photoresist layer 15
The first patterns of openings 15a
The second patterns of openings 15b
The 3rd patterns of openings 15c
First metal structure 16a～16d
Second metal structure 17a～17c
Lead frame 3
Die pad 30
Process step S100～S106, S200～S209
Line of cut 4,4 ', 5
Encapsulating structure M1, M2
Groove width W
Detailed description of the invention
Below, by means of specific instantiation, " wafer stage chip that the present invention records is describedThe manufacture method of size packaging structure " embodiment, those of ordinary skill in the art can by thisThe content that description is recorded is understood advantage of the present invention and effect easily. The present invention also can be byImplemented or apply in other different specific embodiments, the every details in this description alsoCan, based on different viewpoints and application, under not departing from spirit of the present invention, carry out various modifications and changeMore. In addition, accompanying drawing of the present invention is only simple declaration, not describe according to actual size, that isUnreacted go out to be correlated with form actual size, hereby statement. Following embodiment will be furtherDescribe correlation technique content of the present invention in detail, but the content of recording is not in order to limit thisThe technology category of bright claim protection.
Embodiment mono-
Refer to Fig. 1, it is the wafer level chip scale package structure of the embodiment of the present invention oneThe flow chart of manufacture method.
In step S100, provide wafer 100. The material that forms wafer 100 is generally silicon,But can be also other semi-conducting materials, for example GaAs. In embodiments of the present invention, wafer100 thickness is approximately 350 to 680 μ m. Please coordinate the A with reference to Fig. 2, it shows bowing of waferView. In embodiments of the present invention, wafer 100 has completed the manufacturing process that element is made,And comprise multiple semiconductor elements.
In embodiments of the present invention, with wherein one first semiconductor element in multiple semiconductor elementsPart 1 and the second semiconductor element 2 are example, describe embodiment of the present invention wafer stage chip in detailThe manufacture method of size packaging structure. The first semiconductor element 1 and the second semiconductor element 2 examplesRectilinear metal-oxide half field effect transistor (MOSFET), or other power component in this way.In embodiments of the present invention, the first semiconductor element 1 and the second semiconductor element 2 are rectilinearMetal-oxide half field effect transistor.
In the manufacture method of the wafer level chip scale package structure of the present embodiment, be by firstSemiconductor element 1 and the second semiconductor element 2 are packaged into an encapsulating structure jointly. In other words,In same encapsulating structure, there are at least two semiconductor elements. But in other embodiments,The manufacture method of wafer level chip scale package structure of the present invention also can be only to a semiconductorElement, for example, only encapsulate the first semiconductor element 1 and form encapsulating structure.
Please refer to Fig. 2 B and Fig. 2 C. Fig. 2 B shows the first semiconductor element in Fig. 2 A and theThe enlarged drawing of two semiconductor elements. Fig. 2 C shows the generalized section of Fig. 2 B along I-I hatching.The first semiconductor element 1 has an active surface 10 and a back side 11 contrary with active surface 10,Wherein the back side 11 of the first semiconductor element 1 is the some at the back side of wafer 100.
The first semiconductor element 1 defines outside area 101 and active region 102 on active surface 10,Wherein outside area 101 is centered around active region 102 around, is namely positioned at the first semiconductor elementThe neighboring area of part 1. Active region 102 is positioned at the zone line of semiconductor element 1, and mainIn moving district 102, be equipped with one first electrode 103 and one second electrode 104.
The second semiconductor element 2 is adjacent with the first semiconductor element 1, and its structure and the first half is ledBody member 1 is similar. Specifically, the second semiconductor element 2 also defines on active surface 10Active region 202 and outside area 201, and the first electrode 203 and second be set active region 202 is interiorElectrode 204. In embodiments of the present invention, the first electrode 103,203 is gate electrode, and theTwo electrodes 104,204 are source electrode. In one embodiment, source electrode has a lamination knotStructure is for example the laminated construction of copper/silicon/aluminium.
In addition, the outside area 201 of the second semiconductor element 2 and the first semiconductor element 1Outside area 101 is connected, to surround the active region 102 and the second half of the first semiconductor element 1The active region 202 of conductor element 2.
Specify, the outside area 101 of the first semiconductor element 1 can be divided into be cutCut the 101a of portion and channel part 101b, wherein channel part 101b is positioned at the first semiconductor element 1Active region 102 and the active region 202 of the second semiconductor element 2 between.
It should be noted that the present embodiment be taking two semiconductor elements share channel part asExample explanation. In another embodiment of the present invention, can be that corresponding one an of semiconductor element leads toRoad portion, or have the corresponding same channel part of multiple semiconductor elements, do not limit in the present inventionConfiguration between semiconductor element and channel part and corresponding relation.
Referring again to Fig. 1 and Fig. 3, then carry out step S101, form patterning protective layer 12On active surface 10. Patterning protective layer 12 can be dielectric layer, can protect the first semiconductorThe active region 102 of element 1 and the active region 202 of the second semiconductor element 2, in order to avoid active region102,202 are polluted in follow-up manufacturing process, and affect element characteristic. In addition figure,Case protective layer 12 also can be used as the shielding of follow-up manufacturing process.
The material of patterning protective layer 12 can be phosphorosilicate glass (phosphosilicateglass),Polyimides (polyimide) or nitride (nitride). In the present embodiment, patternChange the thickness range of protective layer 12 approximately between 1 to 10 μ m.
Please coordinate with reference to Fig. 3, be the wafer level chip scale package structure of the embodiment of the present invention onePartial cutaway schematic in step S101. By finding out in Fig. 3, patterning protective layer12 have multiple opening 12a～12e. In the present embodiment, opening 12a～12c exposes respectively firstThe first electrode 103, the second electrode 104 and the channel part 101b of semiconductor element 1, and openMouth 12d～12e exposes respectively the first electrode 203 and second electrode of the second semiconductor element 2204。
Specifically, in embodiments of the present invention, the first electrode 103 of the first semiconductor element 1Can be patterned protective layer 12 with the part edge region of the second electrode 104 and cover, and the first electricityThe zone line of the utmost point 103 and the second electrode 104 can pass through respectively opening 12a and opening 12bAnd it is out exposed. Similarly, patterning protective layer 12 also partly covers the second semiconductor elementThe first electrode 203 of 2 and the part edge region of the second electrode 204, and expose the first electrode203 and the zone line of the second electrode 204.
In addition, in the present embodiment, the opening 12c of patterning protective layer 12 exposes the first halfThe channel part 101b of conductor element 1. Particularly, patterning protective layer 12 can cover completelyThe cutting part 101a of semiconductor element 1 and the outside area 201 of the second semiconductor element 2.
Referring again to Fig. 1, in step S102, led by the first semiconductor element 1 and the second halfThinning manufacturing process is carried out at the back side of body member 2. In the present embodiment, the first semiconductor element 1Be copline and be interconnected with the back side of the second semiconductor element 2. And, the first semiconductorThe back side of element 1 and the second semiconductor element 2 be in fact also wafer 100 the back side whereinSome, therefore the first semiconductor element 1 and the second semiconductor element in embodiments of the present invention2 the back side has same numeral. Please coordinate with reference to Fig. 4, it shows the crystalline substance of one embodiment of the inventionThe partial cutaway schematic of circle level chip scale package structure in step S102. In the reality of Fig. 4Executing in example, is to describe as an example of the first semiconductor element 1 and the second semiconductor element 2 example.
In one embodiment, thinning manufacturing process can be mechanical type grinding back surface manufacturing process,Namely utilize the back of the body of mechanical wear down machine by the first semiconductor element 1 and the second semiconductor element 2Face 11 carries out thinning manufacturing process. Namely carry out thinning manufacturing process by the back side of wafer 100,With by the reduced thickness of wafer 100. And, utilize mechanical wear down machine to carry out thinning manufacturing processBefore, can first utilize adhesive tape to protect the master of the first semiconductor element 1 and the second semiconductor element 2Moving face 10. In embodiments of the present invention, the thickness of wafer 100 can be thinned to 125 μ m to 180 μ m.
Please refer to Fig. 1, after thinning manufacturing process, carry out step S103, form back of the body electricityThe back side of utmost point layer 13 after being polished of the first semiconductor element 1 and the second semiconductor element 211 '. Please coordinate with reference to Fig. 5, it is the crystal wafer chip dimension encapsulation knot of the embodiment of the present invention oneThe partial cutaway schematic of structure in step S103. Be noted that in the embodiment of Fig. 5,Dorsum electrode layer 13 extends to the second semiconductor element 2 by first semiconductor element 1 back side 11 'The back side 11 '. Although show that dorsum electrode layer 13 is formed in the first semiconductor element 1 and the second halfThe back side 11 ' of conductor element 2, but in fact dorsum electrode layer 13 is to be formed at whole wafer 100The back side.
In addition, in the present embodiment, dorsum electrode layer 13 can be a conductive material layer, using asThe drain electrode of the first semiconductor element 1. In one embodiment, dorsum electrode layer 13 for metal foldedLayer, for example, be titanium/nickel/silver-colored lamination, and wherein the thickness of titanium layer is 200nm, and the thickness of nickel dam approximately300nm, and the thickness of silver layer is 2000nm. In another embodiment, dorsum electrode layer 13 alsoIt can be titanium/copper lamination. But the material of dorsum electrode layer 13 and structure are not limited to aforesaid materialMaterial, also can use other materials.
In addition, in step S103, can utilize physical vaporous deposition or chemical gaseous phase heavyAmass to form dorsum electrode layer 13, wherein physical vaporous deposition is for example evaporation or sputter, but alsoNon-being used for limits the scope of the invention.
Referring again to Fig. 1, in step S104, carry out selective etch manufacturing process, withChannel part 101b forms groove 101h, to expose dorsum electrode layer 13. Please coordinate with reference to Fig. 6, itsThe part of the wafer level chip scale package structure of demonstration one embodiment of the invention in step S104Generalized section. In one embodiment, in step S104, performed selective etch was madeJourney can be silicon etching manufacturing process.
Specify, the region that channel part 101b is exposed by opening 12c is not appointedWhat electrode layer covers, and therefore, in silicon etching manufacturing process, is exposed to leading in opening 12cThe wafer 100 of the 101b of road portion can be removed, and forms groove 101h.
In addition, in the selective etch manufacturing process of the present embodiment, dorsum electrode layer 13 can be used asEtching stopping layer. That is to say, in silicon etching manufacturing process, when channel part 101b is by downwardsWhile being etched to dorsum electrode layer 13, stop. Therefore, institute's shape after selective etch manufacturing processThe groove 101h becoming is extended to the upper surface of dorsum electrode layer 13 by active surface 10, and exposes portionDivide dorsum electrode layer 13. In embodiments of the present invention, the width W of groove 101h be between 3 to30μm。
But the above embodiments are not in order to limit the present invention, in other embodiments, alsoCan first utilize after cutter cuts wafer 100 by opening 12c, then with wet etchingManufacturing process forms groove 101h.
Referring again to Fig. 1, and please coordinate with reference to Fig. 7 A and Fig. 7 B. Fig. 7 A is the invention processThe partial cutaway schematic of the wafer level chip scale package structure of example one in step S105, figure7B is that the wafer level chip scale package structure of the embodiment of the present invention one is in step S105Local schematic top plan view.
Then,, in the step S105 of Fig. 1, form conductive structure by described groove 101h20 to connect dorsum electrode layer 13. As shown in Fig. 7 A and Fig. 7 B, conductive structure 20 is a body of wall,And the top of body of wall is the upper surface higher than patterning protective layer.
In addition, in the time forming the step of conductive structure 20, more comprise by multiple opening 12a～12bRespectively form be connected in the first semiconductor element 1 the first electrode 103 the first weld pad 21 andBe connected in the second weld pad 22 of the second electrode 104. Similarly, in the step that forms conductive structure 20When rapid, also can form respectively and be connected in the of the second semiconductor element 2 by opening 12d～12eThe first weld pad 21 ' of one electrode 203 and be connected in the second weld pad 22 ' of the second electrode 204.In embodiments of the present invention, conductive structure 20 is first weld pads that are positioned at the first semiconductor element 121 and the second weld pad 22 ' of the second semiconductor element 2 between.
The first weld pad 21, the second weld pad 22 that is noted that the first semiconductor element 1 withAnd the first weld pad 21 ', second weld pad 22 ' of the second semiconductor element 22 are formed at active surface 10Upper, when the first semiconductor element 1 and the second semiconductor element 2 after encapsulation will be assembled in circuitOn plate (not shown) time, the first electrode 103 of the first semiconductor element 1, the second electrode 104With dorsum electrode layer 13 can be respectively by means of the first weld pad 21, the second weld pad 22 and conductive structure 20Be electrically connected at the element on circuit board (not shown). Similarly, the second semiconductor element 2The first electrode 203 and the second electrode 204 can be respectively by means of the first weld pad 21 ' and the second welderingPad 22 ' the electronic component being electrically connected on circuit board.
Specify, in the present embodiment, because conductive structure 20 is formed at the first halfBetween the active region 101 of conductor element 1 and the active region 202 of the second semiconductor element 2, because ofThis first semiconductor element 1 and the second semiconductor element 2 are in fact by conductive structure 20 altogetherEnjoy identical dorsum electrode layer 13. That is to say the first semiconductor element 1 and the second semiconductor element2 drain electrode is electrically connected by dorsum electrode layer 13, and is extended and exposed by conductive structure 20In chip upper surface. In addition, conductive structure 20 can be as the electrode of test use, and the first halfConductor element 1 and the second semiconductor element 2 are electrically connected at circuit board by means of conductive structure 20After, can utilize circuit board to dispel the heat to the first semiconductor element 1 and the second semiconductor element 2.
In addition, by finding out in Fig. 7 B, in the present embodiment conductive structure 20 be formed at logicalThe regional area of the 101b of road portion. But in other embodiments, conductive structure 20 also can crossChannel part 101b between the first semiconductor element 1 and the second semiconductor element 2.
Referring again to Fig. 1, then in step S106, along the cutting part 101a of outside area 101Carry out a cutting step, form multiple encapsulating structure M1 that are separated from each other. In one embodiment,To carry out cutting step by means of crystal grain cutting machine. Please coordinate with reference to Fig. 7 A, Fig. 7 B, figure8A and Fig. 8 B, wherein Fig. 8 A is the wafer level chip scale package structure of the embodiment of the present invention oneGeneralized section after cutting, and Fig. 8 B is the crystal wafer chip dimension envelope of the embodiment of the present invention oneThe local schematic top plan view of assembling structure after cutting. In the step of Fig. 7 A to Fig. 8 A, can find out,In the time carrying out cutting step, be to carry out along the line of cut 4 of the cutting part 101a of outside area 101Cutting. Because the cutting part 101a of outside area 101 does not form conductive structure 20, therefore holdingWhen row cutting step, the cutter of crystal grain cutting machine does not more need metal material to cut, more noEasily loss.
Embodiment bis-
Please refer to Fig. 9, is the system of the wafer level chip scale package structure of the embodiment of the present invention twoThe flow chart of making method.
The present embodiment place different with last embodiment is, in the present embodiment, not by twoIndividual semiconductor element forms encapsulating structure, but only encapsulates for a semiconductor element.And in the present embodiment, each packed semiconductor element is corresponding to a channel part. WithUnder will be taking the first semiconductor element 1 as example, describe the crystal wafer chip dimension of the present embodiment in detailThe manufacture method of encapsulating structure. The element that the present embodiment is identical with last embodiment has identicalLabel.
Please refer to Fig. 9, Figure 10 A and Figure 10 B. Figure 10 A is bowing of the first semiconductor element 1Depending on schematic diagram, Figure 10 B shows the generalized section of Figure 10 A along H-H hatching.
In the present embodiment, the active surface 10 of the first semiconductor element 1 defines outside area equally101 with active region 102, and divide into cutting part 101a and channel part 101b at outside area 101.Be noted that in the present embodiment, at the other cutting part 101a of a wherein side of active region 102Away from the active region 102 of the first semiconductor element 1, and channel part 101b is near the first halfThe active region 102 of conductor element 1.
In addition, Figure 10 B to Figure 10 D is corresponding to the step S200 to S204 in Fig. 9. Due toThe step S200 of the present embodiment is to the step S100 of step S204 and last embodiment to stepS104 is identical, does not repeat them here. That is to say, as shown in Figure 10 D, at completing steps S204Afterwards, on the active surface of the first semiconductor element 1 and the back side, form respectively patterning protective layer12 with dorsum electrode layer 13, and formed groove 101h at channel part 101b.
The present embodiment place different with last embodiment is, forms conduction by groove 101hStructure is to connect the step of dorsum electrode layer 13 and to form the first weld pad 21 and the second weld pad 22Step. Specifically, the method for the present embodiment is after carrying out step S204, proceedsStep S205.
Please coordinate the E with reference to Figure 10, it shows the crystal wafer chip dimension encapsulation of the embodiment of the present inventionThe partial cutaway schematic of structure in step S205. In step S205, form at least oneMetal rib layer 14.
In Figure 10 E, show, metal rib layer 14 along the madial wall of shape ground covering groove 101h,Patterning protective layer 12, the first electrode 103 and the second electrode 104. In the present embodiment, canTo utilize the mode of evaporation or sputter to form metal rib layer 14, and form metal rib layer 14The group that forms of the optional free titanium of material, copper, tungsten and any combination thereof or one wherein.In addition, the thickness of metal rib layer 14 can be between 50nm to 300nm.
Referring again to Fig. 9 and Figure 10 F, in step S206, form photoresist layer 15 in metalOn barrier layer 14, wherein photoresist layer 15 has at least one the first patterns of openings 15a, one second and opensMouth pattern 15b and one the 3rd patterns of openings 15c.
Please coordinate the F with reference to Figure 10, it shows the crystal wafer chip dimension encapsulation of the embodiment of the present inventionThe partial cutaway schematic of structure in step S206. In Figure 10 F, show, photoresist layer 15The first patterns of openings 15a, the second patterns of openings 15b and the 3rd patterns of openings 15c are corresponding respectivelyDefine the position of the first electrode 103, the second electrode 104 and channel part 101b, to be used for respectivelyBe defined in position and the shape of multiple weld pads that will form in follow-up manufacturing process. In this enforcementIn example, aforesaid weld pad is for example the first weld pad 21, the second weld pad 22 in last embodiment.In addition, in the embodiment of the present invention, the thickness of photoresist layer 15 and the shape of wanting in follow-up manufacturing processThe height of the multiple weld pads that become equates.
In one embodiment, the cutting part 101a of outside area 101 can be completely by 15 of photoresist layersCover. And the aperture of the 3rd patterns of openings 15c is greater than the width of groove 101h, to exposeGroove 101h, be positioned at metal rib layer 14 and portion on the channel part 101b of outside area 101Divide the metal rib layer 14 being positioned on active region 102. Specify the 3rd opening figureCase 15c will define shape and the position of the contact pad being electrically connected with dorsum electrode layer 13, and connectsTouch pad will be used so that the electronic component electricity on dorsum electrode layer 13 and circuit board in follow-up manufacturing processProperty connects.
Referring again to Fig. 9, in step S207, form a metal conducting layer in the first opening figureIn case 15a, the second patterns of openings 15b and the 3rd patterns of openings 15c. In the present embodiment, goldBelong to conductive layer and there is laminated construction.
Please coordinate with reference to Figure 10 G and Figure 10 H, all show the wafer stage chip of the embodiment of the present inventionThe partial cutaway schematic of size packaging structure in step S207. In Figure 10 G, show, sameIn one manufacturing process, multiple first metal structure 16a～16d are inserted respectively to the first patterns of openingsIn 15a, the second patterns of openings 15b, the 3rd patterns of openings 15c and groove 101h. Specifically,First in groove 101h, insert the first metal structure 16d, then again respectively at the first patterns of openingsIn 15a, the second patterns of openings 15b and the 3rd patterns of openings 15c, form the first metal structure16a～16c。
That is to say, the first metal structure 16a contacts the first electrode 103, but the first metal structure16b contacts the second electrode 104. In addition, the first metal structure 16d is formed in groove 101hBe formed at the other active of groove 101h to connect dorsum electrode layer 13, the first metal structure 16cOn face 10, and extended towards active region 102 by the position of groove 101h.
The material of first metal structure 16a～16d can be selected copper, nickel or its alloy. At otherIn embodiment, the first metal structure also can be selected other conductive materials. In the present embodiment,The top of one metal structure 16a～16d is the top lower than photoresist layer 15.
Then,, in Figure 10 H, multiple second metal structure 17a～17c are inserted respectively to firstPatterns of openings 15a, the second patterns of openings 15b and the 3rd patterns of openings 15c. In the present embodiment,The end face of the top of second metal structure 17a～17c and photoresist layer 15 flushes. In addition, the second gold medalThe material that belongs to structure 17a～17c is for example tin, so that follow-up, the first semiconductor element 1 is assembled intoOn circuit board.
Referring again to Fig. 9, then carry out step S208, remove photoresist layer 15 and by photoresist layerThe 15 metal rib layers 14 that cover. Please coordinate the I with reference to Figure 10, its demonstration embodiment of the present inventionThe partial cutaway schematic of wafer level chip scale package structure in step S208. Removing lightAfter resistance layer 15 and the metal rib layer 14 that covered by photoresist layer 15, be formed at the first patterns of openingsMetal conducting layer in 15a, the second patterns of openings 15b and the 3rd patterns of openings 15c is electricity each otherSexual isolation.
Please refer to Figure 10 I, at the first metal structure 16a shown in Figure 10 I and the second metal knotStructure 17a coordinates and the function that produces, similar in appearance to the first weld pad 21 in Fig. 7 A. The first metal knotStructure 16b coordinates with the second metal structure 17b and the function that produces, similar in appearance to as in Fig. 7 ATwo weld pads 22. In addition, the first metal structure 16d inserts in groove 101h to connect dorsum electrode layer13, and the first metal structure 16c coordinates with the second metal structure 17c and as can electrically be linked inThe contact pad of circuit board. In other words, in the present embodiment, be used for connecting by groove 101hThe conductive structure of dorsum electrode layer 13 can have connecting portion (the first gold medal being formed in groove 101hBelong to structure 16d) and be formed at contact pad on active surface 10 (the first metal structure 16c withThe second metal structure 17c), wherein connecting portion is to be connected between dorsum electrode layer 13 and contact padOne body of wall.
In the present embodiment, be to plant ball (balldrop) to describe for example. But,In other embodiments, after carrying out step S104, also can change into and weld projection (solderOr the manufacturing process of copper post projection (CupillarBump) bumping).
Then, please refer to Fig. 9 and Figure 10 J. Figure 10 J shows the wafer scale core of the embodiment of the present inventionThe partial cutaway schematic of chip size encapsulating structure in step S209. As last embodiment,In step S209, carry out a cutting step along the cutting part 101a of outside area 101, formMultiple encapsulating structure M2 that are separated from each other. As shown in Figure 10 J, in the present embodiment, be alongBe positioned at the line of cut 4 ' of cutting part 101a, two adjacent encapsulating structure M2 are separated.
Please refer to Figure 10 K and Figure 10 L, the wafer after the cutting that Figure 10 K is the embodiment of the present inventionThe generalized section of level chip scale package structure. After Figure 10 L is the cutting of the embodiment of the present inventionThe schematic top plan view of wafer level chip scale package structure. Through the embodiment of the present invention of Fig. 9The encapsulating structure M2 of manufacture method on active surface 10, form patterning protective layer 12, and canWith second metal structure 17a～17c respectively with circuit board on electronic component be electrically connected.
Please coordinate with reference to Figure 11, it is that in the embodiment of the present invention, the encapsulating structure after cutting is putBe placed in the schematic top plan view of lead frame. Encapsulating structure is for example the encapsulation shown in Fig. 8 A and Fig. 8 BStructure M1, or encapsulating structure M2 as shown in Figure 10 K and Figure 10 L. In addition, thisThe manufacturing process method of the wafer level chip scale package structure of bright embodiment can more comprise followingStep:
First, provide a lead frame 3. Specifically, lead frame 3 comprises multiple die pad 30,And each die pad 30 has a surface, with contact packing structure M1 (or M2), as Figure 11Shown in.
Then, by each the encapsulating structure M1 (or M2) after cutting with a heat-conducting glue material respectivelyBe fixedly arranged in die pad 30. Specifically, encapsulating structure M1 (or M2) is being positioned over to crystalline substanceBefore grain seat 30, the first surface-coated heat-conducting glue material in die pad 30, and heat-conducting glue material is for exampleConducting resinl, thermal plastic insulation or tin cream. Then, can utilize die pick machine to cutEach the encapsulating structure M1 (or M2) cutting is placed on respectively in these die pad 30.
Subsequently, impose a heating manufacturing process, heat-conducting glue material is solidified, thereby make semiconductor elementPart 1 ' is fixed in die pad 30. In heating manufacturing process, whole lead frame 3 can be putEnter in baking box and heat. Finally, wire cutting frame 3, with by multiple die pad 30 by wireOn frame 3, separate.
In the present embodiment, as shown in figure 11, lead frame 3 have framework (not shown) andBe used for fixing multiple moulding (not shown) of each die pad 30. When will be by multiple die pad 30When separating on lead frame 3, can directly utilize cutter along the line of cut 5 shown in Figure 11,Moulding is cut off to moulding, can make die pad 30 by separating on lead frame 3, and obtain lastFinished product.
In sum, beneficial effect of the present invention can be, the embodiment of the present invention providesThe manufacture method of wafer level chip scale package structure, it is by means of form a groove at channel part,And form a conductive structure by groove, thereby make dorsum electrode layer can be by means of conductive structure electricityProperty is connected in other electronic components. In addition, in the time carrying out cutting step, be to enter along cutting partRow cutting.
Specify, in some crystal wafer chip dimension encapsulation manufacturing process, meeting existsWafer backside metal plate is as backside electrode, and this kind of plate thickness is conventionally thicker. And,In order to make the backside electrode of wafer extend to the weld pad of active surface as connecting circuit board, can cutIn cutting, slot, and fill metal material. Therefore, in follow-up cutting manufacturing process, cutterTool is that metal material is cut completely. But the cutter of crystal grain cutting machine has conventionally partiallyThe thin knife edge, in the time utilizing cutter to cut along Cutting Road, institute in metallic plate and Cutting RoadFilling metal material can cause the coefficient of losses of cutter to improve.
In comparison, in embodiments of the present invention, cutting part does not form or only has a small amount ofBe used for connecting the conductive structure of dorsum electrode layer. Accordingly, in the time carrying out cutting step, crystal grain cuttingThe cutter of machine need only cut for wafer itself and back of the body metal level. And, the invention processThe thinner thickness of back of the body metal level of example, therefore can reduce the proportion of goods damageds of cutter.
In addition, the encapsulating structure of the embodiment of the present invention can be fixed in die pad with heat-conducting glue material againOn. Accordingly, by means of heat-conducting glue material and die pad, can be by the semiconductor element in encapsulating structureThe heat producing in when running sheds, and can avoid the performance Yin Gaowen of semiconductor element as far as possible and is subject toTo impact.
The foregoing is only better possible embodiments of the present invention, non-ly therefore limit to power of the present inventionThe claimed scope of profit, therefore the equivalence techniques that all utilizations description of the present invention and accompanying drawing content are doneChange, be all contained in claim protection domain of the present invention.
Claims (12)
1. a manufacture method for wafer level chip scale package structure, is characterized in that, described inManufacture method comprises:
One wafer is provided, comprises multiple semiconductor elements, in wherein said multiple semiconductor elementsOne first semiconductor element there is an active surface and a back side, and described active surface has one mainMoving district and an outside area, described active region is provided with one first electrode and one second electrode, described outsideA trivial cutting part and the channel part of being divided into of portion;
Form a patterning protective layer on described active surface, described patterning protective layer has manyIndividual opening is to expose described the first electrode, described the second electrode and described channel part;
Carry out a thinning manufacturing process in the described back side;
Form a dorsum electrode layer in the described back side;
Carry out an etching manufacturing process, to form a groove at described channel part to expose the described back of the bodyElectrode layer;
Form a conductive structure to connect described dorsum electrode layer by described groove; And
Carry out a cutting step along described cutting part.
2. the manufacture method of wafer level chip scale package structure as claimed in claim 1, itsBe characterised in that, described patterning protective layer covers the portion of described the first electrode and described the second electrodeDivide fringe region.
3. the manufacture method of wafer level chip scale package structure as claimed in claim 1, itsBe characterised in that, described the first electrode for gate electrode, described the second electrode be source electrode and instituteStating dorsum electrode layer is drain electrode.
4. the manufacture method of wafer level chip scale package structure as claimed in claim 1, itsBe characterised in that, forming described conductive structure when connecting the step of described dorsum electrode layer, more bagDraw together and form respectively one first weld pad by multiple described openings and connect described the first electrode and oneTwo weld pads connect described the second electrode.
5. the manufacture method of wafer level chip scale package structure as claimed in claim 1, its spyLevy and be, form a groove to expose after described dorsum electrode layer step at described channel part, comprising:
Form at least one metal rib layer, cover the madial wall of described groove, described patterning guarantorSheath, described the first electrode and described the second electrode;
Form a photoresist layer on described metal rib layer, wherein said photoresist layer has at least oneThe first patterns of openings, one second patterns of openings and one the 3rd patterns of openings, the respectively corresponding institute that definesState the position of the first electrode, described the second electrode and described channel part;
Form a metal conducting layer in described the first patterns of openings, described the second patterns of openings and instituteState in the 3rd patterns of openings; And
Remove the described metal rib layer that described photoresist layer and described photoresist layer cover, to form oneThe first weld pad, one second weld pad and this conductive structure.
6. the manufacture method of wafer level chip scale package structure as claimed in claim 5, itsBe characterised in that, described conductive structure comprises the contact pad being positioned on described active surface and is positioned at instituteState a junction in groove.
7. the manufacture method of wafer level chip scale package structure as claimed in claim 6, itsBe characterised in that, described connecting portion is a body of wall, described in described wall connecting dorsum electrode layer with described inContact pad.
8. the manufacture method of wafer level chip scale package structure as claimed in claim 5, itsBe characterised in that, described metal conducting layer has laminated construction.
9. the manufacture method of wafer level chip scale package structure as claimed in claim 5, itsBe characterised in that, the material of described metal rib layer is free titanium, copper, tungsten and any combination institute thereofThe group of composition or one wherein.
10. the manufacture method of wafer level chip scale package structure as claimed in claim 1,It is characterized in that, after the described cutting step of execution, form multiple encapsulating structures that are separated from each other,And described manufacture method more comprises:
One lead frame is provided, and described lead frame comprises multiple die pad;
By described each encapsulating structure having cut with a heat-conducting glue material be fixedly arranged on respectively multiple described inIn die pad; And
Cut described lead frame, with by multiple described die pad by separating on described lead frame.
The manufacture method of 11. wafer level chip scale package structures as claimed in claim 1,It is characterized in that one second semiconductor element in described multiple described semiconductor elements and thisSemiconductor element is adjacent, and this access site is in the active region and this of this first semiconductor elementBetween the active region of the second semiconductor element.
The manufacture method of 12. wafer level chip scale package structures as claimed in claim 11,It is characterized in that, described dorsum electrode layer extends the back side of described the second semiconductor element.
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