CN103000537A - Wafer-level package structure and production method thereof - Google Patents

Wafer-level package structure and production method thereof Download PDF

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Publication number
CN103000537A
CN103000537A CN2011102904469A CN201110290446A CN103000537A CN 103000537 A CN103000537 A CN 103000537A CN 2011102904469 A CN2011102904469 A CN 2011102904469A CN 201110290446 A CN201110290446 A CN 201110290446A CN 103000537 A CN103000537 A CN 103000537A
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wafer
chip
layer
hole
plastic
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CN2011102904469A
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CN103000537B (en
Inventor
薛彦迅
黄平
何约瑟
哈姆扎·耶尔马兹
鲁军
鲁明联
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Priority to CN201110290446.9A priority Critical patent/CN103000537B/en
Publication of CN103000537A publication Critical patent/CN103000537A/en
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Publication of CN103000537B publication Critical patent/CN103000537B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a semiconductor device package member and a production method thereof, in particular to a package structure and a production method thereof. In the package structure, a chip is packaged integrally without any parts exposed out of package compound in the wafer-level package structure. By the redistribution technology, welding pads distributed on the top surface of the chip are redistributed as array welding points in a top insulating dielectric layer covering the chip, and by through holes formed on a silicon substrate and metal materials filled in the through holes, some electrodes or signal terminals on the top plane of the chip are connected to a bottom electrode metal layer on the bottom plane of the chip. Besides, the chip can be sealed without seams by the top package member and the bottom package member included in the wafer-level package structure, and accordingly good mechanical protection and electrical protection are formed.

Description

Encapsulating structure of a kind of wafer scale and preparation method thereof
Technical field
The present invention relates generally to packaging body of a kind of semiconductor device and preparation method thereof, more precisely, the present invention relates to a kind ofly in Wafer level packaging, chip is carried out overall package and it be there is no exposing encapsulating structure outside plastic packaging material and preparation method thereof.
Background technology
In advanced chip package mode, wafer-level packaging WLCSP (Wafer Level Chip Scale Packaging) is to carry out packaging and testing at the full wafer wafer in advance, and it is carried out plastic packaging, then just be cut to IC packaging body particle one by one, therefore the volume of the packaging body after the encapsulation namely almost is equal to the life size of bare chip, and this packaging body possesses good heat radiation and electric property.
Usually, in the complicated technology flow process of wafer-level packaging, no matter be based on the size that chip is still dwindled in the reduction of considering resistance substrate, finally need the attenuate chip to certain thickness.And that chip is healed is thin more cracked, this just requires to do one's utmost to be avoided chip is caused the damage of any form, but the actual process preparation flow is exactly unsatisfactory, for example the cutting of wafer causes the edge of chip or corner to burst apart to some extent easily, and the chip that one of its consequence obtains is frangible or unfilled corner.On the other hand; in the chip scale package body of current most of wafer scale; chip in the device partly exposes outside plastic packaging material; its harmful effect is to cause the poor and plastic-sealed body of chip humidity-proof ability that omnibearing mechanical protection can't be provided, and electric property also is suppressed to a certain extent.Publication number is the method that the United States Patent (USP) of US2009/0032871 has disclosed a kind of wafer-level packaging, its chips is finished plastic packaging and by after wafer minute cuts off, a part of electrode of chip front side is connected with the electrode of chip back by the conductive structure that is positioned at chip sides, yet the electrode of chip back remains and exposes outside plastic packaging material.The patent No. is the method that 6107164 United States Patent (USP) equally also discloses a kind of wafer-level packaging, by cutting in the front of wafer first and carrying out plastic packaging, again from the thinning back side wafer of wafer, afterwards chip is divided from wafer to cut off, the back side of the chip of finishing plastic packaging that obtains still still exposes outside plastic packaging material.Similarly, also have the patent No. to be respectively the United States Patent (USP) case of US6420244 and 6852607, these patent applications are all less than solving the problem that how chip can also be carried out complete seal protection in the attenuate wafer.
Summary of the invention
In view of the above problems, the present invention proposes a kind of method of wafer-level packaging, include on the wafer of a plurality of chips one, utilize weld pad that heavy distribution technique RDL will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the insulating medium layer that covers chip, arrange solder joint and comprise first kind arrangement solder joint, may further comprise the steps: on described arrangement solder joint, settle solder projection; The front of the described wafer of plastic packaging coats insulating medium layer and the solder projection that is positioned at wafer frontside with the first plastic packaging layer; Grind at the back side in wafer; Apply the back side of the wafer of one deck barrier layer to the attenuate, and form the opening that is arranged in the barrier layer; Carry out etching by the back side that is opened on the wafer behind the attenuate, in substrate that wafer comprises and insulating medium layer, form the contact first kind and arrange the through hole of solder joint, and remove the barrier layer; Fill metal material to described through hole; The back side of the wafer behind attenuate covers the layer of metal layer; Cut wafer at the back side that is coated with metal level of the wafer behind attenuate, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side that is coated with metal level of the wafer behind attenuate, forms the second plastic packaging layer of covered with metal layer, and plastic packaging material also is filled in the cutting groove simultaneously; Grind the first plastic packaging layer being exposed in the first plastic packaging layer of solder projection behind attenuate; In described cutting groove, cut, chip is separated.
Above-mentioned method, after forming described through hole, also the inwall at described through hole deposits the isolation liner bed course, and the metal material of filling by the isolation liner bed course be looped around around the through hole the substrate region insulation.Above-mentioned method, the mode that forms through hole is dry etching or wet etching or laser ablation.Above-mentioned method, the described first kind that contacts with through hole is arranged the position of solder joint, is arranged in the insulating medium layer on the non-active device of the substrate that the covers unit area.Above-mentioned method, described chip are rectilinear MOSFET.Above-mentioned method forms in the process of the through hole that contacts first kind arrangement solder joint, and the described first kind that contacts with through hole is arranged the drain electrode that solder joint consists of described MOSFET; And in the arrangement solder joint of all non-first kind arrangement solder joints, at least a portion does not consist of gate electrode and the source electrode that the arrangement solder joint that contacts with through hole consists of described MOSFET.
The method of another kind of wafer-level packaging provided by the invention, include on the wafer of a plurality of chips one, utilize weld pad that heavy distribution technique RDL will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the insulating medium layer that covers chip, arrange solder joint and comprise first kind arrangement solder joint, may further comprise the steps: apply one deck and cover the insulating medium layer that is positioned at wafer frontside and the barrier layer of arranging solder joint, and formation is arranged in the opening that the barrier layer contact first kind is arranged solder joint; By described opening the first kind is arranged the substrate that solder joint, insulating medium layer and wafer comprise and carry out etching, run through the through hole that the first kind is arranged solder joint until in insulating medium layer, substrate, form, remove afterwards the barrier layer; Settle solder projection on described arrangement solder joint, the part scolder is filled in the described through hole simultaneously; The front of the described wafer of plastic packaging coats insulating medium layer and the solder projection that is positioned at wafer frontside with the first plastic packaging layer; Grind until the back side of the wafer behind attenuate exposes outside the scolder that is filled in the described through hole in the back side of wafer; The back side of the wafer behind attenuate covers the layer of metal layer; Cut wafer at the back side that is coated with metal level of the wafer behind attenuate, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side that is coated with metal level of the wafer behind attenuate, forms the second plastic packaging layer of covered with metal layer, and plastic packaging material also is filled in the cutting groove simultaneously; Grind the first plastic packaging layer so that solder projection is exposed in the first plastic packaging layer behind attenuate; In described cutting groove, cut, chip is separated.
Above-mentioned method, after forming described through hole, also the inwall at described through hole deposits the isolation liner bed course, and the metal material of filling by the isolation liner bed course be looped around around the through hole the substrate region insulation.Above-mentioned method, the mode that forms through hole is dry etching or wet etching or laser ablation.Above-mentioned method, the planar cross-sectional size of formed through hole is less than the planar dimension of arranging solder joint.Above-mentioned method, the described first kind that contacts with through hole is arranged the position of solder joint, is arranged in the insulating medium layer on the non-active device of the substrate that the covers unit area.Above-mentioned method, described chip are rectilinear MOSFET.Above-mentioned method forms in the process of the through hole that contacts first kind arrangement solder joint, and the described first kind that contacts with through hole is arranged the drain electrode that solder joint consists of described MOSFET; And in the arrangement solder joint of all non-first kind arrangement solder joints, at least a portion does not consist of the arrangement solder joint that contacts with through hole and consists of the gate electrode of described MOSFET and the arrangement solder joint of source electrode.
The encapsulating structure of a kind of wafer scale provided by the invention, in this encapsulating structure, utilize weld pad that heavy distribution technique will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the top insulating medium layer that covers chip, arrange solder joint and comprise first kind arrangement solder joint, also comprise: the top plastic-sealed body that coats top insulating medium layer and solder projection, wherein said solder projection is placed in to be arranged on the solder joint, and solder projection is exposed in the plastic-sealed body of top; Cover one deck bottom electrode metal layer of chip back; Be formed on the contact first kind in substrate unit that chip comprises and the top insulating medium layer and arrange the through hole of solder joint, and the metal material of filling in the through hole first kind that will contact with through hole is arranged solder joint and is electrically connected on the described bottom electrode metal layer; Coat the bottom plastic-sealed body of described chip, the described bottom electrode metal layer of horizontal expansion partial coverage of bottom plastic-sealed body, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part is also covered the sidewall of chip, the sidewall of insulating medium layer, the sidewall of top plastic-sealed body simultaneously.
The encapsulating structure of above-mentioned wafer scale also is provided with the isolation liner bed course on the inwall of described through hole, and the metal material of filling is by isolation liner bed course and the substrate region insulation that is looped around around the through hole.The encapsulating structure of above-mentioned wafer scale in the insulating medium layer in covering the substrate unit that chip comprises on the non-active device unit area, is arranged solder joint by the described first kind that described heavy distribution technique setting contacts with through hole.The encapsulating structure of above-mentioned wafer scale, described through hole further run through this first kind that contacts with through hole arranges solder joint; And the planar cross-sectional size of through hole is less than the planar dimension of arranging solder joint, and the metal material of filling in the through hole is to be placed in the extension that the first kind is arranged the solder projection on the solder joint.The encapsulating structure of above-mentioned wafer scale, described chip are rectilinear MOSFET.The encapsulating structure of above-mentioned wafer scale, the described first kind that contacts with through hole is arranged the drain electrode that solder joint consists of described MOSFET; And in the arrangement solder joint of all non-first kind arrangement solder joints, at least a portion does not consist of gate electrode and the source electrode that the arrangement solder joint that contacts with through hole consists of described MOSFET.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of a plurality of chips one, be formed with in the front of wafer and protrude from solder projection wafer frontside and that be electrically connected to chip pad, may further comprise the steps: the front of the described wafer of plastic packaging, with front and the solder projection of the first plastic packaging layer coated silicon wafer; Grind at the back side in wafer; Cut wafer at the back side of the wafer behind attenuate, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side of the wafer behind attenuate, and formation coats the second plastic packaging layer at the back side of the wafer behind the attenuate, and plastic packaging material also is filled in the cutting groove simultaneously; Grind the first plastic packaging layer being exposed in the first plastic packaging layer of solder projection behind attenuate; In described cutting groove, cut, chip is separated.
Above-mentioned method is finished after the grinding back surface of wafer, and the back side that also is included in the wafer behind the attenuate covers the step of layer of metal layer; And in the process of the cutting groove that forms isolating chip, cut wafer at the back side that is coated with metal level of the wafer behind attenuate; And in the process of the second plastic packaging layer at the back side of the wafer after forming the coating attenuate, described the second plastic packaging layer is the while covered with metal layer also.Above-mentioned method, described chip are the IC of planar structure, and its all signal input output end all is arranged on a side of chip end face.Above-mentioned method, described chip are two MOSFET of rectilinear common drain; And the drain electrode of the drain electrode of a MOSFET and another MOSFET is electrically connected by described metal level among two MOSFET, and at least a portion is arranged source electrode and gate electrode that solder joint consists of respectively any one MOSFET among two MOSFET.Above-mentioned method comprises a plurality of diodes at least in the described chip, and an electrode terminal of described diode is electrically connected on the described metal level jointly; And at least a portion is arranged another electrode terminal that solder joint consists of described diode.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of a plurality of chips one, utilize weld pad that heavy distribution technique RDL will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the insulating medium layer that covers chip, may further comprise the steps: on described arrangement solder joint, settle solder projection; The front of the described wafer of plastic packaging coats insulating medium layer and the solder projection that is positioned at wafer frontside with the first plastic packaging layer; Grind at the back side in wafer; Cut wafer at the back side of the wafer behind attenuate, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer; Plastic packaging is carried out to wafer in the back side of the wafer behind attenuate, and formation coats the second plastic packaging layer at the back side of the wafer behind the attenuate, and plastic packaging material also is filled in the cutting groove simultaneously; Grind the first plastic packaging layer so that solder projection is exposed in the first plastic packaging layer; In described cutting groove, cut, chip is separated.
Above-mentioned method is finished after the grinding back surface of wafer, and the back side that also is included in the wafer behind the attenuate covers the step of layer of metal layer; And in the process of the cutting groove that forms isolating chip, cut wafer at the back side that is coated with metal level of the wafer behind attenuate; And in the process of the second plastic packaging layer at the back side of the wafer after forming the coating attenuate, described the second plastic packaging layer is the while covered with metal layer also.
The encapsulating structure of a kind of wafer scale provided by the invention, in this encapsulating structure, be formed with at the end face of chip and protrude from the solder projection chip end face and that be electrically connected to chip pad, also comprise: be coated on the top plastic-sealed body of chip end face, and solder projection is exposed in the plastic-sealed body of top; Coat the bottom plastic-sealed body of described chip, the bottom surface of the horizontal expansion partial coverage chip of bottom plastic-sealed body, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part is also covered the sidewall of chip, the sidewall of top plastic-sealed body simultaneously.
The encapsulating structure of above-mentioned wafer scale also comprises one deck bottom electrode metal layer that covers die bottom surface, also covers the bottom electrode metal layer in the time of the back side of the horizontal expansion partial coverage chip of described the second plastic packaging layer.The encapsulating structure of above-mentioned wafer scale, described chip are the IC of planar structure, and its all signal input output end all is arranged on a side of chip end face.The encapsulating structure of above-mentioned wafer scale, described chip are two MOSFET of rectilinear common drain; And the drain electrode of the drain electrode of a MOSFET and another MOSFET is electrically connected by described metal level among two MOSFET, and at least a portion is arranged source electrode and gate electrode that solder joint consists of respectively any one MOSFET among two MOSFET.The encapsulating structure of above-mentioned wafer scale comprises a plurality of diodes at least in the described chip, and an electrode terminal of described diode is electrically connected on the described metal level jointly; And at least a portion is arranged another electrode terminal that solder joint consists of described diode.
The encapsulating structure of a kind of wafer scale provided by the invention, in this encapsulating structure, utilize weld pad that heavy distribution technique will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the top insulating medium layer that covers chip, also comprise: the top plastic-sealed body that coats top insulating medium layer and solder projection, wherein said solder projection is placed in to be arranged on the solder joint, and solder projection is exposed in the plastic-sealed body of top; Coat the bottom plastic-sealed body of described chip, the bottom surface of the horizontal expansion partial coverage chip of bottom plastic-sealed body, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part is also covered the sidewall of chip, the sidewall of top insulating medium layer, the sidewall of top plastic-sealed body simultaneously.
The encapsulating structure of above-mentioned wafer scale also comprises one deck bottom electrode metal layer that covers die bottom surface, also covers the bottom electrode metal layer in the time of the bottom surface of the horizontal expansion partial coverage chip of described bottom plastic-sealed body.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of a plurality of chips one, be formed with in the front of wafer and protrude from solder projection wafer frontside and that be electrically connected to chip pad, may further comprise the steps: cut in the front in wafer, formation is positioned at the cutting groove that is used for isolating chip of wafer frontside one side, and this cutting groove stops in the substrate that wafer comprises; Plastic packaging is carried out in front in wafer, forms the first plastic packaging layer in the front of coated silicon wafer, and plastic packaging material also is filled in the cutting groove that is arranged in wafer frontside one side simultaneously; Grind at the back side in wafer; Cut wafer at the back side of the wafer behind attenuate, formation is positioned at the cutting groove that is used for isolating chip of the back side one side of the wafer behind the attenuate, and the cutting groove that is arranged in wafer rear one side behind the attenuate stops at substrate and further contacts with the plastic packaging material that is filled in the cutting groove that is arranged in wafer frontside one side; Plastic packaging is carried out to wafer in the back side of the wafer behind attenuate, form to coat the second plastic packaging layer at the back side of the wafer behind the attenuate, and plastic packaging material also is filled in the cutting groove that is arranged in wafer rear one side behind the attenuate simultaneously; Grind the first plastic packaging layer being exposed in the first plastic packaging layer of solder projection behind attenuate; Simultaneously the cutting groove of wafer rear one side in the cutting groove that is arranged in wafer frontside one side, after being arranged in attenuate cuts, and chip is separated.
Above-mentioned method is characterized in that, after grinding was finished at the back side of wafer, etching was carried out at the back side that also is included in the wafer behind the attenuate, and covers the step at the back side of the wafer of layer of metal layer to the attenuate; And the process that forms the cutting groove that is used for isolating chip be arranged in wafer rear one side behind the attenuate, cut wafer at the back side that is coated with metal level of the wafer behind attenuate; And in the process of the second plastic packaging layer at the back side of the wafer after forming the coating attenuate, described the second plastic packaging layer also coats described metal level simultaneously.
The method of a kind of wafer-level packaging provided by the invention, include on the wafer of a plurality of chips one, utilize weld pad that heavy distribution technique RDL will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the insulating medium layer that covers chip, arrange solder joint and comprise first kind arrangement solder joint, may further comprise the steps: on described arrangement solder joint, settle solder projection; Cut in front in wafer, forms the cutting groove that is used for isolating chip be positioned at wafer frontside one side, and this cutting groove stops in the substrate that wafer comprises; The front of the described wafer of plastic packaging coats insulating medium layer and the solder projection that is positioned at wafer frontside with the first plastic packaging layer, and plastic packaging material also is filled in and forms the cutting groove that is arranged in wafer frontside one side simultaneously; Grind at the back side in wafer; Cut wafer at the back side of the wafer behind attenuate, formation is positioned at the cutting groove that is used for isolating chip of wafer rear one side behind the attenuate, and the cutting groove that is arranged in wafer rear one side behind the attenuate stops at substrate and further contacts with the plastic packaging material that is filled in the cutting groove that is arranged in wafer frontside one side; Plastic packaging is carried out to wafer in the back side of the wafer behind attenuate, form to coat the second plastic packaging layer at the back side of the wafer behind the attenuate, and plastic packaging material also is filled in the cutting groove that is arranged in wafer rear one side behind the attenuate simultaneously; Grind the first plastic packaging layer being exposed in the first plastic packaging layer of solder projection behind attenuate; Simultaneously the cutting groove of wafer rear one side in the cutting groove that is arranged in wafer frontside one side, after being arranged in attenuate cuts, and chip is separated.
Above-mentioned method, after grinding was finished at the back side of wafer, etching was carried out at the back side that also is included in the wafer behind the attenuate, and covered the step at the back side of the wafer of layer of metal layer to the attenuate; And the process that forms the cutting groove that is used for isolating chip be arranged in wafer rear one side behind the attenuate, cut wafer at the back side that is coated with metal level of the wafer behind attenuate; And in the process of the second plastic packaging layer at the back side of the wafer after forming the coating attenuate, described the second plastic packaging layer also coats described metal level simultaneously.Above-mentioned method, before the back side that covers the wafer of layer of metal layer to the attenuate, further comprising the steps of:
Backside coating one deck barrier layer of the wafer behind attenuate, and form the opening that is arranged in the barrier layer; Carry out etching by the back side that is opened on the wafer behind the attenuate, in substrate that wafer comprises and insulating medium layer, form the contact first kind and arrange the through hole of solder joint, and remove the barrier layer; Fill metal material to described through hole, and the layer of metal layer that the back side of the wafer behind attenuate covers is electrically connected on the first kind arrangement solder joint that contacts with through hole by the metal material that is filled in the described through hole.Above-mentioned method, the described first kind that contacts with through hole is arranged the position of solder joint, is arranged in the insulating medium layer on the non-active device of the substrate that the covers unit area.
Said method, before settling solder projection on the arrangement solder joint, further comprising the steps of: as apply one deck and coat the insulating medium layer that is positioned at wafer frontside and the barrier layer of arranging solder joint, and formation to be arranged in the opening that the barrier layer contact first kind is arranged solder joint; By described opening to the described first kind arrange solder joint and insulating medium layer, substrate carries out etching, in substrate and insulating medium layer, form and run through the through hole that this first kind is arranged solder joint, and remove the barrier layer; When arranging solder joint arrangement solder projection, the part scolder also is filled in the described through hole in the lump afterwards.Said method, carry out in the process of lapping in the back side of wafer, the back side of the wafer behind attenuate exposes outside the scolder that is filled in the through hole, and the layer of metal layer of the afterwards back side covering of the wafer behind attenuate is electrically connected on the first kind arrangement solder joint that contacts with through hole by the scolder that is filled in the through hole.
The encapsulating structure of a kind of wafer scale provided by the invention, in this structure, be formed with at the end face of chip and protrude from the solder projection chip end face and that be electrically connected to chip pad, comprise: the top plastic-sealed body of coating chip, the horizontal expansion partial coverage of top plastic-sealed body is in the front of chip, the part that extends laterally of the top plastic-sealed body vertical with the horizontal expansion part of top plastic-sealed body is also covered the partial sidewall of chip simultaneously, and solder projection is exposed in the plastic-sealed body of top; The bottom plastic-sealed body of coating chip, the horizontal expansion partial coverage of bottom plastic-sealed body is in the bottom surface of chip, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part of bottom plastic-sealed body is also covered other a part of sidewall of chip simultaneously, and the part that extends laterally of top plastic-sealed body is in contact with one another with the sealing that chip is seamless with extending laterally partly of bottom plastic-sealed body.
The encapsulating structure of above-mentioned wafer scale also comprises one deck bottom electrode metal layer that covers die bottom surface, also covers the bottom electrode metal layer in the time of the bottom surface of the horizontal expansion partial coverage chip of described bottom plastic-sealed body.The encapsulating structure of above-mentioned wafer scale, described chip are the IC of planar structure, and its all signal input output end all is arranged on a side of chip end face.The encapsulating structure of above-mentioned wafer scale, described chip are two MOSFET of rectilinear common drain; And the drain electrode of the drain electrode of a MOSFET and another MOSFET is electrically connected by described bottom electrode metal layer among two MOSFET, and at least a portion is arranged source electrode and gate electrode that solder joint consists of respectively any one MOSFET among two MOSFET.The encapsulating structure of above-mentioned wafer scale comprises a plurality of diodes at least in the described chip, and an electrode terminal of described diode is electrically connected on the described bottom electrode metal layer jointly; And at least a portion is arranged another electrode terminal that solder joint consists of described diode.
The invention provides a kind of encapsulating structure of wafer scale, in this encapsulating structure, utilize weld pad that heavy distribution technique will be distributed in the chip end face again layout designs become to be arranged in the arrangement solder joint of the top insulating medium layer that covers chip, arrange solder joint and comprise first kind arrangement solder joint, it is characterized in that, comprise: the top plastic-sealed body of coating chip, the horizontal expansion partial coverage of top plastic-sealed body is on the insulating medium layer of top, the top plastic-sealed body vertical with the horizontal expansion part of top plastic-sealed body extend laterally part simultaneously also with the sidewall of top insulating medium layer, the partial sidewall of chip is covered, and solder projection is exposed in the plastic-sealed body of top; The bottom plastic-sealed body of coating chip, the horizontal expansion partial coverage of bottom plastic-sealed body is in the bottom surface of chip, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part of bottom plastic-sealed body is also covered other a part of sidewall of chip simultaneously, and the part that extends laterally of top plastic-sealed body is in contact with one another with the sealing that chip is seamless with extending laterally partly of bottom plastic-sealed body.
The encapsulating structure of above-mentioned wafer scale also is included in one deck bottom electrode metal layer that die bottom surface covers, and also covers the bottom electrode metal layer in the time of the bottom surface of the horizontal expansion partial coverage chip of described bottom plastic-sealed body.The encapsulating structure of above-mentioned wafer scale, also comprise: be formed on the through hole that the contact first kind in substrate unit that chip comprises and the top insulating medium layer is arranged solder joint, and the metal material of filling in the through hole first kind that will contact with through hole is arranged solder joint and is electrically connected on the described bottom electrode metal layer.The encapsulating structure of above-mentioned wafer scale, described through hole further run through this first kind that contacts with through hole arranges solder joint; And the planar cross-sectional size of through hole is less than the planar dimension of arranging solder joint, and the metal material of filling in the through hole is to be placed in the extension that the first kind is arranged the solder projection on the solder joint.The encapsulating structure of above-mentioned wafer scale, wherein, described chip is rectilinear MOSFET.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after the accompanying drawing, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
Description of drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only is used for explanation and sets forth, and does not consist of limitation of the scope of the invention.
Figure 1A-1B is original design diagram of the weld pad of chip end face.
Fig. 1 C-1D is the schematic diagram that the original weld pad of chip end face is carried out becoming from new layout designs the arrangement solder joint.
Fig. 1 E, 1F are respectively at original weld pad with at the schematic diagram of planting ball from the arrangement solder joint of new layout.
Fig. 2 A-2M is in a kind of execution mode, and the part of chip is arranged solder joint is connected to the electrode of chip back by the filling metal material in the through hole preparation flow.
Fig. 3 A-3J is in the another kind of execution mode, and the part of chip is arranged solder joint is connected to the electrode of chip back by the filling metal material in the through hole preparation flow.
Fig. 4 A-4E is in a kind of execution mode, forms electrode at the back side of chip and with the preparation flow of chip package after the RDL technical finesse.
Fig. 5 A-5F is in a kind of execution mode, forms electrode at the back side without the chip of RDL technical finesse and with the preparation flow of chip package.
Fig. 6 A-6E is in a kind of execution mode, does not form electrode at the back side of chip and with the preparation flow of chip package after the RDL technical finesse.
Fig. 7 A-7E is in a kind of execution mode, does not form electrode at the back side without the chip of RDL technical finesse and with the preparation flow of chip package.
Fig. 8 A-8I is in a kind of execution mode, is cutting and plastic packaging without the front of the wafer of RDL technical finesse, and plastic packaging and cutting are carried out in the back side of the wafer behind attenuate again, the preparation flow that chip is separated from wafer.
Fig. 9 A-9E is in a kind of execution mode, cutting and plastic packaging without the front of the wafer of RDL technical finesse, and the plastic packaging material of attenuate wafer frontside, the back side plastic packaging of the wafer behind attenuate and cutting are with the preparation flow of chip from separating.
Figure 10 A-10I is in a kind of execution mode, cuts and plastic packaging carries out plastic packaging and cutting in the back side of the wafer behind attenuate again the preparation flow that chip is separated from wafer after the RDL technical finesse in the front of wafer.
Embodiment
Shown in Figure 1A, in the schematic top plan view of chip 100 end faces, originally along chip 100 end faces edge designs all around a plurality of weld pads (Bond Pad) 101 that connect chip 100 internal circuits are arranged, weld pad 101 is generally aluminium pad (Peripheral pads) and is used for forming electrical contact with the external world, such as directly carrying out Bonding or the bottom metal layers UBM of first depositing Ti/Cu/Ni etc. thereon thereon, plant again ball, it can be the signal I/O contact terminal (I/O Pad) of chip 100 internal circuits, or the interface of Power or Ground etc.Figure 1B has described the schematic cross-section of weld pad 101 set on the end face of the chip 100 of segment thickness.
Shown in Fig. 1 C, utilize heavy distribution technique RDL (Redistribution Layer), the existing weld pad 101 around being arranged in of chip 100 end faces is redesigned into the arrangement solder joint 104 of any rational position, arrange solder joint 104 and can be redistributed into periphery, both sides or any side of chip 100 end faces, or even consist of the matrix form arrangement.For the ease of understanding, Fig. 1 C has showed that weld pad 101 is finished and has heavily distributed and form the schematic top plan view of arranging behind the solder joint 104, Fig. 1 D then is that weld pad 101 is processed the schematic cross-section that is arranged in insulating medium layer 102 after new layout through RDL, insulating medium layer 102 covers on the end face of chip 100, insulating medium layer 102 is generally polyimide material (Polyimide), arranging solder joint 104 can corresponding being electrically connected with weld pad 101 by being created on simultaneously interconnection line (Trace) 103 in the insulating medium layer 102, arrange simultaneously solder joint 104 also can be chosen in be not connected with any weld pad 101 after the RDL and individualism for future use.Interconnection line 103 common paths with bending, so Fig. 1 D does not depict interconnection line 103 and the concrete annexation of arrangement solder joint 104, weld pad 101, but carrying out the signal transmission with the external world, the weld pad 101 that this moment, a part was connected with arrangement solder joint 104 then depends on the arrangement solder joint 104 that is attached thereto.
Shown in Figure 1B and 1E, solder projection (Solder bump) 105 directly is welded on the original weld pad 101 of chip 100 end faces; And among Fig. 1 D and the 1F, solder projection 105 but is to be welded on to arrange on the solder joint 104.
Method referring to a kind of wafer-level packaging of Fig. 2 A-2M, shown in Fig. 2 A include a plurality of chips 200 ' wafer 200 on, multiple chips 200 ' mutually each other casting links together and jointly is formed among silicon substrate (or silicon substrate) 200A that wafer 200 comprises, adjacent chip is by scribe line (the Scribe Line of wafer frontside, not shown) mutually define border to each other, chip 200 ' weld pad 201 be positioned at the side in wafer 200 fronts.Utilize weld pad 201 that heavy distribution technique will be distributed in chip 200 ' end face again layout designs become to be arranged in to cover the arrangement solder joint 204 of the insulating medium layer 202 of wafer 200 (cover simultaneously chip 200 '), shown in Fig. 2 B.And plant ball at arrangement solder joint 204 and settle solder projection 205, shown in Fig. 2 C.Carry out plastic package process in the front of wafer 200 afterwards, with the insulating medium layer 202 in the first plastic packaging layer 206 coated solder projection 205 and covering wafer 200 fronts, shown in Fig. 2 D.Grind afterwards the thickness with attenuate wafer 200 at the back side of wafer 200, for example carry out cmp CMP, shown in Fig. 2 E, the segment thickness (such as D1) at wafer 200 back sides is polished, and namely the thickness of substrate 200A obtains attenuate.Apply again the back side of the wafer 200 of one deck barrier layer 207 to the attenuate, shown in Fig. 2 F, and form the opening 207 be arranged in barrier layer 207 patternings ', there are multiple choices on barrier layer 207, such as photoresistance or SiN or SiO2, mainly be in barrier layer 207, form the opening 207 aiming in vertical direction a part and arrange solder joint 204 (arranging solder joint 204a such as the first kind among Fig. 2 G) ', in order to utilize silicon through hole technology (TSV, Through Silicon Via), as the back side of hard mask and the wafer 200 by opening 207 ' behind attenuate substrate 200A and insulating medium layer 202 are carried out etching with barrier layer 207, so that be etched away in the silicon substrate 200A zone of opening 207 ' middle exposure, and etching lasts till that the insulating medium layer 202 in opening 207 ' middle exposure also is etched away, until etching stopping is arranged on the solder joint 204a the final through hole 208 that forms contact first kind arrangement solder joint 204a in substrate 200A and insulating medium layer 202 in the first kind.It is that all arrange the part in the solder joint 204 in fact that the first kind is arranged solder joint 204a, just the first kind arrange solder joint 204a initial not with chip 200 ' any weld pad 201 be connected and individualism, the first kind is arranged solder joint 204a and is used for being connected with some electrodes or the signal terminal that are formed on chip 200 ' bottom surface at subsequent step, thereby these electrodes is guided to a side in chip 200 ' front.Remove barrier layer 207 after finishing the etching of through hole 208, wherein, through hole 208 be formed with various ways, for example dry etching or wet etching or laser ablation; Usually after forming through hole 208, also need to deposit at the inwall of through hole 208 the isolation liner bed course of layer oxide film, so that the follow-up metal material that is filled in the through hole 208 can be by the isolation liner bed course be looped around around the through hole 208 silicon substrate area, insulate in the substrate 200A zone that namely surrounds through hole 208.Oversize to cause the first kind to arrange solder joint 204a unsettled and can't obtain the physical support of insulating medium layer 202 in through hole 208 in order to prevent through hole 208, can control opening 207 ' opening size size, and planar cross-sectional (cross section) size of further controlling through hole 208 makes it less than planar dimension size of arranging solder joint 204, thereby avoids the first kind to arrange coming off of solder joint 204a.
Shown in Fig. 2 H-2I, fill metal material 208 ' to through hole 208, and the back side of the wafer behind attenuate 200 covers layer of metal layer 209, the metal material 208 in this moment metal level 209 contact through holes 208 '.The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, form isolation adjacent chips 200 ' cutting groove 210, this moment, cutter touched certain thickness the first plastic packaging layer 206, cause cutting groove 210 to stop in the first plastic packaging layer 206, also be to rely on the first plastic packaging layer 206 multiple chips 200 ' this moment and interconnect, simultaneously metal level 209 be cut into the bottom electrode metal layer 209 that is positioned at every chips 200 ' bottom surface ', insulating medium layer 202 also be cut into the top insulating medium layer 202 that is positioned at every chips 200 ' end face ', shown in Fig. 2 J.The back side of the wafer 200 after being coated with metal level 209 and being attenuate again, wafer 200 is carried out plastic packaging, although this moment metal level 209 be cut into a plurality of bottom electrode metal layers 209 that are positioned at every chips 200 ' bottom surface ', but all bottom electrode metal layers 209 ' still jointly consist of metal level 209 of an integral body, thereby finish the second plastic packaging layer 211 that forms covered with metal layer 209 behind the plastic packaging, particularly, the second plastic packaging layer 211 coat the bottom electrode metal layer 209 that is positioned at every chips 200 ' bottom surface ', meanwhile, the part plastic packaging material that the second plastic packaging layer 211 comprises also is filled in the cutting groove 210, shown in Fig. 2 K.
Shown in Fig. 2 L-2M, the first plastic packaging layer 206 is ground the first plastic packaging layer 206 with attenuate certain thickness (such as D2), so that solder projection 205 is exposed in the first plastic packaging layer 206, as solder projection 205 expose to the first plastic packaging layer 206 behind the attenuate '.In cutting groove 210, cut afterwards, cutting mouth 212 shown in Fig. 2 M namely is the cutting vestige, and form the width of the cutter that cutting mouth 212 utilizes, less than the width that forms the cutter that cutting groove 210 utilizes, thereby chip 200 ' separate to obtain from wafer 200 encapsulating structure 200 of a plurality of wafer scale the most at last " A; the first plastic packaging layer 206 behind the attenuate ' in this cutting process, form cover top insulating medium layer 202 ' top plastic-sealed body 206 ", the second plastic packaging layer 211 in this cutting process, form cover bottom electrode metal layer 209 ' bottom plastic-sealed body 211 ', and bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover bottom electrode metal layer 209 ', vertical with horizontal expansion part 211 ' a extend laterally part 211 ' b also cover chip 200 ' sidewall, top insulating medium layer 202 ' sidewall, top plastic-sealed body 206 " sidewall; wherein, the part 211 ' b that extends laterally of bottom plastic-sealed body 211 ' comprise is that a part of plastic packaging material that the second plastic packaging layer 211 is filled in the cutting groove 210 forms through the cutting process shown in Fig. 2 M in fact.
Because in the preparation process shown in Fig. 2 J-2M, the substrate 200A that wafer 200 comprises is cut into the substrate unit 200 ' A of chip 200 ' comprise, so encapsulating structure 200 for the wafer scale shown in Fig. 2 M " for the A; among the silicon substrate unit 200 ' A of chip 200 ' comprise, the first kind that the contact first kind is arranged the metal material 208 of filling in the through hole 208 of solder joint 204a ' will contact with through hole 208 arrange solder joint 204a be electrically connected to bottom electrode metal layer 209 ' on.In an optional execution mode, chip 200 ' be the MOSFET of rectilinear (Vertical structure), also be that its principal current flow to the bottom from top device, or vice versa.Chip 200 ' the drain region usually be formed among substrate unit 200 ' A a side near chip 200 ' bottom surface, for strengthen bottom electrode metal layer 209 ' with the ohmic contact in chip 200 ' drain region, can be before the back side of the wafer 200 of depositing metal layers 209 to the attenuate, the back side heavy doping implantation ion identical with the drain region doping type of the wafer 200 behind attenuate.Because bottom electrode metal layer 209 ' contact consists of drain electrode near the drain region among the substrate unit 200 ' A of chip 200 ' bottom surface one side, thereby the drain electrode so the first kind that contacts with through hole 208 is arranged solder joint 204a with MOSFET is electrically connected the drain electrode that consists of rectilinear MOSFET, and in all arrangement solder joints 204, except the first kind is arranged solder joint 204a, consist of with arrangement solder joint 204 that through hole 208 contacts in, have at least a part to arrange solder joint 204 and be connected on the grid and source electrode of the MOSFET that is positioned at chip 200 ' end face one side, and consist of respectively gate electrode and the source electrode of rectilinear MOSFET.This shows, for the chip 200 of rectilinear MOSFET ' drain electrode originally be produced on the bottom electrode metal layer 209 of chip 200 ' bottom surface one side ' on, but the metal material 208 by filling in the through hole 208 ' first kind is arranged solder joint 204a with bottom electrode metal layer 209 ' formation electrically contacts, thus with the end leak the vertical stratification device in source, top the source, draining all is arranged on a side of chip 200 ' end face.Equally, if the side that the source of the vertical stratification device that top, source, the end need to be leaked, drain electrode all are arranged on chip 200 ' end face is as long as the first kind of selected through hole 208 contacts is arranged the source electrode that solder joint 204a is contact MOSFET bottom when forming through hole 208.It is worth mentioning that, in the RDL preparation flow, the first kind that contacts with through hole 208 is arranged the formed position of solder joint 204a, the insulating medium layer 202 that is arranged on the non-active device of the silicon substrate 200A unit area that covers, just be unlikely to when etched substrate 200A forms through hole 208 like this to destroy chip 200 ' integrated circuit unit.Particularly, the formation of any one through hole 208, must guarantee through hole 208 be formed on do not participate in consisting of chip 200 ' the silicon substrate area of circuit structure in.
For the ease of understanding, make an explanation with Fig. 1 F, the first kind that contacts with through hole 108 is arranged solder joint 104 formed positions, be the insulating medium layer 102 that is arranged on the non-active device of the substrate unit 100 ' A unit area (such as the Zone R territory) that covers, substrate unit 100 ' A comes from the cutting and separating of the substrate that the wafer to chip 100 places comprises.In the substrate unit 100 ' A in insulating medium layer 102 comprises among the figure part zone 102 ' cover on the non-active device unit area, the first kind arrange 104 of solder joints be formed on this part zone 102 ' in.What substrate unit 100 ' A comprised is used in the Zone R territory scope of receiving opening 108, do not prepare any efficient circuit unit that does not comprise in other words chip 100 in its transverse area (X-axis) and longitudinal region (Y-axis) and the vertical area (Z axis), simultaneously, the planar dimension of first kind arrangement solder joint 104 is chosen the planar dimension (transverse area and longitudinal region) that is not more than Zone R territory scope.
Referring to Fig. 3 A-3J, the present invention also is provided at the method for carrying out the another kind of wafer-level packaging of localized variation on Fig. 2 A-2M step, wafer 200 shown in Fig. 3 A is to have applied one deck at the wafer 200 shown in Fig. 2 B to cover the insulating medium layer 202 that is positioned at wafer 200 positive sides and the barrier layer 213 of arranging solder joint 204, form afterwards the opening 213 be arranged in barrier layer 213 ', and the first kind that opening 213 ' contact is arranged in the solder joint 204 is arranged solder joint 204a, opening 213 ' formation can carry out photoetching by the barrier layer 213 to photoresistance and so on, thereby selected opening 213 ' aim in vertical direction the first kind to arrange solder joint 204a.Afterwards by opening 213 ' this first kind is arranged the silicon substrate 200A that solder joint 204a and insulating medium layer 202, wafer 200 comprise carries out etching.Wherein, must ensure opening 213 ' planar dimension arrange the planar dimension of solder joint 204a less than the first kind, with guarantee the first kind arrange solder joint 204a only be exposed to opening 213 ' in the zone be etched away and be not that the first kind is arranged all zones of solder joint 204a and is etched away fully, consequently, thereby the first kind arrange solder joint 204a be exposed to opening 213 ' in the zone be etched away first at opening 213 ' expose insulating medium layer 202, continuation is carried out etching to the insulating medium layer 202 of opening 213 ' middle exposure, until at opening 213 ' expose silicon substrate 200A, and continue the silicon substrate 200A of opening 213 ' middle exposure is carried out etching, and etching stopping is in silicon substrate 200A, finally at insulating medium layer 202, form among the silicon substrate 200A of segment thickness and run through the through hole 214 that this first kind is arranged solder joint 204a, shown in Fig. 3 B, remove afterwards barrier layer 213.Usually after forming through hole 214, also will be at the isolation liner bed course of the inwall of through hole 214 deposition layer oxide film, so as for follow-up be filled in the through hole 214 metal material by the isolation liner bed course be looped around around the through hole 214 silicon substrate area insulate.
Shown in Fig. 3 C, settle solder projections 205 at the arrangement solder joint 204 that comprises first kind arrangement solder joint 204a, in this process, part scolder 214 ' flow into simultaneously and be filled in the through hole 214, solder projection 205 castings of this part scolder 214 ' arrange on the solder joint 204a with the first kind link together, and visible scolder 214 ' be is placed in the extension that the first kind that contacts with through hole 214 is arranged the solder projection 205 on the solder joint 204a.After finishing above-mentioned steps, carry out plastic packaging in the front of wafer 200, with the first plastic packaging layer 206 coated solder projection 205 and cover the insulating medium layer 202 in wafer 200 fronts, shown in Fig. 3 D.And carry out in the back side of wafer 200 that CMP grinds until the back side of the wafer 200 behind attenuate expose outside the scolder 214 that is filled in the through hole 214 ', shown in Fig. 3 E, the segment thickness of wafer 200 (such as D3) is polished.The back side of the wafer behind attenuate 200 covers layer of metal layer 209 again, such as chemical vapour deposition (CVD), shown in Fig. 3 F, this moment scolder 214 ' with metal level 209 maintenance electrical contacts.The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, form isolation adjacent chips 200 ' cutting groove 210, cutter divide cutting the first plastic packaging layer 206 on thickness top, this moment, cutting groove 210 stopped in the first plastic packaging layer 206, shown in Fig. 3 G.Rely on the first plastic packaging layer 206 and interconnect multiple chips 200 ' this moment, metal level 209 be cut into the bottom electrode metal layer 209 that is positioned at every chips 200 ' bottom surface ', insulating medium layer 202 also be cut into the top insulating medium layer 202 that is positioned at every chips 200 ' end face '.The back side of the wafer 200 after being coated with metal level 209 and being attenuate again, wafer 200 is carried out plastic packaging, this moment metal level 209 be cut into a plurality of bottom electrode metal layers 209 that are positioned at every chips 200 ' bottom surface ', but bottom electrode metal layer 209 ' still jointly the form metal level 209 of one deck globality, thereby finishing the part plastic packaging material that the second plastic packaging layer 211, the second plastic packaging layer 211 of forming covered with metal layer 209 behind the plastic packaging comprise also is filled in the cutting groove 210 simultaneously.Afterwards shown in Fig. 3 I, grind the first plastic packaging layer 206 with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, the segment thickness of the first plastic packaging layer 206 (such as D4) is polished.Referring to Fig. 3 J, in cutting groove 210, cut at last, with chip 200 ' separate, obtain the encapsulating structure 200 " B of the wafer scale shown in Fig. 3 J.In one embodiment, chip 200 ' with device and the indistinction shown in Fig. 2 M, be rectilinear MOSFET.The encapsulating structure 200 of wafer scale " among the B; in the etching process that through hole 214 forms; the result who produces is that through hole 214 runs through the first kind arrangement solder joint 204a that contacts with through hole 214; and scolder 214 ' generate simultaneously with the solder projection 205 of settling at first kind arrangement solder joint 204a, and the metal material of filling in the through hole 214 is the extension of arranging the solder projection 205 of settling on the solder joint 204a in the first kind.
Referring to Fig. 4 A-4E, the present invention also is provided at the method for carrying out the another kind of wafer-level packaging of other processing steps on the wafer 200 behind the attenuate shown in Fig. 2 E, it should be noted that, in this embodiment, that arrangement solder joint 104 with RDL design is as example, but it is noted that it is not necessary condition that the weld pad 101 of chip 100 end faces of Figure 1A is redesigned into arrangement solder joint 104.
Shown in Fig. 4 A, carry out plastic packaging in a side in wafer 200 fronts, also cover simultaneously insulating medium layer 202 with front and solder projection 205, the first plastic packaging layers 206 of the first plastic packaging layer 206 coated silicon wafer 200; Carry out CMP in the back side of wafer 200 and grind, and after the grinding back surface of finishing wafer 200, the back side that also is included in the wafer 200 behind the attenuate covers the step of layer of metal layer 209; The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, form isolation adjacent chips 200 ' cutting groove 210, the first plastic packaging layer 206 of segment thickness is cut to consist of the degree of depth that cutting groove 210 is arranged in the first plastic packaging layer 206, this moment, cutting groove 210 stopped in the first plastic packaging layer 206, also be rely on the first plastic packaging layer 206 multiple chips 200 ' this moment and mutually casting link together, simultaneously metal level 209 be cut into the bottom electrode metal layer 209 that covers every chips 200 ' bottom surface ', insulating medium layer 202 also be cut into the top insulating medium layer 202 that covers every chips 200 ' end face ', shown in Fig. 4 B.The back side of the wafer 200 after being coated with metal level 209 and being attenuate again, wafer 200 is carried out plastic packaging, finish the second plastic packaging layer 211 that forms covered with metal layer 209 behind the plastic packaging, the part plastic packaging material that comprises of the second plastic packaging layer 211 also is filled in the cutting groove 210 simultaneously, shown in Fig. 4 C.Grind again the first plastic packaging layer 206 after the first plastic packaging layer 206 obtains attenuates ', and with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, shown in Fig. 4 D.In cutting groove 210, cut, with chip 200 ' separate, obtain the encapsulating structure 200 of the wafer scale shown in Fig. 4 E " C, the first plastic packaging layer 206 behind the attenuate ' in this cutting process, form cover top insulating medium layer 202 ' top plastic-sealed body 206 ".In this execution mode, the arrangement solder joint 204 of unnecessary more selected chip 200 ' end faces make its by any through hole that is filled with metal material be connected to bottom electrode metal layer 209 ', so, this type of chip 200 ' type in, the arrangement solder joint 204 that carries out signal transmission with the external world is all in a side of its end face, and a side of its bottom surface does not then have to guide to the signal terminal of 200 ' end face, one side.Among the embodiment, two MOSFET (Common Drain MOSFET) of the common drain that chip 200 ' be is rectilinear, the drain electrode of the drain electrode of a MOSFET and another MOSFET is by bottom electrode metal layer 209 ' be electrically connected among two MOSFET, and at least a portion arrangement solder joint 204 is connected on the source electrode and gate electrode of any one MOSFET among two MOSFET, and consists of source electrode and the gate electrode of any one MOSFET among two MOSFET.In another embodiment, chip 200 ' in comprise at least a plurality of diodes that are integrated among the substrate 200A, and it is in parallel that an electrode terminal of diode is electrically connected at bottom electrode metal layer 209 ' upper formation jointly, at least a portion arrangement solder joint 204 has just consisted of respectively another electrode terminal of diode like this, and all is positioned at a side in chip 200 ' front.Encapsulating structure 200 " among the C; top insulating medium layer 202 ' the come from cutting of insulating medium layer 202; utilize weld pad 201 that heavy distribution technique will be distributed in chip 200 ' end face again layout designs become to be arranged in the top insulating medium layer 202 that covers chip ' arrangement solder joint 204; comprise the first plastic packaging layer 206 behind the attenuate ' in cutting process, form cover top insulating medium layer 202 ' top plastic-sealed body 206 ", the second plastic packaging layer 211 in cutting process, form cover bottom electrode metal layer 209 ' bottom plastic-sealed body 211 ', and bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover bottom electrode metal layer 209 ', vertical with horizontal expansion part 211 ' a extend laterally part 211 ' b also cover chip 200 ' sidewall, top insulating medium layer 202 ' sidewall, top plastic-sealed body 206 " sidewall; wherein; the part 211 ' b that extends laterally of bottom plastic-sealed body 211 ' comprise is that a part of plastic packaging material that the second plastic packaging layer 211 is filled in the cutting groove 210 forms through the cutting process shown in Fig. 4 E in fact, 205 of solder projections are in top plastic-sealed body 206 " in exposed.
In fact, can also be directly settle soldered balls and carry out the flow process of Fig. 4 A-4E at the weld pad 101 of chip 100 end faces of Figure 1A, and the type of chip is identical, only weld pad 101 is not redistribute through RDL, the process of also having lacked deposition one deck insulation insulating medium layer 202 therebetween is shown in Fig. 5 A-5F.Fig. 5 A directly settles first soldered ball 205 on the weld pad 201 of the wafer 200 shown in Fig. 2 A, protrude from solder projection 205 wafer 200 fronts (also be chip 200 ' end face) and that be electrically connected to chip 200 ' weld pad 201 thereby be formed with in the front of wafer 200, carry out plastic packaging in the front of wafer 200 afterwards, with front and the solder projection 205 of the first plastic packaging layer 206 coated silicon wafer 200; And carry out CMP at the back side of wafer 200 and grind, to finish after the grinding, the back side that also is included in the wafer 200 behind the attenuate covers the step of layer of metal layer 209, shown in Fig. 5 A-5B.The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, form isolation adjacent chips 200 ' cutting groove 210, the first plastic packaging layer 206 of segment thickness was cut and consisted of the degree of depth that cutting groove 210 is arranged in the first plastic packaging layer 206 this moment, cutting groove 210 stops in the first plastic packaging layer 206, also be to rely on the first plastic packaging layer 206 multiple chips 200 ' this moment and interconnect, simultaneously metal level 209 be cut into the bottom electrode metal layer 209 that is positioned at every chips 200 ' bottom surface '.The back side of the wafer 200 after being coated with metal level 209 and being attenuate again, wafer 200 is carried out plastic packaging, finish the second plastic packaging layer 211 that forms covered with metal layer 209 behind the plastic packaging, the part plastic packaging material that comprises of the second plastic packaging layer 211 also is filled in the cutting groove 210 simultaneously, shown in Fig. 5 D.Grind the first plastic packaging layer 206 with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, shown in Fig. 5 E.In cutting groove 210, cut, with chip 200 ' separate, obtain the encapsulating structure 200 " D of the wafer scale shown in Fig. 5 F.It should be noted that owing to do not form silicon through hole TSV in the step of this embodiment, so need not the position of considering that silicon through hole TSV will form.Therefore whether the weld pad 101 of chip 100 end faces of Figure 1A being redesigned into arrangement solder joint 104 neither necessary condition.Encapsulating structure 200 " among the D; chip 200 ' end face be formed with and protrude from solder projection 205 chip 200 ' end face and that be electrically connected to chip 200 ' weld pad 201; comprise the first plastic packaging layer 206 behind the attenuate ' in cutting process, form top plastic-sealed body 206 that covers chip 200 ' end face ", the second plastic packaging layer 211 in cutting process, form cover bottom electrode metal layer 209 ' bottom plastic-sealed body 211 ', and bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover bottom electrode metal layer 209 ', vertical with horizontal expansion part 211 ' a extend laterally part 211 ' b cover chip 200 ' sidewall, exposed in the top plastic-sealed body 206 " sidewall, solder projection 205 is in top plastic-sealed body 206 ".
Referring to Fig. 6 A-6E, the present invention also is provided at the method for carrying out the another kind of wafer-level packaging of other processing steps on the wafer 200 behind the attenuate shown in Fig. 2 E, it should be noted that in this embodiment, be with the difference of 4A-4E, not the backside deposition metal level of the wafer 200 behind attenuate.
Shown in Fig. 6 A, carry out plastic packaging in the front of wafer 200, also cover simultaneously insulating medium layer 202 with front and solder projection 205, the first plastic packaging layers 206 of the first plastic packaging layer 206 coated silicon wafer 200; Carry out CMP grinds in the back side of wafer 200, after finishing grinding back surface wafer 200 is cut, form isolation adjacent chips 200 ' cutting groove 210, this moment, cutting groove 210 stopped in the first plastic packaging layer 206, simultaneously insulating medium layer 202 also be cut into the top insulating medium layer 202 that is positioned at every chips 200 ' end face ', shown in Fig. 6 B.Plastic packaging is carried out to wafer 200 in the back side of the wafer behind attenuate 200 again, finishes and forms the second plastic packaging layer 211 behind the plastic packaging, and the part plastic packaging material that comprises of the second plastic packaging layer 211 also is filled in the cutting groove 210 simultaneously, shown in Fig. 6 C.Grind the first plastic packaging layer 206 so that solder projection 205 is exposed in the first plastic packaging layer 206, shown in Fig. 6 D, solder projection 205 be exposed to the first plastic packaging layer 206 behind the attenuate ' outside.In cutting groove 210, cut again, with chip 200 ' separate, obtain the encapsulating structure 200 of the wafer scale shown in Fig. 6 E " E, the first plastic packaging layer 206 behind the attenuate ' in this cutting process, form cover top insulating medium layer 202 ' top plastic-sealed body 206 ".In this execution mode, its back side does not deposit any metal level behind wafer 200 attenuates, chip 200 ' the bottom surface also without any the bottom electrode metal layer, chip 200 ' type be the IC of planar structure (Lateral structure), arrange the signal terminal that solder joint 204 consists of the IC of this planar structure, its all signal input output end all is arranged on a side of chip 200 ' end face.Encapsulating structure 200 " among the E; utilize weld pad 201 that heavy distribution technique will be distributed in chip 200 ' end face again layout designs become to be arranged in to cover chip 200 ' top insulating medium layer 202 ' arrangement solder joint 204; also comprise the covering top insulating medium layer 202 of the first plastic packaging layer 206 behind the attenuate ' in cutting process, form ' top plastic-sealed body 206 ", the second plastic packaging layer 211 forms the horizontal expansion part 211 ' a that covers chip 200 ' bottom surface in cutting process, and vertical with horizontal expansion part 211 ' a extend laterally part 211 ' b also cover chip 200 ' sidewall, top insulating medium layer 202 ' sidewall, exposed in the top plastic-sealed body 206 " sidewall, solder projection 205 is in top plastic-sealed body 206 ".
In the flow process of Fig. 6 A-6E, in another execution mode, can also be directly settle soldered balls and carry out the flow process of Fig. 6 A-6E at the weld pad 101 of chip 100 end faces of Figure 1A, only weld pad 101 is not redistribute through RDL, and the process of having lacked deposition one deck insulation insulating medium layer 202 is shown in Fig. 7 A-7E.Shown in Fig. 7 A, on the weld pad 201 of the wafer 200 shown in Fig. 2 A, directly plant soldered ball 205, and carry out plastic packaging in the front of wafer 200, with front and the solder projection 205 of the first plastic packaging layer 206 coated silicon wafer 200; Carry out CMP in the back side of wafer 200 and grind the thickness of attenuate substrate 200A; The back side of the wafer behind attenuate 200 afterwards, wafer 200 is cut, form isolation adjacent chips 200 ' cutting groove 210, this moment, cutting groove 210 stopped in the first plastic packaging layer 206, this moment, substrate 200A was divided into the substrate unit 200 ' A of every chips 200 ' comprise.Plastic packaging is carried out to wafer 200 in the back side of the wafer behind attenuate 200 again, forms the second plastic packaging layer 211, and the part plastic packaging material that while the second plastic packaging layer 211 comprises also is filled in the cutting groove 210, shown in Fig. 7 C.Grind the first plastic packaging layer 206 with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, shown in Fig. 7 D.In cutting groove 210, cut, with chip 200 ' separate, obtain the encapsulating structure 200 " F of the wafer scale shown in Fig. 7 E.Owing to do not form equally silicon through hole TSV in the step of this embodiment, need not the position of considering that silicon through hole TSV will form.Therefore the weld pad 101 of chip 100 end faces of Figure 1A being redesigned into arrangement solder joint 104 is not necessary condition.Encapsulating structure 200 " among the F; chip 200 ' type be the IC of planar structure; chip 200 ' end face be formed with and protrude from solder projection 205 chip 200 ' end face and that be electrically connected to chip 200 ' weld pad 201; comprise the first plastic packaging layer 206 behind the attenuate ' in cutting process, form top plastic-sealed body 206 that covers chip 200 ' end face ", the second plastic packaging layer 211 in cutting process, form the bottom plastic-sealed body 211 that covers chip 200 ' bottom surface ', bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover chip 200 ' bottom surface, vertical with horizontal expansion part 211 ' a extend laterally part 211 ' b also cover chip 200 ' sidewall, exposed in the top plastic-sealed body 206 " sidewall, solder projection 205 is in top plastic-sealed body 206 ".
Above embodiment all is that a side that is implemented in first the back side of wafer is cut the formation cutting groove, thereby the plastic packaging material in the cutting groove is cut chip is separated again.Following content will provide a side in the front that is implemented in first wafer to cut, and cut execution mode with separating chips in the back side of wafer one side again.
Referring to the method for a kind of wafer-level packaging of Fig. 8 A-8I, be formed with in the front of wafer 200 and protrude from solder projection 205 wafer 200 fronts and that be electrically connected to chip 200 ' weld pad 201, shown in Fig. 8 A-8B.And on weld pad 201, plant ball and settle solder projection 205, shown in Fig. 8 B, cut in the front of wafer 200 afterwards, formation be positioned at wafer 200 positive sides be used for isolating chip 200 ' cutting groove 215, and this cutting groove 215 stops among the substrate 200A of wafer 200, adjacent chip 200 ' between cutting groove 215 can locate to cut formation in the scribe line (Scribe Line) of wafer frontside.Carry out plastic packaging in the front of wafer 200 afterwards, with front and the solder projection 205 of the first plastic packaging layer 206 coated silicon wafer 200, shown in Fig. 8 C, the plastic packaging material that while the first plastic packaging layer 206 comprises also is filled in the cutting groove 215.Carry out again the CMP grinding at the back side of wafer 200 with the thickness of attenuate wafer 200, be the thickness of the substrate 200A that comprises of attenuate wafer 200, shown in Fig. 8 D, the segment thickness of wafer 200 (such as D5) is polished, the thickness that is substrate 200A obtains attenuate, can select afterwards the back side of the wafer 200 behind attenuate to carry out etching, with the remaining stressor layers in the back side of the wafer 200 after repairing the lattice damage that its grinding causes or eliminating attenuate.Shown in Fig. 8 E, the back side of the wafer 200 behind attenuate covers layer of metal layer 209.The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, formation be positioned at wafer 200 back sides one side behind the attenuate be used for isolating chip 200 ' cutting groove 216, and the cutting groove 216 that is arranged in wafer 200 back sides one side behind the attenuate stops at the substrate 200A of wafer 200 and further contacts with the plastic packaging material that is filled in the cutting groove 215 that is arranged in wafer 200 positive sides, namely keep cutting groove 216 to aim in vertical direction and be in contact with one another with cutting groove 215, shown in Fig. 8 F.Simultaneously metal level 209 be cut into the bottom electrode metal layer 209 that covers every chips 200 ' bottom surface '.Plastic packaging is carried out to wafer 200 in the back side of the wafer 200 behind attenuate, formation coats the second plastic packaging layer 211 at the back side of the wafer 200 behind the attenuate, the second plastic packaging layer 211 is while covered with metal layer 209 also, simultaneously the plastic packaging material that comprises of the second plastic packaging layer 211 also is filled in the cutting groove 216 that is arranged in wafer 200 back sides one side behind the attenuate, shown in Fig. 8 G.Grind afterwards the first plastic packaging layer 206 with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, obtain the first plastic packaging layer 206 of attenuate among Fig. 8 H '.Simultaneously the cutting groove 215 of wafer 200 back sides one side in the cutting groove 216 that is arranged in wafer 200 positive sides, after being arranged in attenuate cuts, with a plurality of chips 200 ' separate to obtain encapsulating structure 200 of wafer scale " G; shown in Fig. 8 I, the first plastic packaging layer 206 behind the attenuate ' in this cutting process, form top plastic-sealed body 206 that covers chip 200 ' front ".
The encapsulating structure 200 of wafer scale " among the G; comprise coating chip 200 ' top plastic-sealed body 206 ", top plastic-sealed body 206 " horizontal expansion part 206 " a cover chip 200 ' the front, with top plastic-sealed body 206 " horizontal expansion part 206 " the top plastic-sealed body 206 that a is vertical " extend laterally part 206 " b simultaneously also with chip 200 ' a part of sidewall covered, and solder projection 205 is in top plastic-sealed body 206 " in exposed.Also comprise coating chip 200 ' bottom plastic-sealed body 211 ', bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover chip 200 ' the bottom surface, and also cover simultaneously bottom electrode metal layer 209 ' on; With bottom plastic-sealed body 211 ' the vertical bottom plastic-sealed body 211 of horizontal expansion part 211 ' a ' extend laterally part 211 ' b, simultaneously also with chip 200 ' an other part do not extended laterally part 206 " sidewall that b coats is covered, top plastic-sealed body 206 this moment " extend laterally part 206 " b and bottom plastic-sealed body 211 ' extend laterally that part 211 ' b is in contact with one another and with chip 200 ' seamless sealing.In a kind of execution mode, the deposition process of cancellation metal level 209 in above-mentioned preparation flow, then just do not exist in the device of follow-up acquisition bottom electrode metal layer 209 ', this moment chip 200 ' be the IC of planar structure, its all signal input output end all is arranged on a side of chip 200 ' end face.In a kind of execution mode, comprise bottom electrode metal layer 209 ' chip 200 ' then can be two MOSFET of rectilinear common drain; And the drain electrode of the drain electrode of a MOSFET and another MOSFET is by described bottom electrode metal layer 209 ' be electrically connected among two MOSFET, and at least a portion is arranged source electrode and gate electrode that solder joint 204 consists of respectively any one MOSFET among couple MOSFET.In a kind of execution mode, comprise bottom electrode metal layer 209 ' chip 200 ' in comprise at least a plurality of diodes, and an electrode terminal of described diode is electrically connected on the bottom electrode metal layer 209 jointly ', and at least a portion is arranged another electrode terminal that solder joint 204 consists of respectively described diode, another electrode terminal of a diode of each arrangement solder joint 204 formation.
Based on Fig. 8 A-8I, packaging body 200 " G can also be prepared according to the flow process shown in Fig. 9 A-9E; finish the front of plastic packaging wafer 200 among Fig. 8 C; after the front and solder projection 205 with the first plastic packaging layer 206 coated silicon wafer 200; shown in Fig. 9 A; grind first the first plastic packaging layer 206 with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, carry out again CMP at the back side of wafer 200 and grind thickness with attenuate wafer 200, shown in Fig. 9 B.After the segment thickness of wafer 200 (such as D6) was polished, the back side that can select to carry out etching and the wafer behind attenuate 200 in the back side of the wafer 200 behind the attenuate covered layer of metal layer 209, such as Fig. 9 C.The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, formation be positioned at wafer 200 back sides one side behind the attenuate be used for isolating chip 200 ' cutting groove 216, and the cutting groove 216 that is arranged in wafer 200 back sides one side behind the attenuate stops at the substrate 200A of wafer 200 and further contacts with the plastic packaging material that is filled in the cutting groove 215 that is arranged in wafer 200 positive sides, namely keep cutting groove 216 to aim in vertical direction and be in contact with one another with cutting groove 215, shown in Fig. 9 D.Plastic packaging is carried out to wafer 200 in the back side of the wafer behind attenuate 200 again, formation coats the second plastic packaging layer 211 at the back side of the wafer 200 behind the attenuate, the second plastic packaging layer 211 is while covered with metal layer 209 also, simultaneously the plastic packaging material that comprises of the second plastic packaging layer 211 also is filled in the cutting groove 216 that is arranged in wafer 200 back sides one side behind the attenuate, shown in Fig. 9 E.At this moment, Fig. 9 E is Fig. 8 H, both and indistinction.The encapsulating structure 200 of the wafer scale shown in Fig. 8 I " among the G; comprise coating chip 200 ' top plastic-sealed body 206 ", top plastic-sealed body 206 " horizontal expansion part 206 " a cover chip 200 ' the front, with top plastic-sealed body 206 " horizontal expansion part 206 " the top plastic-sealed body 206 that a is vertical " extend laterally part 206 " b simultaneously also with chip 200 ' partial sidewall covered, and solder projection 205 is in top plastic-sealed body 206 " in exposed; The second plastic packaging layer 211 in cutting process, form cover bottom electrode metal layer 209 ' bottom plastic-sealed body 211 ', bottom plastic-sealed body 211 ' horizontal expansion part 211 " a cover chip 200 ' the bottom surface bottom electrode metal layer 209 ' on; with bottom plastic-sealed body 211 ' horizontal expansion part 211 " the bottom plastic-sealed body 211 that a is vertical ' extend laterally part 211 " b simultaneously also with chip 200 ' other a part of sidewall covered, then just top plastic-sealed body 206 " extend laterally part 206 " b and bottom plastic-sealed body 211 ' extend laterally part 211 " b be in contact with one another and with chip 200 ' seamless sealing.
Flow process shown in above-mentioned Fig. 8 A-8I or the 9A-9E is applicable to the preparation of the MOSFET of the IC of planar structure and vertical stratification, and equally also is applicable to via the RDL technical finesse or does not pass through the preparation of the chip of RDL technical finesse.
Method referring to a kind of wafer-level packaging of Figure 10 A-10G, in conjunction with Figure 1B-1D, utilize weld pad 201 that heavy distribution technique RDL will be distributed in chip 200 ' end face again layout designs become to be arranged in to cover chip 200 ' the arrangement solder joint 204 of insulating medium layer 202, shown in Figure 10 A.And on arrangement solder joint 204, plant ball and settle solder projection 205, cut in the front of wafer 200 afterwards, formation be positioned at wafer 200 positive sides be used for isolating chip 200 ' cutting groove 215, and this cutting groove 215 stops among the substrate 200A of wafer 200.Carry out plastic packaging in the front of wafer 200 afterwards, with the first plastic packaging layer 206 coated insulation dielectric layer 202 and solder projection 205, shown in Figure 10 B, the plastic packaging material that while the first plastic packaging layer 206 comprises also is filled in the cutting groove 215.Carry out again the CMP grinding at the back side of wafer 200 with the thickness of attenuate wafer 200, shown in Figure 10 C, can select afterwards the back side of the wafer 200 behind attenuate to carry out etching, and the back side of the wafer behind attenuate 200 covers layer of metal layer 209.The back side of the wafer 200 after being coated with metal level 209 and being attenuate afterwards, wafer 200 is cut, formation be positioned at wafer 200 back sides one side behind the attenuate be used for isolating chip 200 ' cutting groove 216, and the cutting groove 216 that is arranged in wafer 200 back sides one side behind the attenuate stops at the substrate 200A of wafer 200 and further contacts with the plastic packaging material that is filled in the cutting groove 215 that is arranged in wafer 200 positive sides, namely keep cutting groove 216 to aim in vertical direction and be in contact with one another with cutting groove 215, shown in Figure 10 D.Metal level 209 be cut into the bottom electrode metal layer 209 that is positioned at every chips 200 ' bottom surface '.Plastic packaging is carried out to wafer 200 in the back side of the wafer 200 behind attenuate, formation coats the second plastic packaging layer 211 at the back side of the wafer 200 behind the attenuate, the second plastic packaging layer 211 is while covered with metal layer 209 also, simultaneously the plastic packaging material that comprises of the second plastic packaging layer 211 also is filled in the cutting groove 216 that is arranged in wafer 200 back sides one side behind the attenuate, shown in Figure 10 E.Grind the first plastic packaging layer 206 with the first plastic packaging layer 206 of solder projection 205 behind attenuate ' in exposed, obtain the first plastic packaging layer 206 of attenuate among Figure 10 F '.Simultaneously in the cutting groove 216 that is arranged in wafer 200 positive sides, the cutting groove 215 that is arranged in wafer 200 back sides one side behind the attenuate cuts, with a plurality of chips 200 ' separate to obtain encapsulating structure 200 of wafer scale " H; shown in Figure 10 G; insulating medium layer 202 also be cut into the top insulating medium layer 202 that is positioned at every chips 200 ' end face '; the first plastic packaging layer 206 behind the attenuate ' in this cutting process, form cover top insulating medium layer 202 ' top plastic-sealed body 206 ", and the substrate 200A that comprises of wafer 200 is cut into the substrate unit 200 ' A of each chip 200 ' comprise.
In the method flow shown in Figure 10 A-10G, before the back side that covers the wafer 200 of layer of metal layer 209 to the attenuate, can also select implementation of class like the step of 2F-2I: backside coating one deck barrier layer 207 of the wafer 200 behind attenuate, and form the opening 207 that is arranged in barrier layer 207 '; Etching is carried out at the back side of the wafer 200 by opening 207 ' behind attenuate, forms the through hole 208 that the contact first kind is arranged solder joint 204a in substrate 200A that wafer comprises and insulating medium layer 202, removes afterwards barrier layer 207; Filling metal material 208 ' to described through hole 208, and the layer of metal layer 209 that the back side of the wafer behind attenuate 200 covers is by being filled in metal material 208 in the described through hole 208 ' be electrically connected to the first kind that contacts with through hole 208 to arrange on the solder joint 204a, the position that the described first kind that selection this moment contacts with through hole 208 is arranged solder joint 204a is arranged in the insulating medium layer 202 on the non-active device of the substrate 200A unit area that covers.
In the method flow shown in Figure 10 A-10G, before settling solder projection 205 on the arrangement solder joint 204, can also select implementation of class like the step of Fig. 3 A-3F: apply one deck and coat the insulating medium layer 202 that is positioned at wafer 200 fronts and the barrier layer 213 of arranging solder joint 204, and form be arranged in the barrier layer 213 contact first kind arrange the opening 213 of solder joint 204a '; By described opening 213 ' to the described first kind arrange solder joint 204a and insulating medium layer 202, substrate 200A carries out etching, in substrate 200A and insulating medium layer 202, form and run through the through hole 214 that this first kind is arranged solder joint 204a, and remove barrier layer 213; Afterwards when arranging solder joint 204 and settling solder projections 205, part scolder 214 ' also be filled in the lump in the described through hole 214.In this flow process, carry out in the process of lapping in the back side of wafer 200, the back side of the wafer 200 behind attenuate expose outside the scolder 214 that is filled in the through hole 214 ', and afterwards the layer of metal layer 209 that covers of the back side of the wafer behind attenuate 200 by being filled in scolder 214 in the through hole 214 ' be electrically connected at the first kind that contacts with through hole 214 to arrange on the solder joint 204a.
The encapsulating structure 200 of wafer scale " among the H; coating chip 200 ' top plastic-sealed body 206 ", top plastic-sealed body 206 " horizontal expansion part 206 " a cover top insulating medium layer 202 ' on, with top plastic-sealed body 206 " horizontal expansion part 206 " the top plastic-sealed body 206 that a is vertical " extend laterally part 206 " b simultaneously also with top insulating medium layer 202 ' sidewall, chip 200 ' partial sidewall covered, and solder projection 205 is in top plastic-sealed body 206 " in exposed; And coating chip 200 ' bottom plastic-sealed body 211 ', the bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover chip 200 ' the bottom surface, with bottom plastic-sealed body 211 ' the vertical bottom plastic-sealed body 211 of horizontal expansion part 211 ' a ' extend laterally part 211 ' b simultaneously also with chip 200 ' other a part of sidewall covered, top plastic-sealed body 206 " extend laterally part 206 " b and bottom plastic-sealed body 211 ' the part 211 ' b that extends laterally be in contact with one another with chip 200 ' seamless sealing.Also be included in one deck bottom electrode metal layer 209 that chip 200 ' bottom surface covers ', bottom plastic-sealed body 211 ' horizontal expansion part 211 ' a cover chip 200 ' the bottom surface time also cover bottom electrode metal layer 209 '.Can also include the through hole 208 shown in similar Fig. 2 M among Figure 10 G, this moment chip 200 ' be rectilinear MOSFET, be formed on chip 200 ' substrate unit 200 ' A that comprises and the through hole 208 of top insulating medium layer 202 ' middle contact first kind arrangement solder joint 204a, and the first kind of the metal material 208 of filling in the through hole 208 ' will contact with through hole 208 arrange solder joint 204a be electrically connected to described bottom electrode metal layer 209 ' on, the drain electrode of bottom electrode metal layer 209 ' formation MOSFET.Wafer level packaging structure 200 " H-1 shown in Figure 10 H.In another embodiment, chip 200 among Figure 10 G ' also be rectilinear MOSFET, and can include the through hole 214 shown in similar Fig. 3 J, through hole 214 ran through the first kind that contacts with through hole 214 and arranged solder joint 204a this moment, and the first kind that will contact with through hole 214 arrange solder joint 204a be electrically connected to bottom electrode metal layer 209 ' on; And the planar cross-sectional size of through hole 214 is less than the planar dimension of arranging solder joint 204, and the metal material of filling in the through hole 214 is to be placed in the extension that the first kind is arranged the solder projection 205 on the solder joint 204a, the wafer level packaging structure 200 " H-2 shown in Figure 10 I.
In above-described embodiment, finish to the first plastic packaging layer 206 grind the first plastic packaging layer 206 behind attenuate of rear acquisition ' end face, and can select in this process of lapping solder projection 205 carried out that part is ground until solder projection 205 expose to the first plastic packaging layer 206 behind the attenuate ', simultaneously solder projection 205 since be polished the first plastic packaging layer 206 after the surface (mark) that forms exposes to attenuate ' (also namely expose to top plastic-sealed body 206 "), and the first plastic packaging layer 206 behind the surface of solder projection 205 and the attenuate ' end face (also be top plastic-sealed body 206 " end face) maintenance coplanar.So in formed each packaging body, top plastic-sealed body 206 " solder projection 205 is not enveloped fully; but top plastic-sealed body 206 " be centered around solder projection 205 the side around, and top plastic-sealed body 206 " end face and any one solder projection 205 expose to top plastic-sealed body 206 " surface co-planar.In the above-described embodiments, can utilize different capsulation materials to carry out first plastic packaging layer 206, the second plastic packaging layer 211 of plastic package process to obtain respectively different plastic packaging materials.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, for example, this case is to set forth with MOSFET, the two MOSFET of common drain, based on the present invention's spirit, chip also can be done the conversion of other types.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.

Claims (29)

1. the method for a wafer-level packaging is characterized in that, may further comprise the steps:
One wafer that includes a plurality of chips is provided, forms the solder projection that protrudes from wafer frontside and be electrically connected to chip pad in the front of wafer,
The front of the described wafer of plastic packaging is with front and the solder projection of the first plastic packaging layer coated silicon wafer;
Grind at the back side in wafer;
Cut wafer at the back side of the wafer behind attenuate, form the cutting groove of isolating chip, and cutting groove stops in the first plastic packaging layer;
Plastic packaging is carried out to wafer in the back side of the wafer behind attenuate, and formation coats the second plastic packaging layer at the back side of the wafer behind the attenuate, and plastic packaging material also is filled in the cutting groove simultaneously;
Grind the first plastic packaging layer being exposed in the first plastic packaging layer of solder projection behind attenuate;
Cut in described cutting groove, chip is separated, described the first plastic packaging layer and the second plastic packaging layer coat the chip of described separation, are exposed in the first plastic packaging layer of described solder projection behind attenuate.
2. the method for claim 1, it is characterized in that, also be included in after the grinding back surface of wafer the back side of the wafer behind attenuate, penetrate substrate and the insulating medium layer that wafer comprises and form the through hole of contact first kind weld pad, and fill metal material to described through hole; The position of described the first weld pad that contacts with through hole is positioned on the insulating medium layer on the non-active device of the substrate that the covers wafer unit area.
3. method as claimed in claim 2 is characterized in that, after forming described through hole, also the inwall at described through hole deposits the isolation liner bed course, and the metal material of filling by the isolation liner bed course be looped around around the through hole the substrate region insulation.
4. method as claimed in claim 3 is characterized in that, also covers the back side of the wafer of layer of metal layer to the attenuate.
5. method as claimed in claim 4 is characterized in that, described chip is rectilinear MOSFET, and described metal layer on back is electrically connected to the drain electrode that described first kind weld pad consists of described MOSFET by the metal material of described filling vias.
6. method as claimed in claim 2 is characterized in that, the planar cross-sectional size of formed through hole is less than the planar dimension of weld pad.
7. the method for claim 1 is characterized in that, the front that also is included in wafer forms before the solder projection, in the front of wafer, penetrates the substrate that first kind weld pad, insulating medium layer and part wafer comprise, and forms the through hole of contact first kind weld pad; The position of described the first weld pad is positioned on the insulating medium layer on the non-active device of the substrate that the covers wafer unit area; And
Settle in the process of solder projection on described weld pad, the part scolder is filled in the described through hole simultaneously.
8. method as claimed in claim 7, it is characterized in that, after forming described through hole, also the inwall at described through hole deposits the isolation liner bed course, and is filled in scolder in the described through hole by isolation liner bed course and the substrate region insulation that is looped around around the through hole.
9. method as claimed in claim 8 is characterized in that, also covers the back side of the wafer of layer of metal layer to the attenuate.
10. method as claimed in claim 9 is characterized in that, described chip is rectilinear MOSFET, and described metal layer on back is electrically connected to the drain electrode that described first kind weld pad consists of described MOSFET by the scolder of described filling vias.
11. method as claimed in claim 7 is characterized in that, the mode that forms through hole is dry etching or wet etching or laser ablation.
12. the method for claim 1 is characterized in that, and is further comprising the steps of:
Before carrying out plastic packaging in the front of wafer, cut in the front of wafer, form the cutting groove that is used for isolating chip that is positioned at wafer frontside one side, and this cutting groove stops in the substrate that wafer comprises;
In the process of the first plastic packaging layer in the front that forms coated silicon wafer, plastic packaging material also is filled in the cutting groove that is arranged in wafer frontside one side;
And forming the cutting groove be arranged in wafer rear one side behind the attenuate stops at substrate and further contacts with the plastic packaging material that is filled in the cutting groove that is arranged in wafer frontside one side.
13. method as claimed in claim 12 is characterized in that, after grinding was finished at the back side of wafer, etching was carried out at the back side that also is included in the wafer behind the attenuate, and covered the step at the back side of the wafer of layer of metal layer to the attenuate; And
Formation is arranged in the process of the cutting groove that is used for isolating chip of wafer rear one side behind the attenuate, and cut wafer at the back side that is coated with metal level of the wafer behind attenuate; And
In the process of the second plastic packaging layer at the back side of the wafer after forming the coating attenuate, described the second plastic packaging layer also coats described metal level simultaneously.
14. method as claimed in claim 12 is characterized in that, and is before the back side that covers the wafer of layer of metal layer to the attenuate, further comprising the steps of:
Backside coating one deck barrier layer of the wafer behind attenuate, and form the opening that is arranged in the barrier layer;
Carry out etching by the back side that is opened on the wafer behind the attenuate, in substrate that wafer comprises and insulating medium layer, form the through hole of contact first kind weld pad, and remove the barrier layer;
Fill metal material to described through hole, and the layer of metal layer that the back side of the wafer behind attenuate covers is electrically connected on the first kind weld pad that contacts with through hole by the metal material that is filled in the described through hole.
15. method as claimed in claim 14 is characterized in that, the position of the described first kind weld pad that contacts with through hole is arranged in the insulating medium layer on the non-active device of the substrate that the covers unit area.
16. method as claimed in claim 12 is characterized in that, and is before settling solder projection on the weld pad, further comprising the steps of:
Apply the barrier layer that one deck coats the insulating medium layer and the weld pad that are positioned at wafer frontside, and form the opening that is arranged in barrier layer contact first kind weld pad;
By described opening described first kind weld pad and insulating medium layer, substrate are carried out etching, form the through hole that runs through this first kind weld pad and insulating medium layer and end at substrate one predetermined depths, and remove the barrier layer;
When weld pad was settled solder projection, the part scolder also was filled in the described through hole in the lump afterwards.
17. method as claimed in claim 16, it is characterized in that, carry out in the process of lapping in the back side of wafer, the back side of the wafer behind attenuate exposes outside the scolder that is filled in the through hole, and the layer of metal layer of the afterwards back side covering of the wafer behind attenuate is electrically connected on the first kind weld pad that contacts with through hole by the scolder that is filled in the through hole.
18. the method for claim 1 is characterized in that, finishes after the grinding back surface of wafer, the back side that also is included in the wafer behind the attenuate covers the step of layer of metal layer; And
In the process of the cutting groove that forms isolating chip, cut wafer at the back side that is coated with metal level of the wafer behind attenuate; And
In the process of the second plastic packaging layer at the back side of the wafer after forming the coating attenuate, described the second plastic packaging layer is the while covered with metal layer also.
19. method as claimed in claim 18 is characterized in that, described chip is two MOSFET of rectilinear common drain; And
The drain electrode of the drain electrode of a MOSFET and another MOSFET is electrically connected by described metal level among two MOSFET, and at least a portion weld pad consists of respectively source electrode and the gate electrode of any one MOSFET among two MOSFET.
20. the method for claim 1 is characterized in that, utilize weld pad that heavy distribution technique will be distributed in the chip end face again layout designs become to be arranged in the arrangement weld pad of the insulating medium layer that covers chip, on described arrangement weld pad, settle solder projection.
21. the encapsulating structure of a wafer scale in this encapsulating structure, is formed with at the end face of chip and protrudes from the solder projection chip end face and that be electrically connected to chip pad, it is characterized in that, also comprises:
Be coated on the top plastic-sealed body of chip end face, described top plastic-sealed body be centered around described solder projection the side around, the end face of described top plastic-sealed body and the surface co-planar that exposes to the top plastic-sealed body of any one described solder projection;
Coat the bottom plastic-sealed body of described chip bottom, the bottom surface of the horizontal expansion partial coverage chip of described bottom plastic-sealed body, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part is also covered the sidewall of chip simultaneously, and the part that extends laterally of described bottom plastic-sealed body is extended the described top of contact plastic-sealed body with the sealing that chip is seamless.
22. the encapsulating structure of wafer scale as claimed in claim 21 is characterized in that, also comprises one deck bottom electrode metal layer that covers die bottom surface, also covers the bottom electrode metal layer in the time of the back side of the horizontal expansion partial coverage chip of described bottom plastic-sealed body.
23. the encapsulating structure of wafer scale as claimed in claim 22 is characterized in that, also comprises
Be formed on the through hole of contact first kind weld pad in substrate unit that chip comprises and the top insulating medium layer, and the first kind weld pad that the metal material of filling in the through hole will contact with through hole is electrically connected on the described bottom electrode metal layer.
24. the encapsulating structure of wafer scale as claimed in claim 23 is characterized in that, also is provided with the isolation liner bed course on the inwall of described through hole, and the metal material of filling is by isolation liner bed course and the substrate region insulation that is looped around around the through hole.
25. the encapsulating structure of wafer scale as claimed in claim 24 is characterized in that, described through hole further runs through this first kind weld pad that contacts with through hole; And
The planar cross-sectional size of through hole is less than the planar dimension of weld pad, and the metal material of filling in the through hole is the extension that is placed in the solder projection on the first kind weld pad.
26. the encapsulating structure of wafer scale as claimed in claim 23 is characterized in that, described chip is rectilinear MOSFET, and the described first kind solder joint that contacts with through hole consists of the drain electrode of described MOSFET.
27. the encapsulating structure of wafer scale as claimed in claim 21 is characterized in that:
Described top plastic-sealed body comprises the horizontal expansion partial coverage in the front of chip, and the part that extends laterally of the top plastic-sealed body vertical with the horizontal expansion part of top plastic-sealed body is also covered the partial sidewall of chip simultaneously;
The bottom plastic-sealed body of coating chip, the horizontal expansion partial coverage of bottom plastic-sealed body is in the bottom surface of chip, the part that extends laterally of the bottom plastic-sealed body vertical with the horizontal expansion part of bottom plastic-sealed body is also covered other a part of sidewall of chip simultaneously, and the part that extends laterally of top plastic-sealed body is in contact with one another with the sealing that chip is seamless with extending laterally partly of bottom plastic-sealed body.
28. the encapsulating structure of wafer scale as claimed in claim 21 is characterized in that: described the first plastic-sealed body is comprised of different capsulation materials with described the second plastic-sealed body.
29. the encapsulating structure of wafer scale as claimed in claim 22 is characterized in that, described chip is two MOSFET of rectilinear common drain; And
The drain electrode of the drain electrode of a MOSFET and another MOSFET is electrically connected by described metal level among two MOSFET.
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