CN109844937B - Wafer level package with enhanced performance - Google Patents

Wafer level package with enhanced performance Download PDF

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Publication number
CN109844937B
CN109844937B CN201780062516.0A CN201780062516A CN109844937B CN 109844937 B CN109844937 B CN 109844937B CN 201780062516 A CN201780062516 A CN 201780062516A CN 109844937 B CN109844937 B CN 109844937B
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die
thinned
support pad
contacts
mold compound
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CN109844937A (en
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小梅里尔·阿尔贝特·哈彻
乔纳森·哈勒·哈蒙德
乔恩·查德威克
朱利奥·C·科斯塔
简·爱德华·万德梅尔
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Qorvo US Inc
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Qorvo US Inc
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00777—Preserve existing structures from alteration, e.g. temporary protection during manufacturing
    • B81C1/00785—Avoid chemical alteration, e.g. contamination, oxidation or unwanted etching
    • B81C1/00801—Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer
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Abstract

The present disclosure relates to a wafer level package including a first thinned die (12), a multilayer redistribution structure (18), a first mold compound (20), and a second mold compound (22). The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad (52 (1)) on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and surrounds the first thinned die and extends beyond a top surface of the first thinned die to define an opening (54) within the first mold compound and over the first thinned die. The second mold compound fills the opening and contacts the top surface of the first thinned die.

Description

Wafer level package with enhanced performance
RELATED APPLICATIONS
The present application claims the benefit of provisional patent application Ser. No. 62/374,304, filed 8/12/2016, the disclosure of which is hereby incorporated by reference in its entirety.
Technical Field
The present disclosure relates to a wafer level package and a process for manufacturing the same, and more particularly, to a wafer level package having enhanced thermal, electrical and rigidity properties, and a packaging process for enhancing the thermal, electrical and rigidity properties of a wafer level package.
Background
The widespread use of cellular devices and wireless devices has driven the rapid development of Radio Frequency (RF) technology. The substrate on which the RF device is fabricated plays an important role in achieving a high level of performance in RF technology. Fabrication of RF devices on conventional silicon substrates may benefit from low cost, high volume wafer production of silicon materials, robust semiconductor design tools, and robust semiconductor fabrication techniques.
Regardless of the benefits of using conventional silicon substrates for RF device fabrication, it is well known that conventional silicon substrates can have two undesirable properties for RF devices: harmonic distortion and low resistivity values. Harmonic distortion is a key obstacle to achieving high levels of linearity in RF devices built over silicon substrates. In addition, the low resistivity encountered in silicon substrates can degrade the quality factor (Q) of microelectromechanical systems (MEMS) or other passive components at high frequencies.
Furthermore, high speed and high performance transistors are more densely integrated in RF devices. Accordingly, the amount of heat generated by the RF device will increase significantly due to the large number of transistors integrated in the RF device, the large amount of power through the transistors, and the high operating speed of the transistors. Thus, there is a need to package RF devices in a configuration that achieves better heat dissipation.
Wafer Level Fan Out (WLFO) packaging technology and embedded wafer level ball grid array (EWLB) technology currently attract most of the attention in portable RF applications. WLFO and EWLB technologies are designed to provide high density input/output ports without increasing package size. This capability allows RF devices to be densely packed within a single wafer.
To accommodate increased heating of RF devices, to reduce unwanted harmonic distortion of RF devices, and to take advantage of the advantages of WLFO/EWLB packaging techniques, it is therefore an object of the present disclosure to provide improved packaging designs with enhanced performance. Furthermore, there is a need to enhance the performance of RF devices without increasing the package size.
Disclosure of Invention
The present disclosure relates to a wafer level package having enhanced thermal, electrical and rigidity properties, and a process for manufacturing the wafer level package. The disclosed wafer level package includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer and a first dielectric layer over the first device layer. The first device layer includes a number of first die contacts at a bottom surface of the first device layer. The multi-layered redistribution structure includes at least one first support pad, a plurality of package contacts, and a redistribution interconnect. Herein, the first thinned die resides over a top surface of the multilayer redistribution structure. The at least one first support pad is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die such that the at least one first support pad is placed directly under the first thinned die. The package contacts are also on the bottom surface of the multilayer redistribution structure. The redistribution interconnect connects the package contact to a particular one of the first die contacts. The at least one first support pad is electrically isolated from the package contacts. In addition, the first mold compound resides over the multilayer redistribution structure and surrounds the first thinned die and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The top surface of the first thinned die is exposed at the bottom of the opening. The second mold compound fills the opening and contacts the top surface of the first thinned die.
In one embodiment of the wafer level package, the at least one first support pad and the package contact are formed from a common conductive layer.
In one embodiment of the wafer level package, the bottom surface of the at least one first support pad and the bottom surface of each package contact are in the same plane.
In one embodiment of the wafer level package, the multilayer redistribution structure further comprises at least one second support pad on the bottom surface of the multilayer redistribution structure and not placed directly under the first thinned die. Herein, the at least one second support pad is electrically isolated from the package contacts.
In one embodiment of the wafer level package, the at least one first support pad and the at least one second support pad are separate.
In one embodiment of the wafer level package, the at least one first support pad and the at least one second support pad are connected together.
In one implementation of the wafer level package, the first thinned die provides a microelectromechanical system (MEMS) component.
In one implementation of the wafer level package, the first thinned die is formed of a silicon-on-insulator (SOI) structure. The first device layer of the first thinned die is formed from a silicon epitaxial layer of the SOI structure, and the first dielectric layer of the first thinned die is a buried oxide layer of the SOI structure.
According to a further embodiment, the wafer level package also includes a second complete die residing over the multilayer redistribution structure. Herein, the second complete die has a second device layer and a complete silicon substrate over the second device layer, and the first mold compound encapsulates the second complete die.
According to a further embodiment, the wafer level package further comprises a third thinned die residing over the multilayer redistribution structure. Herein, the third thinned die has a third device layer and a second dielectric layer over the third device layer. The first mold compound extends beyond a top surface of the third thinned die to define a second opening within the first mold compound and over the third thinned die. The top surface of the third thinned die is exposed at the bottom of the second opening. The second mold compound fills the second opening and contacts the top surface of the third thinned die.
In one embodiment of the wafer level package, the multilayer redistribution structure further comprises at least one second support pad and at least one third support pad, the at least one second support pad and the at least one third support pad being on the bottom surface of the multilayer redistribution structure. The at least one second support pad and the at least one third support pad are electrically isolated from the package contacts. The at least one second support pad is not placed directly under the first thinned die and is not placed directly under the third thinned die. The at least one third support pad is vertically aligned with the third thinned die such that the at least one third support pad is placed directly under the third thinned die.
In one implementation of the wafer level package, the first thinned die provides a MEMS component, the second complete die provides a Complementary Metal Oxide Semiconductor (CMOS) controller that controls the MEMS component, and the third thinned die is formed from an SOI structure. Herein, the third device layer of the third thinned die is formed from a silicon epitaxial layer of the SOI structure, and the second dielectric layer of the third thinned die is a buried oxide layer of the SOI structure.
In one embodiment of the wafer level package, the multilayer redistribution structure further comprises at least one structural pad. Herein, the at least one structural pad and the redistribution interconnect are formed from a common conductive layer. The at least one structural pad is located directly under the first thinned die and is electrically isolated from the redistribution interconnect.
In one embodiment of the wafer level package, the second mold compound has a thermal conductivity greater than 2W/m-K.
In one embodiment of the wafer level package, the second mold compound has a resistivity greater than 1E6 ohm-cm.
In one embodiment of the wafer level package, the first mold compound and the second mold compound are formed of the same material.
In one embodiment of the wafer level package, the first mold compound and the second mold compound are formed of different materials.
In one embodiment of the wafer level package, the multilayer redistribution structure is free of glass fibers.
In one implementation of the wafer level package, the connections between the redistribution interconnect and the plurality of first die contacts are free of solder.
In another embodiment, an exemplary wafer level package includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer and a first dielectric layer over the first device layer. The first device layer includes a number of first die contacts at a bottom surface of the first device layer. The multi-layer redistribution structure includes at least one structural pad, a number of package contacts, and a redistribution interconnect. Herein, the first thinned die resides over a top surface of the multilayer redistribution structure. The package contacts are on a bottom surface of the multilayer redistribution structure. The redistribution interconnect connects the package contact to a particular one of the first die contacts. The at least one structural pad and the redistribution interconnect are formed from a common conductive layer, but the at least one structural pad is electrically isolated from the redistribution interconnect. The at least one structural pad is placed directly under the first thinned die. In addition, the first mold compound resides over the multilayer redistribution structure and surrounds the first thinned die and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The top surface of the first thinned die is exposed at the bottom of the opening. The second mold compound fills the opening and contacts the top surface of the first thinned die.
According to an exemplary process, a die wafer having a first die and a first mold compound is provided. Herein, the first die includes a first device layer, a first dielectric layer over the first device layer, and a first silicon substrate over the first dielectric layer. The first device layer includes a number of first die contacts at a bottom surface of the first device layer. The top surface of the first die is a top surface of the first silicon substrate and the bottom surface of the first die is the bottom surface of the first device layer. The first mold compound encapsulates sides and the top surface of the first die, and the bottom surface of the first device layer is exposed. Next, a multi-layer redistribution structure is formed under the die wafer. The multi-layered redistribution structure includes at least one first support pad, a plurality of package contacts, and a redistribution interconnect. The at least one first support pad is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first die such that the at least one first support pad is placed directly under the first die. The package contacts are on the bottom surface of the multilayer redistribution structure and are electrically isolated from the at least one first support pad. The redistribution interconnect connects the package contact to a particular one of the first die contacts. The first mold compound is then thinned to expose the top surface of the first silicon substrate. The first silicon substrate of the first die is substantially removed to provide a first thinned die and a first opening formed within the first mold compound and over the first thinned die. The at least one first support pad is located directly under the first thinned die, and the first thinned die has a top surface exposed at a bottom of the first opening. Finally, a second mold compound is applied to substantially fill the opening and directly contact the top surface of the first thinned die.
Those skilled in the art will appreciate the scope of the present disclosure and appreciate additional aspects thereof upon reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.
Drawings
The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 illustrates an exemplary wafer level package according to one embodiment of the present disclosure.
Fig. 2 illustrates an alternative wafer level package according to another embodiment of the present disclosure.
Fig. 3 illustrates an alternative wafer level package according to another embodiment of the present disclosure.
Fig. 4-18 provide exemplary steps illustrating a process for manufacturing the exemplary wafer level package shown in fig. 1.
It will be appreciated that for clarity of illustration, fig. 1-18 may not be drawn to scale.
Detailed Description
The implementations set forth below represent the necessary information to enable those skilled in the art to practice the implementations and illustrate the best mode of practicing the implementations. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region or substrate is referred to as extending "over" or "over" another element, it can extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Relative terms such as "below" or "above" … … "or" upper "or" lower "or" horizontal "or" vertical "may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and the terms discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present disclosure relates to a wafer level package having enhanced thermal, electrical and rigidity properties, and a packaging process for manufacturing the wafer level package. Fig. 1 illustrates an exemplary wafer level package 10 according to one embodiment of the present disclosure. For illustration purposes, the exemplary wafer level package 10 includes a thinned silicon-on-insulator (SOI) die 12, a thinned microelectromechanical system (MEMS) die 14, a Complementary Metal Oxide Semiconductor (CMOS) controller die 16, a multilayer redistribution structure 18, a first mold compound 20, and a second mold compound 22. In different applications, the wafer level package 10 may include fewer or more thinned MEMS/SOI die, and may include other die, such as: thinned integrated passive device die (not shown). For example, in some applications, the wafer level package 10 may include only thinned MEMS die and CMOS controller die; while in some applications the wafer level package 10 may include only thinned SOI die.
In detail, thinned SOI die 12 includes a first device layer 24 and a first dielectric layer 26 over a top surface of first device layer 24. The first device layer 24 includes a number of first die contacts 28 on a bottom surface of the first device layer 24. Herein, thinned SOI die 12 is formed from an SOI structure, which refers to a structure that includes a silicon substrate, a silicon epitaxial layer, and a buried oxide layer sandwiched between the silicon substrate and the silicon epitaxial layer. The first device layer 24 of thinned SOI die 12 is formed by integrating electronic components (not shown) in or on the silicon epitaxial layer of the SOI structure. The first dielectric layer 26 of thinned SOI die 12 is a Buried Oxide (BOX) layer of the SOI structure. In addition, the silicon substrate of the SOI structure is substantially removed to complete thinned SOI die 12 (more details are discussed later). The first device layer 24 has a thickness between 0.1 μm and 50 μm and the first dielectric layer 26 has a thickness between 10nm and 2000 nm.
The thinned MEMS die 14 includes a second device layer 30 and a second dielectric layer 32 over a top surface of the second device layer 30. The second device layer 30 includes a MEMS component (not shown), typically a switch, and a number of second die contacts 34 on a bottom surface of the second device layer 30. A via structure (not shown) may be used to connect a MEMS component (not shown) to the second die contact 34. The second device layer 30 has a thickness of between 0.5 μm and 100 μm and may be formed of a combination of a dielectric layer and a metal layer (e.g., silicon oxide, silicon nitride, aluminum, titanium, copper, or the like). The second dielectric layer 32 has a thickness between 10nm and 10000nm and may be formed of silicon oxide, silicon nitride or aluminum nitride.
Note that thinned SOI die 12 and thinned MEMS die 14 are both thinned die having a device layer, a dielectric layer over the device layer, and substantially no silicon substrate over the dielectric layer. In this context, substantially no silicon substrate above the dielectric layer refers to a silicon substrate of at most 2 μm above the dielectric layer. In the desired case, each thinned die does not include any silicon substrate over the dielectric layer such that the top surface of each thinned die is the top surface of the dielectric layer. For other cases, the top surface of one thinned die may be the top surface of a thin silicon substrate.
The CMOS controller die 16 includes a third device layer 36 and a silicon substrate 38 over the third device layer 36. The third device layer 36 may include a CMOS controller (not shown) that controls MEMS components (not shown) within the thinned MEMS die 14, and a number of third die contacts 40 at the bottom surface of the third device layer 36. A via structure (not shown) may be used to connect a CMOS controller (not shown) to the third die contact 40. The third device layer 36 has a thickness of between 0.1 μm and 50 μm and may be formed from a combination of a dielectric layer and a metal layer (e.g., silicon oxide, silicon nitride, aluminum, titanium, copper, or the like). The CMOS controller die 16 is a complete die that includes a complete silicon substrate 38 having a thickness between 25 μm and 250 μm or between 10 μm and 750 μm.
Herein, the multilayer redistribution structure 18 includes a first dielectric pattern 42 on top, a number of redistribution interconnects 44, a second dielectric pattern 46, and a number of package contacts 48. In one embodiment, thinned SOI die 12, thinned MEMS die 14, and CMOS controller die 16 reside directly over multilayer redistribution structure 18. Thus, the first device layer 24 of the thinned SOI die 12, the second device layer 30 of the thinned MEMS die 14, and the third device layer 36 of the CMOS controller die 16 are in contact with the first dielectric pattern 42. In addition, the first die contact 28 on the bottom surface of the first device layer 24, the second die contact 34 on the bottom surface of the second device layer 30, and the third die contact 40 at the bottom surface of the third device layer 36 are exposed through the first dielectric pattern 42.
For illustration purposes, the redistribution interconnect 44 includes five first redistribution interconnects 44 (1) and one second redistribution interconnect 44 (2). In different applications, the redistribution interconnect 44 may include fewer or more first redistribution interconnect 44 (1)/second redistribution interconnect 44 (2). Each first redistribution interconnect 44 (1) connects one package contact 48 to a corresponding one of the first, second, and third die contacts 28, 34, and 40. The second redistribution interconnect 44 (2) is used to connect one second die contact 34 to a corresponding third die contact 40 such that a CMOS controller (not shown) within the CMOS controller die 16 electrically connects MEMS components (not shown) within the thinned MEMS die 14. Herein, each redistribution interconnect 44 is electrically coupled to at least one of the first, second, and third die contacts 28, 34, and 40 via the first dielectric pattern 42, and extends under the first dielectric pattern 42. The connections between the redistribution interconnect 44 and the first, second, and third die contacts 28, 34, and 40 are free of solder.
The second dielectric pattern 46 is formed under the first dielectric pattern 42. The second dielectric pattern 46 partially encapsulates each first redistribution interconnect 44 (1). Thus, a portion of each first redistribution interconnect 44 (1) is exposed through the second dielectric pattern 46. Furthermore, the second dielectric pattern 46 completely encapsulates the second redistribution interconnect 44 (2). Thus, no portion of the second redistribution interconnect 44 (2) is exposed through the second dielectric pattern 46. In different applications, there may be additional redistribution interconnects (not shown) electrically coupled to the redistribution interconnects 44 via the second dielectric patterns 46, and additional dielectric patterns (not shown) formed under the second dielectric patterns 46 for partially encapsulating each of the additional redistribution interconnects.
In this embodiment, each package contact 48 is on the bottom surface of the multilayer redistribution structure 18 and is electrically coupled to a corresponding first redistribution interconnect 44 (1) via a second dielectric pattern 46. Thus, the first redistribution interconnect 44 (1) connects the package contact 48 to a corresponding one of the first, second, and third die contacts 28, 34, and 40. Here, the package contacts 48 are separated from each other and extend under the second dielectric pattern 46 such that an air gap 50 is formed around each package contact 48. The air gap 50 may extend under at least 70% of the thinned SOI die 12 and/or under at least 70% of the thinned MEMS die 14.
In the present disclosure, the multilayer redistribution structure 18 may also include a number of support pads 52 that are placed on the bottom surface of the multilayer redistribution structure 18 and within the air gaps 50. The support pads 52 and the package contacts 48 may be formed of a common conductive layer (e.g., a metal layer) such that each support pad 52 and each package contact 48 have the same thickness protruding from the bottom surface of the second dielectric pattern 46. The bottom surface of each support pad 52 and the bottom surface of each package contact 48 are in the same plane. Herein, the support pads 52 are not in contact with any package contacts 48 and are electrically isolated from any package contacts 48.
Note that thinned SOI die 12 has a thickness between 0.1 μm and 50 μm, thinned MEMS die 14 has a thickness between 0.5 μm and 100 μm, and multilayer redistribution structure 18 has a thickness between 2 μm and 300 μm. Thus, a first combination of thinned SOI die 12 and a first portion of multilayer redistribution structure 18 directly under thinned SOI die 12, or a second combination of thinned MEMS die 14 and a second portion of multilayer redistribution structure 18 directly under thinned MEMS die 14, may have a thickness as thin as a few μm. If support pad 52 is not present within a first portion of air gap 50 located directly beneath thinned SOI die 12, then vertical deformation of the first combination may occur during the molding step (more details will be described in the subsequent manufacturing process). Similarly, if the support pad 52 is not present within a second portion of the air gap 50 located directly beneath the thinned MEMS die 14, then vertical deformation of the second combination may occur during the molding step (more details will be described in the subsequent manufacturing process). Without additional support within the first and second portions of the air gap 50, the first and second combinations are unable to withstand high vertical forming pressures.
Herein, the support pad 52 may include a first support pad 52 (1), a second support pad 52 (2), and a third support pad 52 (3). First support pad 52 (1) is on the bottom surface of multilayer redistribution structure 18 and vertically aligned with thinned SOI die 12. Thus, first support pad 52 (1) is placed directly under thinned SOI die 12. The first support pad 52 (1) forms a "standoff" within a first portion of the air gap 50 directly beneath the thinned SOI die 12. These "standoffs" provide mechanical support for thinned SOI die 12 to withstand high molding pressures (more details will be described in the subsequent manufacturing process). By reducing the distance between adjacent first support pads 52 (1) and/or reducing the distance between first support pads 52 (1) and adjacent package contacts 48, the vertical deformation of the first combination of thinned SOI die 12 and the first portion of multilayer redistribution structure 18 may be reduced to an acceptable level. The distance between adjacent first support pads 52 (1) may be between 1 μm and 100 μm, and the distance between the first support pads 52 (1) and the adjacent package contacts 48 may be between 1 μm and 100 μm. Further, each of the first support pads 52 (1) may have the same or different sizes, and may have the same or different shapes, such as square, rectangular, triangular, and circular. The size of each first support pad 52 (1) may be between 5 μm by 5 μm and 100 μm by 100 μm. The first support pad 52 (1) is sized and positioned to avoid coupling effects.
The second support pad 52 (2) is placed on the bottom surface of the multilayer redistribution structure 18, but not directly under the thinned SOI die 12 or directly under the thinned MEMS die 14. For example, the second support pad 52 (2) may be located directly under the first mold compound 20 and/or directly under the CMOS controller die 16. The second support pad 52 (2) provides additional mechanical support for the wafer level package 10 to withstand high molding pressures. The distance between adjacent second support pads 52 (2) may be between 1 μm and 100 μm, and the distance between the second support pads 52 (2) and the adjacent package contacts 48 may be between 1 μm and 100 μm. Further, each of the second support pads 52 (2) may have the same or different sizes, and may have the same or different shapes, such as square, rectangular, triangular, and circular. The size of each second support pad 52 (2) may be between 5 μm by 5 μm and 100 μm by 100 μm. The second support pad 52 (2) is sized and positioned to avoid coupling effects. In some applications, the second support pad 52 (2) may not be present (refer to no support pad 52 being located directly under the first mold compound 20 and/or CMOS controller die 16). If the first support pad 52 (1) is placed at a first average density and the second support pad 52 (2) is placed at a second average density, the second average density may be the same or different than the first average density. In this embodiment, it is desirable that the second average density is not greater than the first average density.
The third support pad 52 (3) is on the bottom surface of the multilayer redistribution structure 18 and vertically aligned with the thinned MEMS die 14. Thus, the third support pad 52 (3) is placed directly under the thinned MEMS die 14. The third support pad 52 (3) forms a "standoff" within the second portion of the air gap 50 directly beneath the thinned MEMS die 14 to provide mechanical support for the thinned MEMS die 14. By reducing the distance between adjacent third support pads 52 (3) and/or reducing the distance between third support pads 52 (3) and adjacent package contacts 48, the vertical deformation of the second combination of thinned MEMS die 14 and the second portion of the multilayer redistribution structure 18 may be reduced to an acceptable level. The distance between adjacent third support pads 52 (3) may be between 1 μm and 100 μm, and the distance between the third support pads 52 (3) and the adjacent package contacts 48 may be between 1 μm and 100 μm. Further, each third support pad 52 (3) may have the same or different sizes, and may have the same or different shapes, such as square, rectangular, triangular, and circular. The size of each third support pad 52 (3) may be between 5 μm by 5 μm and 100 μm by 100 μm. The third support pad 52 (3) is sized and positioned to avoid coupling effects. If the third support pad 52 (3) is placed at a third average density, the first average density, the second average density, and the third average density may be the same or different. In this embodiment, it is desirable that the second average density is not greater than the third average density, and the first average density may be substantially equal to the third average density.
Herein, the first support pad 52 (1), the second support pad 52 (2), and the third support pad 52 (3) have no electrical purpose, but enhance the rigidity (rigidity) of the entire wafer level package 10. The first support pad 52 (1), the second support pad 50 (2) and the third support pad 50 (3) are sized and positioned to reduce vertical deformation, as well as to minimize performance impact and to comply with manufacturability rules (lines, spaces). In some applications, there may be one continuous first support pad 52 (1) (not shown) instead of a number of discrete first support pads 52 (1) located directly under thinned SOI die 12. In some applications, there may be one continuous third support pad 52 (3) (not shown) instead of many discrete third support pads 52 (3) located directly under the thinned MEMS die 14. In some applications, the first, second, and third support pads 52 (1), 52 (2), and 52 (3) are connected together as one continuous support pad (not shown) that extends within the air gap 50 and is electrically isolated from any package contacts 48.
Furthermore, the multilayer redistribution structure 18 may be fiberglass free or glass free. Glass fibers are referred to herein as individual glass strands that become larger groupings by entanglement. These glass filaments may then be woven into a fabric. The first dielectric pattern 42 and the second dielectric pattern 46 may be formed of benzocyclobutene (BCB) or polyimide. The redistribution interconnect 44 may be formed of copper or other suitable metal. The package contacts 48 and the support pads 52 may be formed of at least one of copper, gold, nickel, and palladium.
A first mold compound 20 resides over the top surface of the multilayer redistribution structure 18, resides around the thinned SOI die 12 and the thinned MEMS die 14, and encapsulates the CMOS controller die 16. Further, the first mold compound 20 extends beyond the top surface of the thinned SOI die 12 to define a first opening 54 within the first mold compound 20 and above the thinned SOI die 12, and extends beyond the top surface of the thinned MEMS die 14 to define a second opening 56 within the first mold compound 20 and above the thinned MEMS die 14. Herein, the top surface of thinned SOI die 12 is exposed at the bottom of first opening 54 and the top surface of thinned MEMS die 14 is exposed at the bottom of second opening 56.
The second mold compound 22 substantially fills the first and second openings 54 and 56 and contacts the top surface of the thinned SOI die 12 and the top surface of the thinned MEMS die 14. The second mold compound 22 has a thermal conductivity greater than 2W/m-K or greater than 10W/m-K and has a resistivity greater than 1E6 ohm-cm. In general, the higher the thermal conductivity of the second mold compound 22, the better the thermal performance of the thinned SOI die 12 and the thinned MEMS die 14. Furthermore, the high resistivity of the second mold compound 22 may improve the quality factor (Q) of the MEMS component (not shown) of the thinned MEMS die 14 at high frequencies.
The second mold compound 22 may be formed from a thermoplastic or thermoset material such as PPS (polyphenylene sulfide), an overmolded epoxy doped with a boron nitride or aluminum oxide thermal additive, or the like. In some applications, if the wafer level package 10 includes only the thinned MEMS die 14 and the CMOS controller die 16, the second mold compound 22 may also be formed from an organic epoxy system having a thermal conductivity of less than 2W/mK. The second mold compound 22 may be formed of the same or different material as the first mold compound 20. However, unlike the second mold compound 22, the first mold compound 20 has no thermal conductivity or resistivity requirements. In some applications, both the first mold compound 20 and the second mold compound 22 have a thermal conductivity greater than 2W/mK. In some applications, the first mold compound 20 has a thermal conductivity of less than 2W/m-K and the second mold compound 22 has a thermal conductivity of greater than 2W/m-K. In some applications, the first mold compound 20 has a thermal conductivity greater than 2W/mK and the second mold compound 22 has a thermal conductivity greater than 10W/mK. Herein, a portion of the second mold compound 22 may reside above the top surface of the first mold compound 20. Note that the second mold compound 22 is separated from the CMOS controller die 16 by the first mold compound 20. The top surface of the CMOS controller die 16 is in contact with the first mold compound 20.
In another embodiment, the multilayer redistribution structure 18 may further include a number of structural pads 58 directly under the first dielectric pattern 42 and encapsulated by the second dielectric pattern 46, as shown in fig. 2. The structural pads 58 and the redistribution interconnects 44 may be formed from a common conductive layer (e.g., a metal layer), and thus, each of the structural pads 58 and each of the redistribution interconnects 44 have the same thickness protruding from the bottom surface of the first dielectric pattern 42. Thus, the thickness of the multilayer redistribution structure 18 does not increase. Herein, the structural pads 58 are not in contact with any of the redistribution interconnects 44 and are electrically isolated from the redistribution interconnects 44.
The structural pads 58 may include a first structural pad 58 (1) located directly under the thinned SOI die 12 and a second structural pad 58 (2) located directly under the thinned MEMS die 14. The first structure pad 58 (1) increases the structural rigidity of the multilayer redistribution structure 18 and allows the thinned SOI die 12 to withstand high molding pressures. Thus, the vertical deformation of the first combination of thinned SOI die 12 and the first portion of the multilayer redistribution structure 18 may be reduced to an acceptable level. The distance between adjacent first structural pads 58 (1) may be between 1 μm and 100 μm, and the distance between the first structural pads 58 (1) and adjacent redistribution interconnects 44 may be between 1 μm and 100 μm. Furthermore, each first structural pad 58 (1) may have the same or different sizes and may have the same or different shapes, such as square, rectangular, triangular, and circular. The size of each first structural pad 58 (1) may be between 5 μm by 5 μm and 100 μm by 100 μm. The first structural pad 58 (1) is sized and positioned to avoid coupling effects.
Similarly, the second structural pads 58 (2) increase the structural rigidity of the multilayer redistribution structure 18 and allow the thinned MEMS die 14 to withstand high molding pressures. Thus, the vertical deformation of the second combination of thinned MEMS die 14 and the second portion of the multilayer redistribution structure 18 may be reduced to an acceptable level. The distance between adjacent second structural pads 58 (2) may be between 1 μm and 100 μm, and the distance between the second structural pads 58 (2) and the adjacent redistribution interconnect 44 may be between 1 μm and 100 μm. Furthermore, each second structural pad 58 (2) may have the same or different sizes and may have the same or different shapes, such as square, rectangular, triangular, and circular. The size of each second structural pad 58 (2) may be between 5 μm by 5 μm and 100 μm by 100 μm. The second structural pad 58 (2) is sized and positioned to avoid coupling effects. In some applications, there may be one continuous first structural pad 58 (1) (not shown) instead of many discrete first structural pads 58 (1) located directly under thinned SOI die 12. In some applications, there may be one continuous second structural pad 58 (2) (not shown) instead of many discrete second structural pads 58 (2) located directly under the thinned MEMS die 14.
In another embodiment, the multilayer redistribution structure 18 may include the structural pads 58, but not the support pads 52, as shown in fig. 3. Although there are no additional supports within the first portion of the air gap 50 directly beneath the thinned SOI die 12, the first structural pad 58 (1) increases the structural rigidity of the multilayer redistribution structure 18 such that the first combination of the thinned SOI die 12 and the first portion of the multilayer redistribution structure 18 may still be sufficiently rigid to withstand high molding pressures. The vertical deformation of the first combination of thinned SOI die 12 and the first portion of multilayer redistribution structure 18 may be reduced to an acceptable level. Similarly, although there are no additional supports within the second portion of the air gap 50 located directly beneath the thinned MEMS die 14, the second structural pads 58 (1) increase the structural rigidity of the multilayer redistribution structure 18 such that the second combination of the thinned MEMS die 14 and the second portion of the multilayer redistribution structure 18 may still have sufficient rigidity to withstand high molding pressures. The vertical deformation of the second combination of thinned MEMS die 14 and the second portion of the multilayer redistribution structure 18 may be reduced to an acceptable level.
Fig. 4-18 provide exemplary steps for fabricating the exemplary wafer level package 10 shown in fig. 1. Although the exemplary steps are described as being continuous, the exemplary steps need not be sequential. Some steps may be performed in an order different than presented. Furthermore, processes within the scope of the present disclosure may include fewer or more steps than those illustrated in fig. 4-18.
Initially, an adhesive layer 60 is applied to the top surface of the carrier 62, as shown in fig. 4. SOI die 12D, MEMS die 14D and CMOS controller die 16 are then attached to adhesive layer 60, as shown in fig. 5. Fewer or more dies may be attached to the adhesive layer 60 in different applications. For example, in some applications, only one SOI die 12D may be attached to adhesive layer 60; while in some applications only MEMS die 14D and CMOS controller die 16 may be attached to adhesive layer 60.
SOI die 12D includes a first device layer 24, a first dielectric layer 26 over a top surface of first device layer 24, and a first silicon substrate 64 over first dielectric layer 26. Thus, the bottom surface of first device layer 24 is the bottom surface of SOI die 12D and the backside of first silicon substrate 64 is the top surface of SOI die 12D. Herein, SOI die 12D is formed from an SOI structure, which refers to a structure that includes a silicon substrate, a silicon epitaxial layer, and a buried oxide layer sandwiched between the silicon substrate and the silicon epitaxial layer. The first device layer 24 of SOI die 12D is formed by integrating electronic components (not shown) in or on the silicon epitaxial layer of the SOI structure. First dielectric layer 26 of SOI die 12D is the buried oxide layer of the SOI structure. The first silicon substrate 64 of SOI die 12D is the silicon substrate of the SOI structure. SOI die 12D has a thickness between 25 μm and 250 μm or between 10 μm and 750 μm, and first silicon substrate 64 has a thickness between 25 μm and 250 μm or between 10 μm and 750 μm, respectively.
The MEMS die 14D includes a second device layer 30, a second dielectric layer 32 over a top surface of the second device layer 30, and a second silicon substrate 66 over the second dielectric layer 32. Thus, the bottom surface of the second device layer 30 is the bottom surface of the MEMS die 14D, and the backside of the second silicon substrate 66 is the top surface of the MEMS die 14D. The MEMS die 14D has a thickness between 25 μm and 300 μm or between 10 μm and 800 μm, and the second silicon substrate 66 has a thickness between 25 μm and 300 μm or between 10 μm and 800 μm, respectively. In this embodiment, CMOS controller die 16 may be shorter than SOI die 12D and MEMS die 14D. In different applications, CMOS controller die 16 may be the same height as SOI die 12D or MEMS die 14D, or CMOS controller die 16 may be higher than SOI die 12D and MEMS die 14D.
Next, a first mold compound 20 is applied over the adhesive layer 60 to encapsulate the SOI die 12D, MEMS die 14D and the CMOS controller die 16, as shown in fig. 6. The first mold compound 20, which may be an organic epoxy system or similar material, can be used as an etchant barrier to protect the SOI die 12D, MEMS die 14D and the CMOS controller die 16 from etching chemicals such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and Acetylcholine (ACH). The first mold compound 20 may be applied by various procedures such as sheet molding, overmolding, compression molding, transfer molding, dam-fill encapsulation, or screen-print encapsulation. In a typical compression molding, the molding pressure used to apply the first mold compound 20 is between 100psi and 1000 psi. Because SOI die 12D, MEMS die 14D and CMOS controller die 16 are relatively thick and the bottom surfaces of SOI die 12D, MEMS die 14D and CMOS controller die 16 are substantially planar, no vertical deformation of SOI die 12D, MEMS die 14D or CMOS controller die 16 may occur during this molding step.
A curing process (not shown) is then used to harden the first mold compound 20. Depending on the material used as the first mold compound 20, the curing temperature is between 100 ℃ and 320 ℃. The adhesive layer 60 and carrier 62 are then removed to expose the bottom surface of the first device layer 24, the bottom surface of the second device layer 30, and the bottom surface of the third device layer 36, as shown in fig. 7. Removal of the adhesive layer 60 and carrier 62 may be provided by heating the adhesive layer 60.
Referring to fig. 8-12, a multilayer redistribution structure 18 is formed according to one embodiment of the present disclosure. First, a first dielectric pattern 42 is formed under SOI die 12D, MEMS die 14D and CMOS controller die 16, as shown in fig. 8. Thus, the first, second, and third die contacts 28, 34, and 40 are exposed through the first dielectric pattern 42.
Next, redistribution interconnects 44 are formed, as shown in fig. 9. In this context, the redistribution interconnect 44 includes five first redistribution interconnects 44 (1) and one second redistribution interconnect 44 (2). In different applications, the redistribution interconnect 44 may include fewer or more first redistribution interconnect 44 (1)/second redistribution interconnect 44 (2). The first redistribution interconnect 44 (1) is electrically coupled to the first, second, and third die contacts 28, 34, and 40 via the first dielectric pattern 42 and extends under the first dielectric pattern 42. The second redistribution interconnect 44 (2) is used to connect one second die contact 34 to a corresponding third die contact 40 such that a CMOS controller (not shown) within the CMOS controller die 16 electrically connects MEMS components (not shown) within the thinned MEMS die 14. The second redistribution interconnect 44 (2) may also extend under the first dielectric pattern 42. The connections between the redistribution interconnect 44 and the first, second, and third die contacts 28, 34, and 40 are free of solder. If the structural pads 58 are included in the multilayer redistribution structure 18, the structural pads 58 may be formed from a common conductive layer (not shown) at the same time as the redistribution interconnect 44.
A second dielectric pattern 46 is formed under the first dielectric pattern 42 to partially encapsulate each first redistribution interconnect 44 (1), as shown in fig. 10. Thus, a portion of each first redistribution interconnect 44 (1) is exposed through the second dielectric pattern 46. Furthermore, the second dielectric pattern 46 completely encapsulates the second redistribution interconnect 44 (2). Thus, no portion of the second redistribution interconnect 44 (2) is exposed through the second dielectric pattern 46. If the structural pads 58 are included in the multilayer redistribution structure 18, the second dielectric pattern 46 completely encapsulates each of the structural pads 58. Thus, each of the structure pads 58 is not partially exposed through the second dielectric pattern 46.
Conductive layer 68 is then formed as shown in fig. 11. The conductive layer 68 may be formed of at least one of copper, gold, nickel, and palladium, and is electrically coupled to each of the first redistribution interconnects 44 (1). Conductive layer 68 extends under second dielectric pattern 46 and has a planar bottom surface. Finally, package contacts 48 and support pads 52 are formed simultaneously by patterning common conductive layer 68, as shown in fig. 12. In different applications, the package contacts 48 and the support pads 52 may not be formed from a common layer and may be formed sequentially (not shown). In any case, since the bottom surface of each package contact 48 and the bottom surface of each support pad 52 are in the same plane. The support pads 52 are not in contact with any package contacts 48 and are electrically isolated from any package contacts 48.
In this embodiment, each package contact 48 is electrically coupled to a corresponding first redistribution interconnect 44 (1) via a second dielectric pattern 46. Thus, the first redistribution interconnect 44 (1) connects the package contact 48 to a particular die contact of the first, second, and third die contacts 28, 34, and 40. Support pads 52 are formed within the air gaps 50 that surround each package contact 48. However, the support pads 52 are not in contact with any package contacts 48 and are electrically isolated from any package contacts 48.
Herein, the support pad 52 may include a first support pad 52 (1), a second support pad 52 (2), and a third support pad 52 (3). First support pad 52 (1) is placed directly under SOI die 12D. The third support pad 52 (3) is placed directly under the MEMS die 14D. Second support pad 52 (2) is not placed directly under SOI die 12D or directly under MEMS die 14D. The second support pad 52 (2) may be located directly under the first mold compound 20 and/or directly under the CMOS controller die 16. If the first support pad 52 (1) is formed at a first average density, the second support pad 52 (2) is formed at a second average density, and the third support pad 52 (3) is formed at a third average density, the first average density, the second average density, and the third average density may be the same or different. In this embodiment, it is desirable that the second average density is not greater than the first average density or the third average density, and the first average density may be substantially equal to the third average density.
After the formation of the multilayer redistribution structure 18, the first mold compound 20 is thinned to expose the first silicon substrate 64 of the SOI die 12D and the second silicon substrate 66 of the MEMS die 14D, as shown in fig. 13. The thinning process may be performed using a mechanical polishing process. Because CMOS controller die 16 has a lower height than both MEMS die 14D and SOI die 12D, silicon substrate 38 of CMOS controller die 16 is not exposed and is still encapsulated by first mold compound 20.
Next, the first silicon substrate 64 and the second silicon substrate 66 are substantially removed to form a precursor package 70, as shown in fig. 14. Removing first silicon substrate 64 from SOI die 12D provides thinned SOI die 12 and forms first opening 54 within first mold compound 20 and over thinned SOI die 12. Removing the second silicon substrate 66 from the MEMS die 14D provides a thinned MEMS die 14 and forms the second opening 56 within the first mold compound 20 and over the thinned MEMS die 14. In this context, substantially removing the silicon substrate means removing at least 95% of the entire silicon substrate and leaving at most 2 μm of the silicon substrate. Where desired, first and second silicon substrates 62 and 64 are completely removed such that first dielectric layer 26 of thinned SOI die 12 is exposed at the bottom of first opening 54 and second dielectric layer 32 of thinned MEMS die 14 is exposed at the bottom of second opening 56.
The substantial removal of the first and second silicon substrates 62 and 64 may be provided by an etching process utilizing a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, naOH or the like. The first dielectric layer 26 acts as an etch stop layer to protect the first device layer 24 of the thinned SOI die 12 and the second dielectric layer 32 acts as an etch stop layer to protect the second device layer 30 of the thinned MEMS die 14. The first mold compound 20 encapsulates the CMOS controller die 16 and protects the CMOS controller die 16 from wet/dry etchant chemicals. In some applications, a protective layer (not shown) may be placed at the bottom surface of the multilayer redistribution structure 18 to protect the package contacts 48 from the etchant chemistry. The protective layer is applied before the etching process and removed after the etching process. Furthermore, if the silicon substrate 38 of the CMOS controller die 16 is not encapsulated by the first mold compound 20 (in some applications, the CMOS controller die 16 is the same height as the SOI die 12D and the MEMS die 14D, or higher than the SOI die 12D and the MEMS die 14D, the silicon substrate 38 of the CMOS controller die 16 may be exposed during the thinning process), an additional protective layer (not shown) may be placed over the silicon substrate 38 to protect the CMOS controller die 16 from the etchant chemistry. The additional protective layer is applied before the etching process and removed after the etching process.
The precursor package 70 may be attached to the rigid carrier 72 via an adhesive material 74, as shown in fig. 15. Herein, the rigid carrier 72 may be a light transmissive rigid carrier, and is formed of quartz, fused silica, or sapphire. The adhesive material 74 may be a UV sensitive tape or film. The package contacts 48 and the support pads 52 may be in contact with the adhesive material 74. The rigid carrier 72 may help to assist in mechanical support of the precursor package 70. In some applications, the precursor package 70 may not be attached to the rigid carrier 72 due to the following manufacturing steps.
Second mold compound 22 is then applied to substantially fill first and second openings 54 and 56, as shown in fig. 16. In this context, substantially filling the opening refers to filling at least 75% of the entire opening. The second mold compound 22 resides directly over the top surface of the thinned SOI die 12 and the top surface of the thinned MEMS die 14. If no first silicon substrate 64 remains in the first opening 54 and no second silicon substrate 66 remains in the second opening 56, then the second mold compound 22 resides directly over the first dielectric layer 26 and the second dielectric layer 32. In some cases, the second mold compound 22 may also reside over the first mold compound 20.
The second mold compound 22 may be formed from a thermoplastic or thermoset material such as PPS, an overmolded epoxy doped with a boron nitride or aluminum oxide thermal additive, or the like. In some applications, the precursor package 70 may include only the thinned MEMS die 14 and CMOS controller die 16. The second mold compound 22 may also be formed from an organic epoxy resin system having a thermal conductivity of less than 2W/m-K. The second mold compound 22 may be applied by various procedures such as sheet molding, overmolding, compression molding, transfer molding, dam-fill encapsulation, and screen-printing encapsulation. During the molding process of second mold compound 22, the liquefaction and molding pressure may not be uniform across precursor package 70. The first combination of thinned SOI die 12 and the first portion of multilayer redistribution structure 18, and the second combination of thinned MEMS die 14 and the second portion of multilayer redistribution structure 18 may experience greater molding pressures than the other portions of precursor package 70. In typical compression molding, if the second mold compound 22 is formed of a high thermal conductivity material (> = 2W/m·k), the molding pressure and temperature used to coat the second mold compound 22 are between 250psi and 1000psi, and between 100 ℃ and 350 ℃, respectively.
Note that thinned SOI die 12 has a thickness between 0.1 μm and 50 μm, thinned MEMS die 14 has a thickness between 0.5 μm and 100 μm, and multilayer redistribution structure 18 has a thickness between 2 μm and 300 μm. Thus, a first combination of thinned SOI die 12 and a first portion of multilayer redistribution structure 18, or a second combination of thinned MEMS die 14 and a second portion of multilayer redistribution structure 18, may have a thickness as thin as a few μm. If there is no support within the first portion of the air gap 50 directly beneath the thinned SOI die 12, then vertical deformation of the first combination occurs at a higher rate. In this context, since the bottom surface of each package contact 48 and the bottom surface of each support pad 52 are in the same plane, first support pad 52 (1) forms a "standoff" within the first portion of air gap 50 to provide mechanical support for thinned SOI die 12 to withstand high molding pressures. By reducing the distance between adjacent first support pads 52 (1) and/or reducing the distance between first support pads 52 (1) and adjacent package contacts 48, the vertical deformation of the first combination of thinned SOI die 12 and the first portion of multilayer redistribution structure 18 may be reduced to an acceptable level.
Similarly, if there is no support within a second portion of the air gap 50 located directly below the thinned MEMS die 14, vertical deformation of the second combination may occur at a higher rate. In this context, since the bottom surface of each package contact 48 and the bottom surface of each support pad 52 are in the same plane, the third support pad 52 (3) forms a "standoff" within the second portion of the air gap 50 to provide mechanical support for the thinned MEMS die 14 to withstand high molding pressures. By reducing the distance between adjacent third support pads 52 (3) and/or reducing the distance between third support pads 52 (3) and adjacent package contacts 48, the vertical deformation of the second combination of thinned MEMS die 14 and the second portion of the multilayer redistribution structure 18 may be reduced to an acceptable level.
Further, the second support pad 52 (2) provides mechanical support for the CMOS controller die 16 and/or the first mold compound 20. The first support pad 52 (1), the second support pad 52 (2), and the third support pad 52 (3) enhance the rigidity of the entire wafer level package 10.
A curing process (not shown) is then performed to harden the second mold compound 22. Depending on the material used as the second mold compound 22, the curing temperature is between 100 ℃ and 320 ℃. The top surface of second mold compound 22 is then planarized to form wafer level package 10, as shown in fig. 17. If the second mold compound 22 does not cover the top surface of the first mold compound 20, the top surface of the second mold compound 22 and/or the first mold compound 20 is planarized to be coplanar (not shown). A mechanical polishing process may be used for planarization.
Finally, the rigid carrier 72 is detached from the wafer level package 10, as shown in fig. 18. If the rigid carrier 72 is a light transmissive rigid carrier and the adhesive material 74 is a UV sensitive film or tape, the rigid carrier 72 is exposed to a UV environment to effect the detachment process. The wafer level package 10 may be marked, diced, and singulated into individual components (not shown).
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (22)

1. A wafer level package, the wafer level package comprising:
a first thinned die comprising a first device layer and a first dielectric layer over the first device layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
a multilayer redistribution structure comprising at least one first support pad, a plurality of package contacts and a redistribution interconnect, wherein:
the first thinned die resides over a top surface of the multilayer redistribution structure;
The at least one first support pad is on the bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die such that the at least one first support pad is placed directly under the first thinned die;
-the plurality of package contacts are on the bottom surface of the multilayer redistribution structure; and is also provided with
The redistribution interconnect connects the plurality of package contacts to a particular first die contact of the plurality of first die contacts, wherein the at least one first support pad is not in contact with the plurality of package contacts and the redistribution interconnect and is electrically isolated from the plurality of package contacts, the redistribution interconnect, and the plurality of first die contacts;
a first mold compound residing over the multilayer redistribution structure and surrounding the first thinned die and extending beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die, wherein the top surface of the first thinned die is exposed at a bottom of the opening; and
a second mold compound filling the opening and in contact with the top surface of the first thinned die.
2. The wafer level package of claim 1, wherein the plurality of package contacts and the at least one first support pad are formed from a common conductive layer.
3. The wafer level package of claim 1, wherein a bottom surface of the at least one first support pad and a bottom surface of each of the plurality of package contacts are in a same plane.
4. The wafer level package of claim 1, further comprising at least one second support pad on the bottom surface of the multilayer redistribution structure and not placed directly under the first thinned die, wherein the at least one second support pad is electrically isolated from the plurality of package contacts and the redistribution interconnect.
5. The wafer level package of claim 4, wherein the at least one first support pad and the at least one second support pad are separate.
6. The wafer level package of claim 4, wherein the at least one first support pad and the at least one second support pad are connected together.
7. The wafer level package of claim 1, wherein the first thinned die provides a microelectromechanical system (MEMS) component.
8. The wafer level package of claim 1, wherein the first thinned die is formed of a silicon-on-insulator (SOI) structure, wherein the first device layer of the first thinned die is formed of a silicon epitaxial layer of the SOI structure, and the first dielectric layer of the first thinned die is a buried oxide layer of the SOI structure.
9. The wafer level package of claim 1, further comprising a second complete die residing above the top surface of the multilayer redistribution structure, wherein:
the second complete die has a second device layer and a complete silicon substrate over the second device layer; and is also provided with
The first mold compound encapsulates the second complete die.
10. The wafer level package of claim 9, wherein the first thinned die provides a MEMS component and the second complete die provides a Complementary Metal Oxide Semiconductor (CMOS) controller that controls the MEMS component.
11. The wafer level package of claim 9, further comprising a third thinned die residing over the top surface of the multilayer redistribution structure, wherein:
The third thinned die has a third device layer and a second dielectric layer over the third device layer;
the first mold compound extending beyond a top surface of the third thinned die to define a second opening within the first mold compound and above the third thinned die, wherein the top surface of the third thinned die is exposed at a bottom of the second opening; and is also provided with
The second mold compound fills the second opening and contacts the top surface of the third thinned die.
12. The wafer level package of claim 11, further comprising at least one second support pad and at least one third support pad, wherein:
-the at least one second support pad and the at least one third support pad are on the bottom surface of the multilayer redistribution structure;
the at least one second support pad and the at least one third support pad are electrically isolated from the plurality of package contacts and the redistribution interconnect;
the at least one second support pad is not placed directly under the first thinned die and is not placed directly under the third thinned die; and is also provided with
The at least one third support pad is aligned vertically with the third thinned die such that the at least one third support pad is placed directly under the third thinned die.
13. The wafer level package of claim 11, wherein the first thinned die provides a MEMS component, the second complete die provides a CMOS controller that controls the MEMS component, and the third thinned die is formed from an SOI structure, wherein the third device layer of the third thinned die is formed from a silicon epitaxial layer of the SOI structure, and the second dielectric layer of the third thinned die is a buried oxide layer of the SOI structure.
14. The wafer level package of claim 1, wherein the multilayer redistribution structure further comprises at least one structural pad, wherein:
-the at least one structural pad and the redistribution interconnect are formed from a common conductive layer; and is also provided with
The at least one structural pad is located directly under the first thinned die and is electrically isolated from the redistribution interconnect and the plurality of first die contacts.
15. The wafer level package of claim 1, wherein the second mold compound has a thermal conductivity greater than 2W/m-K.
16. The wafer level package of claim 1, wherein the second mold compound has a resistivity greater than 1E6 ohm-cm.
17. The wafer level package of claim 1, wherein the first mold compound and the second mold compound are formed of the same material.
18. The wafer level package of claim 1, wherein the first mold compound and the second mold compound are formed of different materials.
19. The wafer level package of claim 1, wherein the multilayer redistribution structure is free of glass fibers.
20. The wafer level package of claim 1, wherein the connections between the redistribution interconnect and the plurality of first die contacts are free of solder.
21. A wafer level package, the wafer level package comprising:
a first thinned die comprising a first device layer and a first dielectric layer over the first device layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
a multilayer redistribution structure comprising at least one structure pad, a plurality of package contacts, and a redistribution interconnect, wherein:
The first thinned die resides over a top surface of the multilayer redistribution structure;
-the plurality of package contacts are on a bottom surface of the multilayer redistribution structure;
the redistribution interconnect connects the plurality of package contacts to a particular first die contact of the plurality of first die contacts;
-the at least one structural pad and the redistribution interconnect are formed from a common conductive layer; and is also provided with
The at least one structural pad is located directly under the first thinned die and is electrically isolated from the redistribution interconnect and the plurality of first die contacts;
a first mold compound residing over the multilayer redistribution structure and surrounding the first thinned die and extending beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die, wherein the top surface of the first thinned die is exposed at a bottom of the opening; and
a second mold compound filling the opening and in contact with the top surface of the first thinned die.
22. A method of manufacturing a wafer level package, the method comprising:
providing a die wafer having a first die and a first die compound, wherein:
the first die comprising a first device layer, a first dielectric layer over the first device layer, and a first silicon substrate over the first dielectric layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
the top surface of the first die is a top surface of the first silicon substrate and the bottom surface of the first die is the bottom surface of the first device layer; and is also provided with
The first mold compound encapsulates sides and the top surface of the first die, wherein the bottom surface of the first device layer is exposed;
forming a multilayer redistribution structure under the die wafer, wherein:
the multilayer redistribution structure comprises at least one first support pad, a plurality of package contacts and a redistribution interconnect;
the at least one first support pad is on the bottom surface of the multilayer redistribution structure and vertically aligned with the first die such that the at least one first support pad is placed directly under the first die;
-the plurality of package contacts are on the bottom surface of the multilayer redistribution structure; and is also provided with
The redistribution interconnect connects the plurality of package contacts to a particular first die contact of the plurality of first die contacts, wherein the at least one first support pad is not in contact with the plurality of package contacts and the redistribution interconnect and is electrically isolated from the plurality of package contacts, the redistribution interconnect, and the plurality of first die contacts;
thinning the first mold compound to expose the top surface of the first silicon substrate;
substantially removing the first silicon substrate of the first die to provide a first thinned die and an opening formed within the first mold compound and over the first thinned die, wherein the at least one first support pad is located directly under the first thinned die and the first thinned die has a top surface exposed at a bottom of the opening; and
a second mold compound is applied to substantially fill the opening and directly contact the top surface of the first thinned die.
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