CN105655311A - Wafer-level chip package backside interconnection structure and manufacturing method thereof - Google Patents
Wafer-level chip package backside interconnection structure and manufacturing method thereof Download PDFInfo
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- CN105655311A CN105655311A CN201610003461.3A CN201610003461A CN105655311A CN 105655311 A CN105655311 A CN 105655311A CN 201610003461 A CN201610003461 A CN 201610003461A CN 105655311 A CN105655311 A CN 105655311A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The invention provides a wafer-level chip package backside interconnection structure and a manufacturing method thereof and belongs to the field of semiconductor packaging. The packaging method comprises the steps of 1, providing a wafer with a functional region, a bonding pad and a dielectric layer; 2, providing a cover plate, and bonding the cover plate with the wafer together by means of the bonding glue; 3, conducting the silicon etching operation on the lower surface of the substrate of the wafer, and removing the silicon material in scribe lines on the lower surface of the substrate of the wafer and the silicon material on the bonding pad to form a first groove body and a second groove body; 4, manufacturing a redistribution layer on the lower surface of the substrate of the wafer; 5, cutting the wafer along the scribe lines to form the package of the single chip. According to the technical scheme of the invention, the challenge of multiple materials on the cutting process is reduced, and the yield of the cutting process is improved. Meanwhile, the packaging reliability is improved. Moreover, the stress applied onto the periphery of the bonding pad is released, so that the stress generated due to the thermal mismatch of different materials is reduced. Therefore, the stratifying, cracking and other invalid phenomena at the interfaces of different materials are alleviated.
Description
Technical field
The present invention relates to wafer stage chip encapsulation field, particularly relate to and the encapsulation of a kind of wafer stage chip forms the opening exposing pad to realize structure of back side interconnection and preparation method thereof.
Background technology
The general structure of wafer includes several chip units, each chip unit includes substrate and is positioned at the dielectric layer in front of described substrate, and the front of substrate is provided with element region, and described element region periphery is provided with some pads, and pad is positioned at dielectric layer, the pad of element region and its periphery is electrical connected; In this structure, dielectric material between pad and substrate, is had to be separated by. At present, the back side interconnection step of wafer stage chip includes, the back side of wafer substrate is done opening, this opening extends to the front of wafer from the back side of wafer, and expose the pad in front, metallic circuit is laid, by the back side electrically guiding to wafer of pad, it is achieved the back interconnection of wafer stage chip at opening inwall.
The opening at the wafer substrate back side exposes in the step of pad, it is necessary to remove the barrier material on pad, such as silicon, dielectric layer, insulating barrier or aforesaid combined material. The barrier material removed on pad generally adopts lithographic method, expose pad and generally adopt laser boring or mechanical cutting method, but when using laser boring or machine cuts to form the opening running through pad, structural stress is bigger, structural strength between pad and metallic circuit is more weak, easily cause storeroom lamination, reduce reliability. And machine cuts, different Cutting Roads needs different cutter couplings, limits the range of application of the method.
Summary of the invention
The invention provides a kind of wafer scale and expose bonding pad opening semiconductor package forming back side interconnection and preparation method thereof, the silicon in Cutting Road 105 region on wafer 100 is removed, forms the second cell body 106, and make metal level 402 not cover Cutting Road 100; Remove the material on wafer 100 pad, form the first cell body 104 connected with the second cell body 106, pad 102 can be made to come out, and without material block between adjacent pad, reduce the stress level in encapsulating structure, improve the reliability of encapsulation and the yield of wafer cutting technique, increase the exposed area of pad simultaneously, improve the conductance general character.
In order to realize object above, the present invention by the following technical solutions:
Wafer stage chip backside interconnection structure of the invention process, described structure includes:
A kind of wafer stage chip encapsulating structure, including a wafer, described wafer has the functional surfaces of a silicon base and upper surface thereof, described functional surfaces has some chip units, and described chip unit comprises functional areas and some pads of functional areas surrounding, it is characterized in that, between adjacent chips unit, etching forms the second cell body extended by substrate lower surface and the first cell body of exposure chip unit each limit adjacent pad, described first cell body and the connection of the second cell body to functional surfaces.
Optionally, described first cell body can expose a part for each pad, or all.
Optionally, being formed with a groove between adjacent chips unit, described first cell body and the second cell body are located at described channel bottom.
Optionally, the functional surfaces of wafer is also bonded with the combination of cover plate or cover plate and knee wall.
Optionally, being equipped with rewiring metal on the upside of the inwall of at least the first cell body, described rewiring metal at least extends to substrate lower surface from pad.
The method of back side interconnection in the encapsulation of a kind of wafer stage chip, it is characterised in that comprise the following steps:
Step 1 a, it is provided that wafer 100, described wafer has a substrate and the functional surfaces of upper surface 100a thereof, and described functional surfaces has some chip units, and described chip unit comprises functional areas 101 and at least one pad 102 of functional areas surrounding;
Step 2 a, it is provided that cover plate 300, utilizes bonding glue to be bonded together with wafer 100 by described cover plate 300;
Step 3, carries out silicon etching to wafer substrate lower surface 100b, will belong to the silicon in Cutting Road 105 region on substrate lower surface 100b, and the silicon on pad 102 is removed in the lump, forms the first cell body 104 and the second cell body 106 respectively;
Step 4, makes redistribution layer, makes redistribution layer at wafer substrate lower surface 100b, and pad 102 is electrically conducting to the position of default soldered ball 404 by the first cell body 104;
Step 5, carries out being cut to the encapsulation of single chips along wafer 100 Cutting Road 105.
Optionally, in described step 2, before wafer bonding, make knee wall 200 to be bonded of cover plate 300, make the wafer functional areas 101 after bonding be placed in the cavity that described knee wall 200 is formed.
Optionally, described silicon etching is to adopt dry etch process, or wet-etching technology.
Optionally, before carrying out step 3, first adopting precut to remove Cutting Road region part silicon, the method then carrying out silicon etching forms the first cell body 104 and the second cell body 106.
Optionally, the redistribution layer structure of described wafer second surface 100b includes passivation layer 401, reroutes metal level 402 and welding resisting layer 403.
Optionally, described rewiring metal level 402 is not covered with Cutting Road 105 region.
Compared with prior art, the invention has the beneficial effects as follows:
Enforcement by patent of the present invention:
1. by the silicon in Cutting Road 105 region on wafer 100 is removed, form the second cell body 106, and make metal level 402 not cover Cutting Road 100, thus reducing the challenge that cutting technique is caused by many materials, improve the yield of cutting technique, and improve the reliability of encapsulation.
2. by the silicon in the first cell body 104 region on wafer 100 is removed, pad 102 can be made to come out, and owing to the silicon in pad 102 region is removed, and connect with the second cell body 106, stress herein is made to obtain very big release, thus reducing the stress owing to different materials thermal mismatching produces, improving the layering of different materials interface, crackle etc. and losing efficacy.
The example embodiment cited below particularly of the present invention, and coordinate accompanying drawing that features described above and the advantage of the present invention are elaborated.
Accompanying drawing explanation
Fig. 1 is to the schematic diagram that 9 is that the method according to the invention flow process arranges from front to back in order.
Number in the figure:
100. wafer
100a. upper surface of substrate
100b. substrate lower surface
101. functional areas
102. pad
103. dielectric layer
104. the first cell body
105. Cutting Road
106. the second cell body
200. knee wall
300. cover plate
401. passivation layer
402. metal level
403. welding resisting layer
404. soldered ball
Detailed description of the invention
More understandable for enabling the invention to, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail. For convenience of description, in the structure of embodiment accompanying drawing, each ingredient does not press normal rates convergent-divergent, therefore does not represent the actual relative size of each structure in embodiment. Wherein described structure or the above or upside in face, comprise the middle situation also having other layers.
Wafer stage chip backside interconnection structure of the invention process, described structure includes:
Wafer 100; Wafer substrate upper surface 100a, and making has functional areas 101 and pad 102 on its surface, pad 102 is wrapped in dielectric layer 103; Wafer substrate lower surface 100b; Wafer substrate lower surface 100b is formed the first cell body 104 and the second cell body 106, makes the pad 102 of wafer first surface 100a be come out by the first cell body 104; Then making successively and have passivation layer 401, metal level 402, welding resisting layer 403, soldered ball 404, by the redistribution layer that said structure forms, pad 102 and the soldered ball 404 being positioned at wafer second surface 100b realize interconnection the most at last.
Optionally, the first cell body can expose a part for each pad, it is also possible to exposes the whole of each pad.
Optionally, between the chip unit that one functional areas and peripheral weld dish thereof are formed, may also be formed with a groove, first cell body 104 and the second cell body 106 are located at this channel bottom, reduce the stress level in encapsulating structure, improve the reliability of encapsulation and the yield of wafer cutting technique, increase the exposed area of pad simultaneously, improve the conductance general character.
Optionally, the functional surfaces of wafer is also bonded with cover plate, to support wafer, strengthens the intensity of wafer; Or it is bonded with the combination of cover plate and knee wall, not contaminated with functional section.
The manufacturing process of the wafer stage chip back side interconnection of the present embodiment is described in detail below in conjunction with figure (1) to (9).
Step 1, it is provided that wafer 100:
Refer to figure (1), it is provided that wafer 100, described wafer makes on 100 functional areas 101, pad 102, dielectric layer 103.
Step 2, is bonded cover plate 300:
One cover plate 300 is provided, utilizes bonding glue by cover plate 300 together with wafer bonding.
In the present embodiment, described cover plate 300 can be the transparent materials such as glass, quartz, plastic cement, it is also possible to for materials such as silicon, pottery, metals.
Refer to figure (2), in the present embodiment, before wafer bonding, make knee wall 200 to be bonded of cover plate 300, make the wafer functional areas 101 after bonding be placed in the cavity that described knee wall 200 is formed, described cavity can be circular or square. Cavity can functional section not contaminated or scratch.
Refer to figure (3), described cover plate 300 utilizes bonding glue to be bonded with knee wall 200, and described support enclosure wall 200 is bonded glue with upper surface of substrate 100a utilization and is bonded, and described bonding glue can be a kind of resinae adhesive glue.
In other embodiments, can being not provided with knee wall 200, cover plate plays a supportive role in encapsulation procedure, strengthens the intensity of wafer, and the bonding glue being bonded cover plate and wafer in this embodiment can be ephemeral key rubber alloy.
Optionally, after wafer bonding, wafer substrate lower surface 100b is carried out thinning:
Refer to profile (4) and plane graph (5), wafer 100 is thinning, by grinder, wafer substrate lower surface 100b is ground, it is thinned to setting thickness, and after thinning, wafer substrate lower surface 100b is carried out destressing plasma etching.
In the present embodiment, the thickness of wafer 100 is thinned to 130 microns from 600��700 microns started most; Destressing plasma etching is to remove in wafer 100 owing to grinding the internal stress produced, improving the warpage of wafer 100, it is simple to subsequent technique carries out.
Step 3, silicon etching:
Refer to profile (6) and plane graph (7), wafer substrate lower surface 100b is carried out silicon etching, wafer substrate lower surface 100b will belong to the silicon in Cutting Road 105 region, form the second cell body 106, and the silicon on pad 102 is removed, form the first cell body 104.
In the present embodiment, described silicon etching is the dry etch process adopting plasma etching, including deep reaction ion etching (DRIE), it is possible to adopt wet etching.
In the present embodiment, described second cell body 106 is possible with cutting technique formation.
Lithographic method forms the first cell body, expose whole pad and the interval without silicon materials between adjacent pad, can effectively discharge the stress near pad, thus reducing the stress owing to different materials thermal mismatching produces, improving the layering of different materials interface, crackle etc. and losing efficacy.
Step 4, redistribution layer:
Refer to figure (8), described redistribution layer includes passivation layer 401, metal level 402 and welding resisting layer 403. First it is coated with one layer of passivation layer 401 at first cell body the 104, second cell body 106 and wafer substrate lower surface 100b; Next utilizes the mode of exposure imaging or laser ablation to be removed by the passivation layer 401 on pad 103, thus exposing pad 103; Then pass through sputtering or electroplating technology and make layer of metal layer 402 on passivation layer 401 surface, and it is patterned, will be located in the metal level 402 in Cutting Road 105 region simultaneously and be removed; Finally it is coated one layer of welding resisting layer 403 on metal level 402 surface, and exposes in the position of reserved soldered ball 404.
Preferably, the thickness of outermost welding resisting layer 403 is less than 1.5 times of passivation layer 401 thickness
In the present embodiment, described passivation layer 401 and welding resisting layer can be light-sensitive materials, it is also possible to be oxide (such as silicon dioxide), or nitride (such as silicon nitride). By being patterned by described metal level 402, thus pad 103 being conducting to the position of reserved soldered ball 404, and form soldered ball 404 in this position.
Step 5, cutting:
Refer to figure (9), wafer 103 is cut to along Cutting Road 100 encapsulation of single chips.
Above example is with reference to accompanying drawing; to a preferred embodiment of the present invention will be described in detail; those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, but when without departing substantially from the essence of the present invention, all drops within protection scope of the present invention.
Claims (9)
1. wafer stage chip encapsulation backside interconnection structure, including a wafer (100), described wafer has the functional surfaces of a silicon base and upper surface thereof, described functional surfaces has some chip units, described chip unit comprises functional areas (101), and some pads (102) of functional areas surrounding, functional areas are electrically connected by dielectric layer (103) with pad, it is characterized in that, expose first cell body (104) of chip unit each limit adjacent pad, and etching forms the second cell body (106) extended by substrate lower surface to functional surfaces between adjacent chips unit, described first cell body and the connection of the second cell body,Being equipped with rewiring metal on the upside of the inwall of the first cell body, described rewiring metal at least extends to substrate lower surface from pad.
2. structure according to claim 1, it is characterised in that described first cell body exposes a part for each pad, or all.
3. structure according to claim 1, it is characterised in that being formed with a groove between adjacent chips unit, described first cell body and the second cell body are located at described channel bottom.
4. structure according to claim 1, it is characterised in that be also bonded with cover plate (300) or cover plate and the combination of knee wall (200) on the functional surfaces of wafer.
5. preparation method of a kind of wafer stage chip encapsulation backside interconnection structure as described in claim 1-4 any one, it is characterised in that comprise the following steps:
Step 1, one wafer (100) is provided, described wafer has silicon base and the functional surfaces of silicon base upper surface (100a), described functional surfaces has some chip units, described chip unit comprises functional areas (101) and at least one pad (102) of functional areas surrounding;
Step 2 a, it is provided that cover plate (300), utilizes bonding glue described cover plate (300) and wafer 100 to be bonded together;
Step 3, wafer substrate lower surface (100b) is carried out silicon etching, substrate lower surface (100b) will belong to the silicon in Cutting Road (105) region, and the silicon on pad (102) removes in the lump, form the first cell body (104) and the second cell body (106) respectively;
Step 4, makes redistribution layer, makes redistribution layer at wafer substrate lower surface (100b), and pad (102) is electrically conducting to the position of default soldered ball (404) by the second cell body (106);
Step 5, carries out being cut to the encapsulation of single chips along wafer (103) Cutting Road (105).
6. method according to claim 5, it is characterized in that, in described step 2, before wafer bonding, make knee wall (200) to be bonded of cover plate (300), make the wafer functional areas (101) after bonding be positioned at the cavity central authorities that described knee wall (200) is formed.
7. method according to claim 5, it is characterised in that described silicon etching is to adopt dry etch process, or wet-etching technology.
8. method according to claim 5, it is characterised in that the redistribution layer structure of described wafer second surface (100b) includes passivation layer (401), reroutes metal level (402) and welding resisting layer (403).
9. method according to claim 5, it is characterised in that described rewiring metal level (402) is not covered with Cutting Road (105) region.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610003461.3A CN105655311A (en) | 2016-01-02 | 2016-01-02 | Wafer-level chip package backside interconnection structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610003461.3A CN105655311A (en) | 2016-01-02 | 2016-01-02 | Wafer-level chip package backside interconnection structure and manufacturing method thereof |
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| CN105655311A true CN105655311A (en) | 2016-06-08 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110494964A (en) * | 2017-04-07 | 2019-11-22 | 微芯片技术股份有限公司 | Semiconductor package part and relevant packaging and testing method with exposed redistribution layer feature |
| CN113097168A (en) * | 2021-03-26 | 2021-07-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
| CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路（宁波）有限公司 | Manufacturing method of packaging structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110494964A (en) * | 2017-04-07 | 2019-11-22 | 微芯片技术股份有限公司 | Semiconductor package part and relevant packaging and testing method with exposed redistribution layer feature |
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| CN110494964B (en) * | 2017-04-07 | 2023-10-31 | 微芯片技术股份有限公司 | Semiconductor packages with exposed redistribution layer features and related packaging and testing methods |
| CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路（宁波）有限公司 | Manufacturing method of packaging structure |
| CN113097168A (en) * | 2021-03-26 | 2021-07-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
| WO2022198785A1 (en) * | 2021-03-26 | 2022-09-29 | 武汉新芯集成电路制造有限公司 | Semiconductor apparatus and method for forming same |
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