CN201994303U - Through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure - Google Patents
Through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure Download PDFInfo
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- CN201994303U CN201994303U CN 201120033891 CN201120033891U CN201994303U CN 201994303 U CN201994303 U CN 201994303U CN 201120033891 CN201120033891 CN 201120033891 CN 201120033891 U CN201120033891 U CN 201120033891U CN 201994303 U CN201994303 U CN 201994303U
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- chip
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- line layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model relates to a through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure, which comprises a chip body (1-1), wherein the front of the chip body is provided with a chip source electrode (2-1) and a chip gate electrode (2-2), the front surfaces of the chip body, the chip source electrode and the chip gate electrode are provided with a chip surface protection layer (3), a through hole (1-2) penetrates through the front and the back of the chip body (1-1), the surfaces of the chip source electrode (2-1), the chip gate electrode (2-2) and the chip surface protection layer (3) are provided with a line layer (4), the line layer (4) is filled in a chip through hole (1-2), a sealed chip through hole (1-2) is not arranged at the line layer (4) filled in chip through hole (1-2), instead, a half-filling structure with a hollow cavity is reserved on the line layer (4) filled in the chip through hole (1-2), and the back surface (1-3) of the chip body (1-1) is provided with a back surface metal layer (7) which is interconnected with the line layer (4). The utility model provides the packaging structure with high property and high reliability.
Description
Technical field
The utility model relates to a kind of disc grade chip size encapsulating structure.Belong to the semiconductor packaging field.
Background technology
The MOSFET(metal oxide semiconductor field effect tube) be to utilize field effect to control semi-conductive field-effect transistor.Because MOSFET has the characteristic that can realize low power consumption voltage control, receives increasing concern in recent years.The MOSFET performance particularly quality of current carrying capacity depends on heat dispersion to a great extent, and the quality of heat dispersion depends primarily on packing forms again.Yet conventional MOS FET encapsulation mainly is forms such as TO, SOT, SOP, QFN, QFP, and this class encapsulation all is that chip is wrapped in the plastic-sealed body, and the heat that produces in the time of can't be with chip operation is in time led away or left, and has restricted the MSOFET performance boost.And plastic packaging itself increased device size, do not meet the requirement that semiconductor develops to light, thin, short, little direction.With regard to packaging technology, this class encapsulation all is based on single chips to be carried out, and has the problem that production efficiency is low, packaging cost is high.
Disc grade chip size encapsulation (Wafer Level Chip Scale Packaging) is a kind of novel encapsulated technology, and encapsulation back chip is a bare chip, and size is equal to chip size fully, and is based on the batch encapsulation that whole wafer carries out.If the disc grade chip size encapsulation technology can be incorporated into the MOSFET field, not only can promote the MOSFET performance, dwindle package dimension, and can enhance productivity, reduce packaging cost.
Source electrode of MOSFET chip (Source) and grid (Gate) are positioned at chip front side, need the drain electrode (Drain) of metal level as chip be set at chip back or inside.But realize the disc grade chip size encapsulation, also need chip front side is guided in the metal level drain electrode that is provided with, form homonymy with source electrode and grid and distribute.Can play the effect that forms the chip drain electrode and drain electrode is guided to the front by filling full metal in the silicon through hole, but because thermal coefficient of expansion (CTE) does not match between metal and the silicon, metal overinflation in the device use and cause silicon cracking causes that device reliability reduces.
Summary of the invention
The purpose of this utility model is to overcome the deficiency of conventional MOS FET encapsulating structure, and a kind of interconnected type wafer level of through hole MOSFET encapsulating structure with high-performance and high reliability is provided.
The purpose of this utility model is achieved in that the interconnected type wafer level of a kind of through hole MOSFET encapsulating structure; comprise the chip body; described chip body front is provided with chip source electrode and chip gate electrode; the chip body; chip source electrode and chip gate electrode front are provided with the chip surface protective layer; be penetrated with the chip through hole at chip body front and back; at described chip source electrode; the surface of chip gate electrode and chip surface protective layer is provided with line layer; and in the chip through hole, be filled with line layer; and the line layer of filling in the chip through hole does not have airtight chip through hole; but leave half interstitital texture of cavity; and line layer directly links to each other with the chip through-hole side wall; between no any dielectric isolation layer; be provided with the circuit sealer at the circuit laminar surface; line layer surface in chip body front is provided with soldered ball; the back side at the chip body is provided with metal layer on back, and metal layer on back and line layer are interconnected.
The beneficial effects of the utility model are:
(1) the utility model by form and line layer that through-hole wall directly links to each other and chip back metal layer as the drain electrode of chip, obtained bigger drain area, promoted the current carrying capacity of chip; The chip back metal layer plays the fin effect, the radiating effect when having improved chip operation; And the hole layer within the circuit is guided to chip front side with formed drain electrode, thereby has realized being undertaken by the soldered ball and the external world in chip front side interconnected, and this structure has shortened chip and extraneous interconnected distance, has also strengthened chip conduction, heat-conducting effect.
(2) owing to just partly fill metal in the through hole, metal can expand towards hole internal cavity direction when being heated; Compare with full packing metal in the hole, can alleviate the stress that thermal coefficient of expansion does not match and produces greatly, improve product reliability.
(3) than conventional MOS FET encapsulation, the encapsulating structure that the utility model proposes is based on that whole wafer carries out, rather than carries out based on single; So have production efficiency height, characteristics that packaging cost is low.
Description of drawings
Fig. 1 is the tangent plane schematic diagram of the interconnected type wafer level of the utility model through hole MOSFET encapsulating structure.
Fig. 2, Fig. 3, Fig. 4 and Fig. 5 are respectively the tangent plane schematic diagram of several detailed structure of interconnect portion A among Fig. 1.
Fig. 6 becomes single packaged chip schematic diagram for the wafer cutting and separating.
Fig. 7 respectively has under the exhausting hole situation for B place adjacent chips among Fig. 6, and cutting position is schematic diagram between through hole.Mode by Fig. 7 obtains interconnect architecture shown in Fig. 2, Fig. 3 tangent plane schematic diagram.
Fig. 8 is for only having under the exhausting hole situation between B place adjacent chips among Fig. 6, and cutting position is positioned at the through hole schematic diagram.Mode by Fig. 8 obtains interconnect architecture shown in Fig. 4, Fig. 5 tangent plane schematic diagram.
Among the figure:
In chip body 1-1, chip through hole 1-2, chip source (source) electrode 2-1, chip grid (gate) electrode 2-2, chip surface protective layer 3, line layer 4, circuit sealer 5, soldered ball 6, metal layer on back 7, back side 1-3, the through hole owing to just partly filling cavity 5-1, chip 8, the cutting position C that metal forms.
Embodiment
Referring to Fig. 1, Fig. 1 is the tangent plane schematic diagram of the interconnected type wafer level of the utility model through hole MOSFET encapsulating structure.As seen from Figure 1, the interconnected type wafer level of the utility model through hole MOSFET encapsulating structure, comprise chip body 1-1, chip through hole 1-2, chip source electrode 2-1, chip gate electrode 2-2, chip surface protective layer 3, line layer 4, circuit sealer 5, soldered ball 6 and metal layer on back 7, described chip source electrode 2-1 and chip gate electrode 2-2 are arranged at chip body 1-1 front, chip surface protective layer 3 is arranged at chip body 1-1, chip source electrode 2-1 and chip gate electrode 2-2 front, described chip through hole 1-2 runs through chip body 1-1 front and back, line layer 4 is arranged at described chip source electrode 2-1, chip gate electrode 2-2 and chip surface protective layer 3 the surface and be filled in the chip through hole 1-2, and the line layer 4 of filling in chip through hole 1-2 does not have airtight chip through hole 1-2, but leaves half interstitital texture of cavity; And line layer 4 directly links to each other with chip through hole 1-2 sidewall, between no any dielectric isolation layer.Circuit sealer 5 is arranged at line layer 4 surfaces, and soldered ball 6 is arranged at line layer 4 surfaces in chip body 1-1 front, and the back side 1-3 of chip body 1-1 is provided with metal layer on back 7, and metal layer on back 7 is interconnected with line layer 4.
Fig. 2, Fig. 3, Fig. 4 and Fig. 5 are respectively the tangent plane schematic diagram of several detailed structure of interconnect portion A among Fig. 1.Wherein, Fig. 2 feature is that chip through hole 1-2 is that full hole and circuit sealer 5 do not contact with metal layer on back; Fig. 3 feature is that through hole is that full hole and circuit sealer 5 contact with metal layer on back; Fig. 4 feature is that through hole is half hole, and circuit sealer 5 does not contact with metal layer on back; Fig. 5 feature is that through hole is half hole, and circuit sealer 5 contacts with metal layer on back.
The starting point of encapsulation process is the wafer that has chip source electrode 2-1, chip gate electrode 2-2 and chip surface protective layer 3, the MOSFET chip after obtaining encapsulating by following process:
1), by photoetching, silicon etching and photoresist stripping process, form through hole;
2), by photoetching, sputter, plating, photoresist lift off and metal etch process, formation line layer;
3), form the circuit sealer by photoetching process;
4), pass through attenuate, metal depositing technics such as sputter, evaporation or plated film, formation metal layer on back;
5), by printing solder or electroplate scolder or plant the method for putting soldered ball, refluxing then and form soldered ball;
6), the method by the wafer cutting and separating forms single MSOFET packaged chip, referring to Fig. 6.Fig. 7 respectively has under the exhausting hole situation cutting position C schematic diagram between through hole for B place adjacent chips 8 among Fig. 6.Mode by Fig. 7 obtains interconnect architecture shown in Fig. 2, Fig. 3 tangent plane schematic diagram.
Fig. 8 only has under the exhausting hole situation for 8 of B place adjacent chips among Fig. 6, and cutting position C is positioned at the through hole schematic diagram.Mode by Fig. 8 obtains interconnect architecture shown in Fig. 4, Fig. 5 tangent plane schematic diagram.
Claims (5)
1. the interconnected type wafer level of through hole MOSFET encapsulating structure; comprise chip body (1-1); it is characterized in that: described chip body (1-1) front is provided with chip source electrode (2-1) and chip gate electrode (2-2); chip body (1-1); chip source electrode (2-1) and chip gate electrode (2-2) front are provided with chip surface protective layer (3); be penetrated with chip through hole (1-2) at chip body (1-1) front and back; at described chip source electrode (2-1); the surface of chip gate electrode (2-2) and chip surface protective layer (3) is provided with line layer (4); and in chip through hole (1-2), be filled with line layer (4); and the line layer (4) of filling in chip through hole (1-2) does not have airtight chip through hole (1-2); but leave half interstitital texture of cavity; and line layer (4) directly links to each other with chip through hole (1-2) sidewall; between no any dielectric isolation layer; be provided with circuit sealer (5) on line layer (4) surface; line layer (4) surface positive at chip body (1-1) is provided with soldered ball (6); be provided with metal layer on back (7) at the back side of chip body (1-1) (1-3), and metal layer on back (7) is interconnected with line layer (4).
2. the interconnected type wafer level of a kind of through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is full hole, and circuit sealer (5) does not contact with metal layer on back (7).
3. the interconnected type wafer level of a kind of through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is full hole, and circuit sealer (5) contacts with metal layer on back (7).
4. the interconnected type wafer level of a kind of through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is half hole, and circuit sealer (5) does not contact with metal layer on back (7).
5. the interconnected type wafer level of a kind of through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is half hole, and circuit sealer (5) contacts with metal layer on back (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120033891 CN201994303U (en) | 2011-01-31 | 2011-01-31 | Through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120033891 CN201994303U (en) | 2011-01-31 | 2011-01-31 | Through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure |
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| Publication Number | Publication Date |
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| CN201994303U true CN201994303U (en) | 2011-09-28 |
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| CN 201120033891 Expired - Lifetime CN201994303U (en) | 2011-01-31 | 2011-01-31 | Through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105590867A (en) * | 2014-10-24 | 2016-05-18 | 无锡超钰微电子有限公司 | Manufacturing method of wafer-level chip scale packaging structure |
-
2011
- 2011-01-31 CN CN 201120033891 patent/CN201994303U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105590867A (en) * | 2014-10-24 | 2016-05-18 | 无锡超钰微电子有限公司 | Manufacturing method of wafer-level chip scale packaging structure |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110928 |