CN201994305U

CN201994305U - Rear-through-hole interconnected wafer-level MOSFET (metal-oxide-semiconductor field effect transistor) packaging structure

Info

Publication number: CN201994305U
Application number: CN 201120033895
Authority: CN
Inventors: 陈栋; 胡正勋; 张黎; 陈锦辉; 赖志明
Original assignee: Jiangyin Changdian Advanced Packaging Co Ltd
Current assignee: Jiangyin Changdian Advanced Packaging Co Ltd
Priority date: 2011-01-31
Filing date: 2011-01-31
Publication date: 2011-09-28
Anticipated expiration: 2021-01-31

Abstract

The utility model relates to a rear-through-hole interconnected wafer-level MOSFET (metal-oxide-semiconductor field-effect transistor) packaging structure. A chip source electrode (2-1) and a chip gate electrode (2-2) are arranged on the face side of a chip body (1-1); a chip-surface protective layer (3) is arranged on the face sides of the chip body, the chip source electrode and the chip gate electrode; a face-side line layer (4) is arranged on the surfaces of the chip body, the chip source electrode, the chip gate electrode and the chip-surface protective layer; a line-surface protective layer (5) is arranged on the surfaces of the face-side line layer and the chip-surface protective layer; welding balls (7) are arranged on the face side of the face-side line layer; and a line layer (6) is arranged on the back side of the chip body and is filled in through holes of the chip, and the line layer filled in through holes of the chip is in direct contact with the side wall of the chip through hole and forms interconnection with the face-side line layer. The rear-through-hole interconnected wafer-level MOSFET packaging structure is the packaging structure with high performance and high reliability.

Description

The interconnected type wafer level of back through hole MOSFET encapsulating structure

Technical field

The utility model relates to a kind of disc grade chip size encapsulating structure.Belong to the semiconductor packaging field.

Background technology

The MOSFET(metal oxide semiconductor field effect tube) be to utilize field effect to control semi-conductive field-effect transistor.Because MOSFET has the characteristic that can realize low power consumption voltage control, receives increasing concern in recent years.The MOSFET performance particularly quality of current carrying capacity depends on heat dispersion to a great extent, and the quality of heat dispersion depends primarily on packing forms again.Yet conventional MOS FET encapsulation mainly is forms such as TO, SOT, SOP, QFN, QFP, and this class encapsulation all is that chip is wrapped in the plastic-sealed body, and the heat that produces in the time of can't be with chip operation is in time led away or left, and has restricted the MSOFET performance boost.And plastic packaging itself increased device size, do not meet the requirement that semiconductor develops to light, thin, short, little direction.With regard to packaging technology, this class encapsulation all is based on single chips to be carried out, and has the problem that production efficiency is low, packaging cost is high.

Disc grade chip size encapsulation (Wafer Level Chip Scale Packaging) is a kind of novel encapsulated technology, and encapsulation back chip is a bare chip, and size is equal to chip size fully, and is based on the batch encapsulation that whole wafer carries out.If the disc grade chip size encapsulation technology can be incorporated into the MOSFET field, not only can promote the MOSFET performance, dwindle package dimension, and can enhance productivity, reduce packaging cost.

Source electrode of MOSFET chip (Source) and grid (Gate) are positioned at chip front side, need the drain electrode (Drain) of metal level as chip be set at chip back or inside.But realize the disc grade chip size encapsulation, also need chip front side is guided in the metal level drain electrode that is provided with, form homonymy with source electrode and grid and distribute.Form the chip drain electrode by forming metallic circuit in chip front side and in the silicon through hole, fill metal and interconnected, so both can having played, the chip drain electrode that forms can be guided to the effect of chip front side again with the metallic circuit in front.

Summary of the invention

The purpose of this utility model is to overcome the deficiency of conventional MOS FET encapsulating structure and its implementation, and a kind of high performance back through hole wafer level MOSFET encapsulating structure that has is provided.

The purpose of this utility model is achieved in that the interconnected type wafer level of a kind of back through hole MOSFET encapsulating structure, comprises the chip body, is provided with chip source electrode and chip gate electrode in chip body front; Be provided with the chip surface protective layer in chip body, chip source electrode and chip gate electrode front; Surface at chip body, chip source electrode, chip gate electrode and chip surface protective layer is provided with the front line layer; Be provided with the circuit sealer at front line layer and chip surface protective layer surface; The circuit laminar surface is provided with soldered ball in the front; Be penetrated with the chip through hole at chip body front and back; Be provided with line layer at the chip body back side, and in the chip through hole, be filled with line layer, and the line layer that is filled in the chip through hole directly contacts with the chip through-hole side wall and forms interconnected with the front line layer.

The beneficial effects of the utility model are:

(1) line layer that directly links to each other by formation and through-hole wall and chip back of the utility model has obtained bigger drain area as the drain electrode as chip, has promoted the current carrying capacity of chip; Line layer plays the fin effect, the radiating effect when having improved chip operation; And the hole layer within the circuit is connected formed drain electrode with the chip front side line layer, thereby has realized being undertaken by the soldered ball and the external world in chip front side interconnected, and this structure has shortened chip and extraneous interconnected distance, has also strengthened chip conduction, heat-conducting effect.

(2) than conventional MOS FET encapsulation, the method for packing that the utility model proposes is based on that whole wafer carries out, rather than carries out based on single; So have production efficiency height, characteristics that packaging cost is low.

Description of drawings

Fig. 1 is the tangent plane schematic diagram of the interconnected type wafer level of through hole MOSFET encapsulating structure behind the utility model.

Fig. 2, Fig. 3 and Fig. 4 are respectively the tangent plane schematic diagram of several detailed structure of interconnect portion A among Fig. 1.

Fig. 5 becomes single packaged chip schematic diagram for the wafer cutting and separating.

Fig. 6 respectively has under the exhausting hole situation for B place adjacent chips among Fig. 5, and cutting position is schematic diagram between through hole.Mode by Fig. 6 obtains interconnect architecture shown in Fig. 2, Fig. 3 tangent plane schematic diagram.

Fig. 7 is for only having under the exhausting hole situation between B place adjacent chips among Fig. 5, and cutting position is positioned at the through hole schematic diagram.Mode by Fig. 7 obtains interconnect architecture shown in Fig. 4 tangent plane schematic diagram.

Reference numeral among the figure:

In the chip body 1-1, chip through hole 1-2, back side 1-3, chip source (source) electrode 2-1, chip grid (gate) electrode 2-2, chip surface protective layer 3, front line layer 4, circuit sealer 5, line layer 6, soldered ball 7, through hole owing to just partly filling cavity 6-1, chip 8, the cutting position C that metal forms.

Embodiment

Referring to Fig. 1, Fig. 1 is the tangent plane schematic diagram of the interconnected type wafer level of through hole MOSFET encapsulating structure behind the utility model.As seen from Figure 1; the interconnected type wafer level of through hole MOSFET encapsulating structure comprises chip body 1-1, chip through hole 1-2, chip source electrode 2-1, chip gate electrode 2-2, chip surface protective layer 3, front line layer 4, circuit sealer 5, soldered ball 7 and line layer 6 behind the utility model.Chip source electrode 2-1 and chip gate electrode 2-2 are arranged at chip body 1-1 front, and chip surface protective layer 3 is arranged at chip body 1-1, chip source electrode 2-1 and chip gate electrode 2-2 front; Front line layer 4 is arranged at chip body 1-1, chip source electrode 2-1, chip gate electrode 2-2 and chip surface protective layer 3 surfaces; Circuit sealer 5 is arranged at front line layer 4 and chip surface protective layer 3 surfaces; Soldered ball 7 is arranged at front line layer 4 surfaces; Chip through hole 1-2 is through chip body 1-1 front and back; Line layer 6 is arranged at the chip body 1-1 back side, and is filled with line layer 6 in chip through hole 1-2, and the line layer that is filled in chip through hole 1-2 directly contacts with chip through hole 1-2 sidewall, and interconnected with 4 formation of front line layer.

Fig. 2, Fig. 3 and Fig. 4 are respectively the tangent plane schematic diagram of several detailed structure of interconnect portion A among Fig. 1.Wherein, Fig. 2 feature is that chip through hole 1-2 is that full hole and line layer 6 do not have airtight chip through hole 1-2, but leaves cavity 6-1; Fig. 3 feature is that chip through hole 1-2 is full hole and line layer 6 airtight chip through hole 1-2, the chamber of not leaving a blank; Fig. 4 feature is that chip through hole 1-2 is half hole, and line layer 6 do not have airtight chip through hole 1-2, but leaves cavity 6-1.

The starting point of encapsulation process is the wafer that has chip source electrode 2-1, chip gate electrode 2-2 and chip surface protective layer 3, the MOSFET chip after obtaining encapsulating by following process:

1), by photoetching, sputter, plating, photoresist lift off and metal etch process, form the front line layer;

2), form the circuit sealer by photoetching process;

3), pass through attenuate, photoetching, silicon etching and photoresist stripping process, formation chip through hole;

4), pass through metal depositing technics such as sputter, evaporation or plated film, formation line layer;

5), by printing solder or electroplate scolder or plant the method for putting soldered ball, refluxing then and form soldered ball;

6), the method by the wafer cutting and separating forms single MSOFET packaged chip.Referring to Fig. 5.Fig. 6 respectively has under the exhausting hole situation for adjacent chips among Fig. 5, and cutting position is schematic diagram between through hole.Mode by Fig. 6 obtains interconnect architecture shown in Fig. 2, Fig. 3 tangent plane schematic diagram.Fig. 7 is for only having under the exhausting hole situation between adjacent chips among Fig. 5, and cutting position is positioned at the through hole schematic diagram.Mode by Fig. 7 obtains interconnect architecture shown in Fig. 4 tangent plane schematic diagram.

Claims

1. the interconnected type wafer level of through hole MOSFET encapsulating structure after a kind comprises chip body (1-1), it is characterized in that: be provided with chip source electrode (2-1) and chip gate electrode (2-2) in described chip body (1-1) front; Be provided with chip surface protective layer (3) in chip body (1-1), chip source electrode (2-1) and chip gate electrode (2-2) front; Surface at chip body (1-1), chip source electrode (2-1), chip gate electrode (2-2) and chip surface protective layer (3) is provided with front line layer (4); Be provided with circuit sealer (5) at front line layer (4) and chip surface protective layer (3) surface; Be provided with soldered ball (7) on front line layer (4) surface; Be penetrated with chip through hole (1-2) at chip body (1-1) front and back; Be provided with line layer (6) at chip body (1-1) back side, and be filled with line layer (6) in chip through hole (1-2), and the line layer (6) that is filled in chip through hole (1-2) directly contacts with chip through hole (1-2) sidewall and form interconnected with front line layer (4).

2. the interconnected type wafer level of a kind of back through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is that full hole and line layer (6) do not have airtight chip through hole (1-2), but leaves cavity (6-1).

3. the interconnected type wafer level of a kind of back through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is full hole and the airtight chip through hole of line layer (6) (1-2), the chamber of not leaving a blank.

4. the interconnected type wafer level of a kind of back through hole according to claim 1 MOSFET encapsulating structure, it is characterized in that: described chip through hole (1-2) is half hole, and line layer (6) do not have airtight chip through hole (1-2), but leaves cavity (6-1).