CN104347431A - Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure - Google Patents
Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure Download PDFInfo
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- CN104347431A CN104347431A CN201310310373.4A CN201310310373A CN104347431A CN 104347431 A CN104347431 A CN 104347431A CN 201310310373 A CN201310310373 A CN 201310310373A CN 104347431 A CN104347431 A CN 104347431A
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 13
- 238000000227 grinding Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 6
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a packaging structure exposing a top surface and a bottom surface of a device and a method for manufacturing the packaging structure. The packaging structure is used for packaging a chip with thinned thickness, a top source electrode of the chip is electrically connected with a contact body and a source electrode pin in corresponding positions in sequence, and a top grid electrode is electrically connected with a contact body and a grid electrode pin in corresponding positions in sequence; a bottom drain electrode of the chip is electrically connected with a bearing part and contact parts of a frame and drain pins on the contact parts in sequence. The pins are insulated and isolated by a first plastic package body and a second plastic package body. The top surface of the packaging structure is flush and used for being electrically connected with other external devices. A bottom surface of the bearing part of the frame electrically connected with the bottom drain electrode of the chip is exposed, thereby effectively improving a heat dissipation effect of the device.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of encapsulating structure exposing device topmost surface and bottom surface, and the manufacture method of this encapsulating structure.
Background technology
At present, such as building the low side MOSFET(metal oxide semiconductor field effect tube in a kind of DC-to-DC converter) chip time, the top source electrode of this MOSFET chip can be exposed the back side being arranged on its encapsulating structure by usual hope, convenient to realize and other external devices such as chip or surface-mounted integrated circuit are carried out while circuit is connected, the face exposure of the bottom drain of this MOSFET chip at encapsulating structure can also be arranged, to improve the radiating effect of device.
It is the schematic diagram of existing a kind of package structure of semiconductor device shown in Fig. 1, the bottom drain of a MOSFET chip 1 is bonded in a main body by conducting resinl 4 and is plate-like and in the framework 2 that upwards bends of relative both sides, this framework 2 is made up of metal alloy or other electric conducting material, there is certain interstitial spaces between sidewall in the edge of described MOSFET chip 1 and framework 2, be filled with insulating barrier 5 at this interstitial spaces place.The both sides end face that described framework 2 upwards bends is formed with some coating further, and the bottom drain as MOSFET chip 1 is positioned at the pin 6 of this framework 2 end face in order to realize being connected with the circuit of external devices.
Compared with the enforcement structure (not shown) flushed with existing another pin 6 place plane A ' and the top source electrode 3 place plane A of this MOSFET chip 1, plane A ' shown in Fig. 1 has better radiating effect lower than the encapsulating structure of plane A, but due to this encapsulating structure end face can not completely and the plane such as surface-mounted integrated circuit bonded to each other, therefore can affect the reliability of electric connection.
Summary of the invention
The object of this invention is to provide and a kind ofly expose encapsulating structure of device topmost surface and bottom surface and preparation method thereof, to reduce the thickness of chip and encapsulating structure, the convenient electric connection with external devices, and better device radiating effect is provided.
In order to achieve the above object, a technical scheme of the present invention is to provide a kind of manufacture method exposing the encapsulating structure of device topmost surface and bottom surface, and it comprises following steps:
Step 1, is formed with multiple chip on a wafer, and each chip comprises top first electrode and top second electrode that are arranged on wafer end face, and is arranged on a bottom electrode of wafer bottom surface;
Step 2, wafer end face corresponds to each top electrodes, is formed with conductive contact respectively;
Step 3, encapsulates at wafer end face, is formed and covers the end face of each chip and the first plastic-sealed body of contact;
Step 4, grinds the bottom surface of wafer, until this wafer is thinned to the thickness of setting; And the wafer after grinding is cut into each chip of single;
Step 5, arranges a conductive framework, described framework be provided with bearing part with around the first relative side of this bearing part and the 3rd side, and the second relative side and the 4th side; This framework is respectively equipped with contact portion in the first side with the 3rd side and is connected with bearing part, and the plane at described contact portion place is higher than the plane at place, described bearing part;
Step 6, is fixed on the bottom surface of chip described in any one on the end face of the bearing part of framework, and forms the electric connection between the bottom electrode of chip and the bearing part of framework and contact portion;
Step 7, encapsulates the framework being connected to chip, makes the contact portion on the contact of each top electrodes on chip and framework, leaves the surface be exposed to outside the second plastic-sealed body end face that encapsulation formed respectively, in order to be electrically connected with external devices; Further, also make the bottom surface of described bearing part on framework, leave the surface be exposed to outside described second plastic-sealed body bottom surface, in order to dispel the heat;
Step 8, at end face each contact of correspondence of whole encapsulating structure and the exposed surface of contact portion, be formed with the pin of coating as respective electrode, realize the electric connection with external devices, wherein, the first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side respectively, the second pin be electrically connected with top first electrode extends to the edge of the second side but the edge terminated in away from the first side and the 3rd side, the 3rd pin be electrically connected with top second electrode extends to the edge of the 4th side but the edge terminated in away from the first side and the 3rd side.
In the embodiment that some are different, chip described in step 1 is a kind of MOSFET chip, is provided with top grid, top source electrode and bottom drain.
Contact described in step 2 to be formed on corresponding top electrodes and protrude from chip end face plant ball or projection.
After grinding, the thickness of described wafer is preferably 1mil or below 1mil.
In step 8, the first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side respectively, but terminates in the edge away from the second side and the 4th side; Along the bottom in these framework four corners, be also formed with breach respectively by etching partially; Described breach is filled by the second plastic-sealed body when encapsulating.
The bearing part area of described framework is greater than the area of chip, the interstitial spaces between described chip and bearing part, is filled by the second plastic-sealed body when encapsulating.
In a preferred embodiment, the end face of described chip and framework is all wrapped in the second plastic-sealed body of encapsulation formation in step 7; By grinding together from the end face of whole encapsulating structure, thus the end face of described contact and contact portion is exposed to outside the end face of the first plastic-sealed body and the second plastic-sealed body, and make described contact, contact portion, the end face of the first plastic-sealed body and the second plastic-sealed body is all in same plane.
In another preferred embodiment, before the bottom surface of described step 4 grinding crystal wafer, first grind at the end face encapsulating wafer, make the end face of contact on each chip after grinding be exposed to outside the end face of described first plastic-sealed body;
Before then encapsulating formation second plastic-sealed body in described step 7, first at the end face masking tape of described chip and framework, thus the surface exposed is needed to protect when encapsulating to contact and contact portion; Further, after packaging cull or grinding are gone to the end face of whole encapsulating structure, make the end face of contact and the first plastic-sealed body on described chip, be all in same plane with the end face of described contact portion and the second plastic-sealed body.
Preferably, by adjusting the distributing position of described coating on chip and framework end face, and the annexation of described coating and corresponding contact body or contact portion, realize reconstructing of whole encapsulating structure surface circuit pattern.
Another technical scheme of the present invention is to provide a kind of encapsulating structure exposing device topmost surface and bottom surface, comprises in described encapsulating structure:
A chip, is provided with top first electrode, top second electrode and bottom electrode; Described top first electrode and top second electrode are formed with conductive contact respectively;
A framework, be provided with bearing part with around the first relative side of this bearing part and the 3rd side, and the second relative side and the 4th side; This framework is respectively equipped with contact portion in the first side with the 3rd side and is connected with bearing part, and the plane at described contact portion place is higher than the plane at place, described bearing part; The bottom surface of described chip is fixed on the end face of the bearing part of this framework, and forms the electric connection between the bottom electrode of described chip and the bearing part of framework and contact portion;
To the plastic-sealed body that described chip and framework encapsulate, realize between each contact on chip, and the contact on chip and separation mutual between the contact portion on framework and insulation; Further, the contact on described chip and the contact portion on framework, leave the surface be exposed to outside plastic-sealed body end face respectively, in order to be electrically connected with external devices; The bottom surface of bearing part on described framework, also leaves the surface outside the bottom surface being exposed to plastic-sealed body, in order to dispel the heat;
At the end face of whole encapsulating structure, the exposed surface of each contact corresponding and contact portion, be formed with the pin of the coat of metal as respective electrode, realize the electric connection with external devices, wherein, the first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side respectively, the second pin be electrically connected with top first electrode extends to the edge of the second side but the edge terminated in away from the first side and the 3rd side, the 3rd pin be electrically connected with top second electrode extends to the edge of the 4th side but the edge terminated in away from the first side and the 3rd side.
In a preferred embodiment, before described chip is fixedly attached on framework, this chip is formed and has covered chip end face and the first plastic-sealed body separated by each contact mutually insulated; Further, the end face of each contact is exposed to outside the end face of described first plastic-sealed body;
After described chip is fixedly attached on framework, the second plastic-sealed body that encapsulation is formed further is at least filled with the interstitial spaces between chip and framework, and the end face of each contact and contact portion is all exposed to outside the end face of described second plastic-sealed body.
In another preferred embodiment, before described chip is fixedly attached on framework, this chip is formed with the first plastic-sealed body chip end face and contact all wrapped up;
After described chip is fixedly attached on framework, be formed with the second plastic-sealed body chip and framework all wrapped up further; Further, ground by the encapsulating structure end face after formation second plastic-sealed body, the end face of described contact and contact portion is exposed to outside the end face of the first plastic-sealed body and the second plastic-sealed body.
Preferably, described plastic-sealed body around chip four limits and extend to the edge of the second side and the 4th side, the portion top surface that the second pin be electrically connected with top first electrode covers described plastic-sealed body extends to the edge of the second side, and the portion top surface that the 3rd pin be electrically connected with top second electrode covers described plastic-sealed body extends to the edge of the 4th side.
Preferably, the end face that described contact and contact portion expose separately, is all in same plane with the end face of described plastic-sealed body.
In preferred embodiment, described chip is a kind of MOSFET chip, and described top first electrode is grid, described top second electrode is source electrode, described bottom electrode is drain electrode.
Described contact to be formed on corresponding top electrodes and protrude from chip end face plant ball or projection.
Before described chip is fixedly attached on framework, the substrate thickness of this chip is preferably 1mil or below 1mil.
The first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side but the edge terminated in away from the second side and the 4th side respectively; Along the bottom in these framework four corners, be also formed with breach respectively by etching partially; Further, described breach is filled by plastic-sealed body when encapsulating.
In sum, compared with prior art, the advantage of encapsulating structure of the present invention and preparation method thereof is, can be applied to encapsulation one makes thickness meet each MOSFET chip of ultra-thin substrate (substrateless) magnitude, effectively to reduce the volume after device package after wafer level grinds.The top source electrode of this chip is electrically connected contact and the source lead of correspondence position successively, and top grid is then electrically connected contact and the gate lead of correspondence position successively; And the bottom drain of chip has been electrically connected bearing part and the contact portion of framework successively, and the drain lead in contact portion.Described gate lead, source lead, drain lead are insulated by the first plastic-sealed body, the second plastic-sealed body each other and isolate, the end face of the encapsulating structure at these pin places flushes, this end face, using in actual applications down as the back side of device, is used for being electrically connected with other external devices.By changing the coating distribution forming described pin, reconstructing of encapsulating structure surface circuit pattern can be realized.In the front of device, then the bottom surface of the framework bearing part bottom drain with chip be electrically connected exposes and arranges, thus effectively improves device radiating effect.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing a kind of package structure of semiconductor device;
Fig. 2, Fig. 3 are the schematic diagram of the front and back of the encapsulating structure of exposure device topmost surface of the present invention and bottom surface respectively;
Fig. 4 ~ Figure 12 is the structural representation that in the manufacture method of the encapsulating structure described in the first with the present invention, each step is corresponding;
Figure 13 ~ Figure 21 is the structural representation corresponding with each step in the manufacture method of encapsulating structure described in the second of the present invention.
Embodiment
Below with reference to accompanying drawing, multiple embodiment of the present invention is described.
Coordinate see shown in Fig. 2, Fig. 3, be described for the encapsulating structure of a MOSFET chip, one side (Fig. 3) on described encapsulating structure exposes and is provided with source lead 52 spaced apart from each other, gate lead 51 and two drain lead 61, the top source electrode 12 of MOSFET chip, top grid 11 and bottom drain 13 is realized, the electric connection corresponding with between other external devices (being such as another chip or surface-mounted integrated circuit etc.) via these pins; Meanwhile, on the framework 40 of carries chips 10, corresponding framework 40 bottom surface connecting bottom drain 13, exposing the another side (Fig. 2) being arranged on described encapsulating structure, dispelling the heat for helping device.
Embodiment 1
As Fig. 4 ~ Figure 12 will introduce the first manufacture method of above-mentioned encapsulating structure, wherein comprise following step:
Steps A 1 shown in Figure 4, be formed with multiple chip 10 on a wafer, each described chip 10 is MOSFET chips, be included in the mutual separated top grid 11 of wafer end face formation and the embodiment of top source electrode 12(Fig. 4 and be provided with two top source electrodes 12), and the bottom drain 13 formed in wafer bottom surface.
Steps A 2 shown in Figure 5, at wafer end face by planting the similar technique such as ball (ball dropping) or projection (wafer bumping), on the top grid 11 and top source electrode 12 of each chip 10, correspondence is formed with the conductive contact 21 and 22 of the one protruding from chip 10 surface, is used for being electrically connected with external devices.Some common materials in related process can be used to form the described contact in respective electrode, such as, be copper, tin, lead etc.
Steps A 3 shown in Figure 6, encapsulate at the end face of wafer, cover the first plastic-sealed body 31 of each chip 10 end face to be formed, and this first plastic-sealed body 31 has enough thickness is all wrapped up therein by the contact 21 and 22 protruding from chip 10 surface.
Steps A 4 shown in Figure 7, the end face of wafer after packaging grinds, that is, corresponding grinding from the first plastic-sealed body 31 end face of each chip 10, at least makes the end face of each contact 21 and 22 to come out.Now the end face of contact 21 and 22 flushes with the end face of the first plastic-sealed body 31.Or in various embodiments, after contact 21 and 22 comes out, can also grind together with the end face of 22 with contact 21 the first plastic-sealed body 31 further, until arrive the thickness requirement of setting.Comparison diagram 6 ~ Fig. 7, can find out that the thickness of the first plastic-sealed body 31 has from H to h(H>h) change.
Steps A 5 shown in Figure 8, grinds in the bottom surface of wafer, until the thickness y of wafer meets ultra-thin substrate (substrateless) magnitude.Comparison diagram 7 ~ Fig. 8, can find out that the thickness of wafer is from Y to y(Y>y) change.Such as, after grinding, the thickness y of wafer is 1mil(Mill) or thinner.
After grinding, wafer is cut, form each independently chip 10.Follow-up correlation step is all carry out for any one chip of single 10.
Steps A 6 shown in Figure 9, arranges the framework 40(Lead Frame of a conduction), such as make this framework 40 by metal or metal alloy materials such as copper.Described framework 40 is roughly the plate-like that wherein two relative edges upwards bend.Hereinafter for convenience of description, the both sides that framework 40 upwards bends are called the first side and the 3rd side, corresponding to the left and right sides in Fig. 9; The other both sides of not bending on framework 40 are called the second side and the 4th side, corresponding to the upper and lower sides in Fig. 9.
That is to say, described framework 40 has a bearing part 41, and is relatively connected to two contact portions 42 outside this side, bearing part 41 first and the 3rd side, and the plane at two contact portion 42 places is higher than the plane at place, bearing part 41.In addition, along the bottom in four corners of framework 40, be also formed with breach 43 respectively by etching partially technique.
Steps A 7 shown in Figure 10, adopts conducting resinl 70 bonding etc. can form method that is fixing and conduction connection, is connected to the bottom surface of chip 10 on the end face of this bearing part 41; Now, the bottom drain 13 of chip 10 is formed with the bearing part 41 of framework 40 down and is electrically connected, and still forms electric connection with two contact portions 42 further by bearing part 41.Bearing part 41 area due to framework 40 is greater than the area of chip 10, therefore between the edge of the edge of chip 10 to bearing part 41, there is interstitial spaces.
Steps A 8, encapsulates the framework 40 being connected to chip 10, forms second plastic-sealed body 32.The material of this second plastic-sealed body 32, can be identical with the material forming above-mentioned first plastic-sealed body 31.And the position just to showing chip 10 in the accompanying drawing of Figure 11 and subsequent step just shows the edge line of chip 10, this edge line might not directly be seen in actual applications as the border of first, second plastic-sealed body 32.
Specifically shown in Figure 11, at the end face of framework 40, the second plastic-sealed body 32 that encapsulation is formed is filled with the interstitial spaces between described chip 10 and bearing part 41; And on framework 40 end face of the second side and the 4th side, side and bottom surface all wrap up by the second plastic-sealed body 32, the breach 43 etching partially formation bottom framework 40 also fill by the second plastic-sealed body 32.After encapsulation, the contact 21 and 22 of chip 10 top source electrode 12 and top grid 11 is exposed to beyond the second plastic-sealed body 32; On framework 40 first side and the 3rd side, the end face of two contact portions 42 and side also all expose setting, are electrically connected with external devices for follow-up.
In advance at chip 10 end face masking tape, thus height can be controlled when encapsulating, and on protect IC 10, the contact 21 and 22, contact portion 42 etc. of such as electrode needs the surface exposed; And remove adhesive tape after packaging, and coordinate carry out cull (deflash) or grinding technics after, residual encapsulating material can be removed, make the end face of encapsulating structure smooth, and guarantee that on chip 10, the described surface exposed that needs is not covered by the second plastic-sealed body 32.Now, preferably make the end face of chip 10 and contact portion 42 and the second plastic-sealed body 32 all at same plane.
Shown in Figure 2, in the bottom surface of framework 40, the second plastic-sealed body 32 is centered around the bottom surface surrounding of chip 10, that is, covered completely the bottom surface of two contact portions 42 on framework 40; By prior masking tape or carry out the similar approach such as bottom surface grinding after packaging, whole (or at least partially) of the bottom surface of bearing part 41 are come out, be mainly used for helping device heat radiation, in other embodiments also can in order to realize the electric connection of chip 10 bottom drain 13 and other devices.
Steps A 9, encapsulating structure end face with can for follow-up welding metal material formed coating, make described coating correspondence be arranged at the end face of each contact 21 and 22 and contact portion 42, carry out the pin be electrically connected as respective electrode on chip 10 and external devices.
Arrange described coating according to actual needs, suitably can also adjust the circuit pattern on encapsulating structure surface further.In the example that Figure 12 provides, the contact 22 of two top source electrodes 12 of chip 10 covers with same coating, this part coating will use as source lead 52.Similar, on the contact 21 of the top grid 11 of chip 10, then cover using another coating as gate lead 51; Further, at the end face of two contact portions 42 of corresponding chip 10 bottom drain 13, the coating as drain lead 61 is also formed with respectively.Wherein, the drain lead 61 be electrically connected with contact portion 42 extends to the edge of the first side and the 3rd side respectively.Due to etch partially formation bottom framework 40 breach 43 also fill by the second plastic-sealed body 32, drain lead 61 terminates in the position away from the second side and four side edge.In the example that Figure 12 provides, drain lead 61 extends to the breach 43 plastic-sealed body edge of filling and etching partially formation respectively continuously along the first side and the 3rd side.In addition, gate lead 51 extends to the edge of the second side of encapsulating structure but the position terminated in away from the first side and the 3rd lateral edges; Source lead 52 extends to the edge of the 4th side of encapsulating structure but the position terminated in away from the first side and the 3rd lateral edges, the convenient situation detecting grid and source electrode when practical application.In the example that Figure 12 provides, plastic-sealed body around chip four limits and extend to the edge of the second side and the 4th side, gate lead 51 and source lead 52 cover the portion top surface of plastic-sealed body respectively and extend to the edge of the second side, the 4th side.In different embodiments, the exposed surface (Fig. 2) of described bearing part 41 on the framework 40 that the bottom drain 13 with chip 10 is electrically connected, can form heat dissipating layer further or connect heat sink; Or, the coating or similar conductive structure that are connected with other device electric also can be formed in the bottom surface of this exposure.
Embodiment 2
As Figure 13 ~ Figure 21 will introduce the second manufacture method of encapsulating structure of the present invention, wherein comprise following step:
Step B1 shown in Figure 13 ~ Figure 15 ~ step B3, similar with the steps A 1 ~ steps A 3 in previous embodiment respectively, be formed with multiple MOSFET chip on a wafer, the top grid 11 of each chip 10 and top source electrode 12 are formed with respectively the contact 21 and 22 of the conduction protruding from chip 10 end face, are also formed with the first plastic-sealed body 31 and cover the end face of chip 10 and each contact 21 and 22 is wrapped in wherein.
Do not need in the present embodiment to grind the end face of wafer, but directly carry out the step B4 shown in Figure 16, grind in the bottom surface of wafer, until the thickness y of wafer meets ultra-thin substrate (substrateless) magnitude.Relatively Figure 15 ~ Figure 16 is visible, and the thickness of the first plastic-sealed body 31 is all H, and the thickness of wafer then has from Y to y(Y>y) change.After grinding, the thickness y of wafer is preferably 1mil(Mill) or thinner.Cutting crystal wafer forms each independently chip 10 afterwards.
The framework 40 of the conduction arranged in the step B5 shown in Figure 17, comprise a bearing part 41 and be relatively connected to two contact portions 42 outside this side, bearing part 41 first and the 3rd side, and the plane at two contact portion 42 places is higher than the plane at place, bearing part 41.In addition, along the bottom in four corners of framework 40, be also formed with breach 43 respectively by etching partially technique.
In step B6 as shown in figure 18, be bonded on the end face of bearing part 41 by the underrun conducting resinl 70 etc. of chip 10, the bottom drain 13 of chip 10 externally can be electrically connected by the bearing part 41 of framework 40 and contact portion 42.
In step B7 as shown in figure 19, by encapsulation, chip 10 and framework 40 are all wrapped in the second plastic-sealed body 32 of formation, all wrap up in the end face of whole encapsulating structure, side and bottom surface, is only come out in the side of two of framework 40 contact portions 42.
In step B8 as shown in figure 20, grind at the end face of encapsulating structure, until the contact 21 and 22 of top grid 11 on chip 10 and top source electrode 12, and the end face of two contact portions 42 on framework 40 is all exposed to beyond the second plastic-sealed body 32.The end face of chip 10 and the end face of the second plastic-sealed body 32 due to together with grind, so both are positioned at same plane after grinding.
As shown in Figure 2, by encapsulating front masking tape or grinding bottom surface after packaging, the bottom surface of the bearing part 41 corresponding with chip 10 bottom drain 13 is exposed and arranges, help heat radiation.
In step B9 as shown in figure 21, at least on the end face of encapsulating structure, the corresponding contact 21 and 22 of each electrode and the end face of contact portion 42 form welding coating, carry out as with external devices the pin that is electrically connected.Further, by adjusting the distributing position of coating further, reconstructing (re-pattern) of encapsulating structure surface circuit pattern can be realized, with the application needs of satisfied reality.Provide in Figure 21 a kind of with Figure 12 in similar circuit pattern, repeat no more.
In sum, in the encapsulating structure formed by above-mentioned two kinds of methods, be preferably applied to encapsulation one and make thickness meet the MOSFET chip of ultra-thin substrate (substrateless) magnitude, effectively to reduce the volume after device package after wafer level grinding.The top source electrode 12 of this chip 10 is electrically connected contact 22 and the source lead 52 of correspondence position successively, and top grid 11 is electrically connected contact 21 and the gate lead 51 of correspondence position successively; And the bottom drain 13 of chip 10 has been electrically connected bearing part 41 and the contact portion 42 of framework 40 successively, and the drain lead 61 in contact portion 42.Described gate lead 51, source lead 52, drain lead 61 to be insulated isolation by the first plastic-sealed body 31, second plastic-sealed body 32 each other, the end face of the encapsulating structure at these pin places flushes, using in actual applications down as the back side (Fig. 3) of device, be used for being electrically connected with other external devices.By changing the coating distribution forming described pin, reconstructing of encapsulating structure surface circuit pattern can be realized.In the front (Fig. 2) of device, then the bottom surface of framework 40 bearing part 41 bottom drain 13 with chip 10 be electrically connected exposes and arranges, and effectively improves device radiating effect.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (17)
1. expose a manufacture method for the encapsulating structure of device topmost surface and bottom surface, it is characterized in that, comprise following steps:
Step 1, is formed with multiple chip on a wafer, and each chip comprises top first electrode and top second electrode that are arranged on wafer end face, and is arranged on a bottom electrode of wafer bottom surface;
Step 2, wafer end face corresponds to each top electrodes, is formed with conductive contact respectively;
Step 3, encapsulates at wafer end face, is formed and covers the end face of each chip and the first plastic-sealed body of contact;
Step 4, grinds the bottom surface of wafer, until this wafer is thinned to the thickness of setting; And the wafer after grinding is cut into each chip of single;
Step 5, arranges a conductive framework, described framework be provided with bearing part with around the first relative side of this bearing part and the 3rd side, and the second relative side and the 4th side; This framework is respectively equipped with contact portion in the first side with the 3rd side and is connected with bearing part, and the plane at described contact portion place is higher than the plane at place, described bearing part;
Step 6, is fixed on the bottom surface of chip described in any one on the end face of the bearing part of framework, and forms the electric connection between the bottom electrode of chip and the bearing part of framework and contact portion;
Step 7, encapsulates the framework being connected to chip, makes the contact portion on the contact of each top electrodes on chip and framework, leaves the surface be exposed to outside the second plastic-sealed body end face that encapsulation formed respectively, in order to be electrically connected with external devices; Further, also make the bottom surface of described bearing part on framework, leave the surface be exposed to outside described second plastic-sealed body bottom surface, in order to dispel the heat;
Step 8, at end face each contact of correspondence of whole encapsulating structure and the exposed surface of contact portion, be formed with the pin of coating as respective electrode, realize the electric connection with external devices, wherein, the first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side respectively, the second pin be electrically connected with top first electrode extends to the edge of the second side but the edge terminated in away from the first side and the 3rd side, the 3rd pin be electrically connected with top second electrode extends to the edge of the 4th side but the edge terminated in away from the first side and the 3rd side.
2. manufacture method as claimed in claim 1, is characterized in that:
Chip described in step 1 is a kind of MOSFET chip, is provided with top grid, top source electrode and bottom drain.
3. manufacture method as claimed in claim 1, is characterized in that:
Contact described in step 2 to be formed on corresponding top electrodes and protrude from chip end face plant ball or projection.
4. manufacture method as claimed in claim 1, is characterized in that:
After grinding, the thickness of described wafer is 1mil or below 1mil.
5. manufacture method as claimed in claim 1, is characterized in that:
In step 8, the first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side respectively, but terminates in the edge away from the second side and the 4th side; Along the bottom in these framework four corners, be also formed with breach respectively by etching partially; Described breach is filled by the second plastic-sealed body when encapsulating.
6. the manufacture method as described in claim 1 or 5, is characterized in that:
The bearing part area of described framework is greater than the area of chip, the interstitial spaces between described chip and bearing part, is filled by the second plastic-sealed body when encapsulating.
7. manufacture method as claimed in claim 1, is characterized in that:
The end face of described chip and framework is all wrapped in the second plastic-sealed body of encapsulation formation in step 7; By grinding together from the end face of whole encapsulating structure, thus the end face of described contact and contact portion is exposed to outside the end face of the first plastic-sealed body and the second plastic-sealed body, and make described contact, contact portion, the end face of the first plastic-sealed body and the second plastic-sealed body is all in same plane.
8. manufacture method as claimed in claim 1, is characterized in that:
Before the bottom surface of described step 4 grinding crystal wafer, first grind at the end face encapsulating wafer, make the end face of contact on each chip after grinding be exposed to outside the end face of described first plastic-sealed body;
Before then encapsulating formation second plastic-sealed body in described step 7, first at the end face masking tape of described chip and framework, thus the surface exposed is needed to protect when encapsulating to contact and contact portion; Further, after packaging cull or grinding are gone to the end face of whole encapsulating structure, make the end face of contact and the first plastic-sealed body on described chip, be all in same plane with the end face of described contact portion and the second plastic-sealed body.
9. manufacture method as claimed in claim 1, is characterized in that:
By adjusting the distributing position of described coating on chip and framework end face, and the annexation of described coating and corresponding contact body or contact portion, realize reconstructing of whole encapsulating structure surface circuit pattern.
10. expose an encapsulating structure for device topmost surface and bottom surface, it is characterized in that, comprise in described encapsulating structure:
A chip, is provided with top first electrode, top second electrode and bottom electrode; Described top first electrode and top second electrode are formed with conductive contact respectively;
A framework, be provided with bearing part with around the first relative side of this bearing part and the 3rd side, and the second relative side and the 4th side; This framework is respectively equipped with contact portion in the first side with the 3rd side and is connected with bearing part, and the plane at described contact portion place is higher than the plane at place, described bearing part; The bottom surface of described chip is fixed on the end face of the bearing part of this framework, and forms the electric connection between the bottom electrode of described chip and the bearing part of framework and contact portion;
To the plastic-sealed body that described chip and framework encapsulate, realize between each contact on chip, and the contact on chip and separation mutual between the contact portion on framework and insulation; Further, the contact on described chip and the contact portion on framework, leave the surface be exposed to outside plastic-sealed body end face respectively, in order to be electrically connected with external devices; The bottom surface of bearing part on described framework, also leaves the surface outside the bottom surface being exposed to plastic-sealed body, in order to dispel the heat;
At the end face of whole encapsulating structure, the exposed surface of each contact corresponding and contact portion, be formed with the pin of the coat of metal as respective electrode, realize the electric connection with external devices, wherein, the first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side respectively, the second pin be electrically connected with top first electrode extends to the edge of the second side but the edge terminated in away from the first side and the 3rd side, the 3rd pin be electrically connected with top second electrode extends to the edge of the 4th side but the edge terminated in away from the first side and the 3rd side.
11. encapsulating structures as claimed in claim 10, is characterized in that:
Before described chip is fixedly attached on framework, this chip is formed and has covered chip end face and the first plastic-sealed body separated by each contact mutually insulated; Further, the end face of each contact is exposed to outside the end face of described first plastic-sealed body;
After described chip is fixedly attached on framework, the second plastic-sealed body that encapsulation is formed further is at least filled with the interstitial spaces between chip and framework, and the end face of each contact and contact portion is all exposed to outside the end face of described second plastic-sealed body.
12. encapsulating structures as claimed in claim 10, is characterized in that:
Described plastic-sealed body around chip four limits and extend to the edge of the second side and the 4th side, the portion top surface that the second pin be electrically connected with top first electrode covers described plastic-sealed body extends to the edge of the second side, and the portion top surface that the 3rd pin be electrically connected with top second electrode covers described plastic-sealed body extends to the edge of the 4th side.
13. encapsulating structures as claimed in claim 12, is characterized in that:
The end face that described contact and contact portion expose separately, is all in same plane with the end face of described plastic-sealed body.
14. encapsulating structures as claimed in claim 10, is characterized in that:
Described chip is a kind of MOSFET chip, and described top first electrode is grid, described top second electrode is source electrode, described bottom electrode is drain electrode.
15. encapsulating structures as claimed in claim 10, is characterized in that:
Described contact to be formed on corresponding top electrodes and protrude from chip end face plant ball or projection.
16. encapsulating structures as claimed in claim 10, is characterized in that:
Before described chip is fixedly attached on framework, the substrate thickness of this chip is 1mil or below 1mil.
17. encapsulating structures as claimed in claim 10, is characterized in that:
The first pin be electrically connected with described contact portion extends to the edge of the first side and the 3rd side but the edge terminated in away from the second side and the 4th side respectively; Along the bottom in these framework four corners, be also formed with breach respectively by etching partially; Further, described breach is filled by plastic-sealed body when encapsulating.
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| CN201310310373.4A CN104347431B (en) | 2013-07-23 | 2013-07-23 | Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure |
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| CN106328545A (en) * | 2015-07-02 | 2017-01-11 | 万国半导体(开曼)股份有限公司 | Ultrathin chip double-surface exposed package structure of and manufacturing method thereof |
| CN110310931A (en) * | 2019-07-15 | 2019-10-08 | 深圳市泛宜微电子技术有限公司 | A kind of chip and potted element |
| CN116544197A (en) * | 2023-07-05 | 2023-08-04 | 华羿微电子股份有限公司 | Power device packaging structure and packaging method |
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| CN104347431B (en) | 2017-04-12 |
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