CN104347431B - Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure - Google Patents
Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure Download PDFInfo
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- CN104347431B CN104347431B CN201310310373.4A CN201310310373A CN104347431B CN 104347431 B CN104347431 B CN 104347431B CN 201310310373 A CN201310310373 A CN 201310310373A CN 104347431 B CN104347431 B CN 104347431B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a packaging structure exposing a top surface and a bottom surface of a device and a method for manufacturing the packaging structure. The packaging structure is used for packaging a chip with thinned thickness, a top source electrode of the chip is electrically connected with a contact body and a source electrode pin in corresponding positions in sequence, and a top grid electrode is electrically connected with a contact body and a grid electrode pin in corresponding positions in sequence; a bottom drain electrode of the chip is electrically connected with a bearing part and contact parts of a frame and drain pins on the contact parts in sequence. The pins are insulated and isolated by a first plastic package body and a second plastic package body. The top surface of the packaging structure is flush and used for being electrically connected with other external devices. A bottom surface of the bearing part of the frame electrically connected with the bottom drain electrode of the chip is exposed, thereby effectively improving a heat dissipation effect of the device.
Description
Technical field
The present invention relates to the encapsulating structure of semiconductor applications, more particularly to a kind of exposure device topmost surface and bottom surface, and should
The manufacture method of encapsulating structure.
Background technology
At present, for example the low side MOSFET in a kind of DC-to-DC converter is built（Metal oxide semiconductcor field effect
Ying Guan）During chip, it is often desirable that the top source electrode exposure of the MOSFET chips can be arranged on the back side of its encapsulating structure, side
Just while realizing that carrying out circuit with the external devices such as other chips or surface-mounted integrated circuit is connected, additionally it is possible to by the MOSFET chips
Bottom drain encapsulating structure face exposure arrange, to improve the radiating effect of device.
It is a kind of schematic diagram of existing package structure of semiconductor device shown in Fig. 1, by the bottom leakage of a MOSFET chip 1
It is that the framework 2 is by metal in the framework 2 that plate-like and relative both sides are folded upward at that pole is bonded in a main body by conducting resinl 4
Alloy or other conductive material are made, exist between the side wall in the edge and framework 2 of the MOSFET chips 1 it is certain between
Every space, insulating barrier 5 is filled with the interstitial spaces.Further formed on the both sides top surface that the framework 2 is folded upward at
There are some coating, the pin 6 of the top surface of framework 2 is located to realize and external devices as the bottom drain of MOSFET chips 1
Circuit connection.
With existing another place plane A of pin 6 ' flush with place plane A of top source electrode 3 of the MOSFET chips 1
Enforcement structure（Not shown in figure）Compare, plane A shown in Fig. 1 ' there is preferably radiating effect less than the encapsulating structure of plane A
Really, but because the top surface of the encapsulating structure can not be completely bonded to each other with the plane such as surface-mounted integrated circuit, therefore can affect electrically
The reliability of connection.
The content of the invention
It is an object of the invention to provide encapsulating structure of a kind of exposure device topmost surface and bottom surface and preparation method thereof, to reduce
The thickness of chip and encapsulating structure, the convenient electric connection with external devices, and more preferable device radiating effect is provided.
In order to achieve the above object, a technical scheme of the invention is to provide the envelope of a kind of exposure device topmost surface and bottom surface
The manufacture method of assembling structure, it is comprised the steps of：
Step 1, is formed with a wafer multiple chips, and each chip includes the top first for being arranged on wafer top surface
Electrode and top second electrode, and it is arranged on a bottom electrode of wafer bottom surface；
Step 2, corresponds to each top electrodes on wafer top surface, is respectively formed with conductive contact；
Step 3, is packaged in wafer top surface, and formation covers the top surface of each chip and the first plastic packaging of contact
Body；
Step 4, is ground to the bottom surface of wafer, until the wafer to be thinned to the thickness of setting；And by after grinding
Wafer is cut into each chip of single；
Step 5, arranges a conductive framework, and the framework is provided with bearing part and around the relative of the bearing part
The first side and the 3rd side, and the second relative side and the 4th side；The framework is respectively equipped with contact in the first side and the 3rd side
Part is connected with bearing part, and the plane that the contact portion is located is higher than the plane that the bearing part is located；
Step 6, the bottom surface of any one of chip is fixed on the top surface of the bearing part of framework, and forms chip
Bottom electrode and framework bearing part and contact portion between electric connection；
Step 7, the framework to being connected to chip is packaged so that the contact and framework of each top electrodes on chip
On contact portion, be respectively kept be exposed to encapsulation formed the second plastic-sealed body top surface outside surface, to external devices
It is electrically connected with；Also, the bottom surface of the bearing part on framework is also caused, is left and is exposed to the second plastic-sealed body bottom surface
Outside surface, to be radiated；
Step 8, in top surface each contact of correspondence and the exposed surface of contact portion of whole encapsulating structure, is formed with plating
Layer realizes the electric connection with external devices as the pin of respective electrode, wherein, with contact portion electric connection
First pin extends respectively into the edge of the first side and the 3rd side, extends with the second pin that top first electrode is electrically connected with
To the second side edge but terminate in edge away from the first side and the 3rd side, the 3rd be electrically connected with top second electrode
Pin extends to the edge of the 4th side but terminates in edge away from the first side and the 3rd side.
In some different embodiments, chip described in step 1 is a kind of MOSFET chips, is provided with top grid, top
Portion's source electrode and bottom drain.
Contact described in step 2 is formed on correspondence top electrodes and protrudes from the plant ball or projection of chip top surface.
The thickness of the wafer is preferably 1mil or below 1mil after grinding.
In step 8, the first pin being electrically connected with the contact portion extends respectively into the side of the first side and the 3rd side
Edge, but terminate in the edge away from the second side and the 4th side；Along the bottom in four corners of framework, also respectively by etching partially shape
Into jagged；The breach is filled in encapsulation by the second plastic-sealed body.
The bearing part area of the framework is more than the area of chip, and the interval between the chip and bearing part is empty
Gap, is filled in encapsulation by the second plastic-sealed body.
In a preferred embodiment, in step 7 the top surface of the chip and framework is all wrapped in encapsulation shape
Into the second plastic packaging body in；Ground together by the top surface from whole encapsulating structure, so as to by the contact and contact portion
Top surface be exposed to outside the top surface of the first plastic-sealed body and the second plastic-sealed body, and cause the contact, contact portion, first
The top surface of plastic-sealed body and the second plastic-sealed body is at same plane.
In another preferred embodiment, before the bottom surface of step 4 grinding crystal wafer, first wafer is encapsulated
Top surface is ground so that the top surface of contact is exposed to outside the top surface of first plastic-sealed body on each chip after grinding；
Then encapsulation is formed before the second plastic-sealed body in the step 7, first in the chip and the top surface rubber cover of framework
Band, so as to need exposed surface to protect contact and contact portion in encapsulation；Also, after packaging to whole envelope
The top surface of assembling structure carries out cull or grinding so that the top surface of contact and the first plastic-sealed body on the chip, connects with described
The top surface of contact portion point and the second plastic-sealed body is at same plane.
Preferably, by adjusting distributing position of the coating on chip and framework top surface, and the coating and phase
Answer the annexation of contact or contact portion to realize reconstructing for whole encapsulating structure surface circuit pattern.
Another technical scheme of the present invention is to provide the encapsulating structure of a kind of exposure device topmost surface and bottom surface, the encapsulation
Include in structure：
One chip, is provided with top first electrode, top second electrode and bottom electrode；The top first electrode and top
Conductive contact is respectively formed with portion's second electrode；
One framework, is provided with bearing part and the first relative side and the 3rd side around the bearing part, and relatively
The second side and the 4th side；The framework is respectively equipped with contact portion and is connected with bearing part in the first side and the 3rd side, and institute
The plane at contact portion place is stated higher than the plane that the bearing part is located；The bottom surface of the chip is fixed on holding for the framework
Carry on the top surface of part, and form electrically connecting between the bottom electrode of the chip and the bearing part of framework and contact portion
Connect；
The plastic-sealed body being packaged to the chip and framework, realizes between each contact on chip, and chip
On contact and framework on contact portion between mutual separation and insulation；Also, the contact and frame on the chip
Contact portion on frame, is respectively kept with the surface being exposed to outside plastic-sealed body top surface, to be electrically connected with external devices；
The bottom surface of bearing part on the framework, also leaves the surface outside the bottom surface for being exposed to plastic-sealed body, to be radiated；
In the top surface of whole encapsulating structure, the exposed surface of each contact and contact portion is corresponded to, be formed with metal-plated
Layer realizes the electric connection with external devices as the pin of respective electrode, wherein, with contact portion electric connection
First pin extends respectively into the edge of the first side and the 3rd side, extends with the second pin that top first electrode is electrically connected with
To the second side edge but terminate in edge away from the first side and the 3rd side, the 3rd be electrically connected with top second electrode
Pin extends to the edge of the 4th side but terminates in edge away from the first side and the 3rd side.
In a preferred embodiment, before the chip is fixedly attached on framework, formed on the chip
There is the first plastic-sealed body for covering chip top surface and separating each contact mutually insulated；Also, the top surface of each contact
It is exposed to outside the top surface of first plastic-sealed body；
After the chip is fixedly attached on framework, the second plastic-sealed body that further encapsulation is formed at least is filled with core
Interstitial spaces between piece and framework, also, the top surface of each contact and contact portion is all exposed to second plastic-sealed body
Top surface outside.
In another preferred embodiment, before the chip is fixedly attached on framework, shape on the chip
Into there is the first plastic-sealed body for all wrapping up chip top surface and contact；
After the chip is fixedly attached on framework, it is formed further with all wrap up chip and framework
Second plastic-sealed body；Also, be ground by the encapsulating structure top surface after the second plastic-sealed body is formed, by the contact and
The top surface of contact portion is exposed to outside the top surface of the first plastic-sealed body and the second plastic-sealed body.
Preferably, the plastic-sealed body is around four sides of chip and extends to the edge of the second side and the 4th side, with top the
The second pin that one electrode is electrically connected with covers the edge that the portion top surface of the plastic-sealed body extends to the second side, with top second
The 3rd pin that electrode is electrically connected with covers the edge that the portion top surface of the plastic-sealed body extends to the 4th side.
Preferably, the respective exposed top surface of the contact and contact portion, is at together with the top surface of the plastic-sealed body
One plane.
In preferred embodiment, the chip is a kind of MOSFET chips, and the top first electrode is grid, the top
It is drain electrode that portion's second electrode is source electrode, the bottom electrode.
The contact is formed on correspondence top electrodes and protrudes from the plant ball or projection of chip top surface.
Before the chip is fixedly attached on framework, the substrate thickness of the chip is preferably 1mil or below 1mil.
The first pin being electrically connected with the contact portion extends respectively into edge but the termination of the first side and the 3rd side
At the edge away from the second side and the 4th side；Along the bottom in four corners of framework, also respectively by etching partially to form jagged；
Also, the breach is filled in encapsulation by plastic-sealed body.
In sum, compared with prior art, the advantage of encapsulating structure of the present invention and preparation method thereof is that it is possible to
Be applied to encapsulation one kind makes thickness meet ultra-thin substrate after wafer level is ground（substrateless）Magnitude each
MOSFET chips, effectively to reduce the volume after device is encapsulated.The top source electrode of the chip is electrically connected with successively correspondence position
Contact and source lead, top grid is then electrically connected with successively the contact and gate lead of correspondence position；And the bottom of chip
Portion's drain electrode has been electrically connected with successively the drain lead on the bearing part and contact portion, and contact portion of framework.The grid
Pole pin, source lead, drain lead are dielectrically separated from each other by the first plastic-sealed body, the second plastic-sealed body, and these pins are located
The top surface of encapsulating structure flush, the top surface using in actual applications down as the back side of device, for other outside devices
Part is electrically connected with.By changing the coating for forming pin distribution, encapsulating structure surface circuit pattern can be realized
Reconstruct.In the front of device, then the bottom surface exposure of the framework bearing part being electrically connected with the bottom drain of chip is arranged,
So as to be effectively improved device radiating effect.
Description of the drawings
Fig. 1 is a kind of schematic diagram of existing package structure of semiconductor device；
Fig. 2, Fig. 3 are respectively the signals of the front and back of the encapsulating structure of exposure device topmost surface of the present invention and bottom surface
Figure；
Fig. 4 ~ Figure 12 is that structure corresponding with each step in the manufacture method of the first encapsulating structure of the invention is shown
It is intended to；
Figure 13 ~ Figure 21 is shown with the corresponding structure of each step in the manufacture method of encapsulating structure described in second of the present invention
It is intended to.
Specific embodiment
Below with reference to accompanying drawing, multiple specific embodiments of the present invention are illustrated.
Coordinate referring to shown in Fig. 2, Fig. 3, illustrate by taking the encapsulating structure of a MOSFET chip as an example, in the encapsulation
One side in structure（Fig. 3）Exposure is provided with source lead spaced apart from each other 52, gate lead 51 and two drain leads 61, Jing
Top source electrode 12, top grid 11 and the bottom drain 13 of MOSFET chips are realized by these pins, with other external devices
（E.g. another chip or surface-mounted integrated circuit etc.）Between corresponding electric connection；Meanwhile, carry on the framework 40 of chip 10,
The bottom surface of framework 40 of correspondence connection bottom drain 13, exposure is arranged on the another side of the encapsulating structure（Fig. 2）, it is used to help device
Part is radiated.
Embodiment 1
As Fig. 4 ~ Figure 12 will introduce the first manufacture method of above-mentioned encapsulating structure, wherein comprising below step：
Step A1 shown in Figure 4, is formed with a wafer multiple chips 10, and each described chip 10 is one
MOSFET chips, are included in the spaced-apart top grid 11 and top source electrode 12 of the formation of wafer top surface（The embodiment of Fig. 4
In be provided with two top source electrodes 12）, and the bottom drain 13 formed in wafer bottom surface.
Step A2 shown in Figure 5, in wafer top surface by planting ball（ball dropping）Or projection（wafer
bumping）Etc. similar technique, it has been correspondingly formed on the top grid 11 and top source electrode 12 of each chip 10 and has protruded from chip
A kind of conductive contact 21 and 22 on 10 surfaces, for being electrically connected with external devices.Related process can be used
In some common materials forming the contact in respective electrode, e.g. copper, stannum, lead etc..
Step A3 shown in Figure 6, is packaged in the top surface of wafer, and to be formed each top surface of chip 10 is covered
First plastic-sealed body 31, and there is first plastic-sealed body 31 enough thickness will protrude from the contact 21 and 22 on the surface of chip 10
All it is wrapped in inside it.
Step A4 shown in Figure 7, is ground on the top surface of wafer after packaging, i.e. correspondence is from each chip
10 top surface of the first plastic-sealed body 31 starts grinding, at least so that the top surface of each contact 21 and 22 can come out.Now
The top surface of contact 21 and 22 is flushed with the top surface of the first plastic-sealed body 31.Or in various embodiments, when the He of contact 21
After 22 come out, further the top surface of the first plastic-sealed body 31 and contact 21 and 22 can also be ground together, directly
To the thickness requirement for reaching setting.Relatively Fig. 6 ~ Fig. 7, it can be seen that the thickness of the first plastic-sealed body 31 has from H to h（H>h）Change
Change.
Step A5 shown in Figure 8, is ground in the bottom surface of wafer, until the thickness y of wafer meets ultra-thin substrate
（substrateless）Magnitude.Relatively Fig. 7 ~ Fig. 8, it can be seen that the thickness of wafer is from Y to y（Y>y）Change.For example, grind
Afterwards the thickness y of wafer is 1mil（Mill）Or it is thinner.
Wafer is cut after grinding, forms each independent chip 10.Follow-up correlation step is both for any one
The chip 10 of single is carrying out.
Step A6 shown in Figure 9, arranges the framework 40 of a conduction（Lead Frame）, such as by metals such as copper or
Metal alloy compositions are making the framework 40.The plate-like that the relative edge of the substantially two of which of the framework 40 is folded upward at.
Infra for convenient description, the both sides being folded upward on framework 40 are referred to as into the first side and the 3rd side, corresponding to the left side in Fig. 9
Right side；Other both sides without bending on framework 40 are referred to as into the second side and the 4th side, corresponding to the upper and lower sides in Fig. 9.
I other words, the framework 40 has a bearing part 41, and is relatively connected to the bearing part 41 first
Two contact portions 42 on the outside of side and the 3rd side, and the plane that two contact portions 42 are located is located higher than bearing part 41
Plane.In addition, the bottom in four corners along framework 40, is also respectively formed with breach 43 by etching partially technique.
Step A7 shown in Figure 10, using bonding of conducting resinl 70 etc. method that is fixed and being conductively connected can be formed,
The bottom surface of chip 10 is connected on the top surface of the bearing part 41；Now, the bottom drain 13 of chip 10 down with framework 40
Bearing part 41 be electrically connected, also further also formed with two contact portions 42 by bearing part 41 and electrically connected
Connect.Because the area of bearing part 41 of framework 40 is more than the area of chip 10, therefore at the edge of chip 10 to bearing part 41
Edge between there are interstitial spaces.
Step A8, the framework 40 to being connected to chip 10 is packaged, and forms second plastic-sealed body 32.Second plastic packaging
The material of body 32, can be identical with the material for forming above-mentioned first plastic-sealed body 31.And in the accompanying drawing of Figure 11 and subsequent step only
Position only for showing chip 10 just shows the edge line of chip 10, and the edge line is used as first, second plastic-sealed body 32
Border might not be immediately seen in actual applications.
It is concrete shown in Figure 11, in the top surface of framework 40, encapsulate the second plastic-sealed body 32 for being formed and be filled with the core
Interstitial spaces between piece 10 and bearing part 41；And on framework 40 top surface of the second side and the 4th side, side and bottom surface all by
Second plastic-sealed body 32 is wrapped up, and the bottom of framework 40 etches partially the breach 43 to be formed and also filled by the second plastic-sealed body 32.After encapsulation,
The contact 21 and 22 of the top source electrode 12 of chip 10 and top grid 11 is exposed to beyond the second plastic-sealed body 32；The side of framework 40 first
Also all exposure is arranged with the top surface of two contact portions 42 and side on the 3rd side, for subsequently electrically being connected with external devices
Connect.
So as to the control height in encapsulation, and can protect on chip 10 for example in advance in the top surface masking tape of chip 10
Contact 21 and 22, contact portion 42 of electrode etc. needs exposed surface；And adhesive tape is removed after packaging, and cooperation is gone
Cull（deflash）Or after grinding technics, the encapsulating material of residual can be removed so that the top surface of encapsulating structure is smooth, and
Guarantee described on chip 10 to need exposed surface not covered by the second plastic-sealed body 32.Now, preferably cause chip 10 with
The top surface of the plastic-sealed body 32 of contact portion 42 and second is all in same plane.
Shown in Figure 2, in the bottom surface of framework 40, the second plastic-sealed body 32 is centered around the bottom surface surrounding of chip 10, i.e. by frame
The bottom surface of two contact portions 42 is completely covered on frame 40；The classes such as bottom surface grinding are carried out by prior masking tape or after packaging
Like method, by the whole of the bottom surface of bearing part 41（Or at least a portion）Come out, be mainly used for helping device radiating,
In other embodiments also can be to realize the electric connection of the bottom drain 13 of chip 10 and other devices.
Step A9, in the top surface of encapsulating structure to be available for subsequently welding the metal material for using formation coating, makes the plating
Layer is correspondingly arranged in the top surface of each contact 21 and 22 and contact portion 42, used as respective electrode and external devices on chip 10
The pin being electrically connected with.
According to actual needs arranging described coating, additionally it is possible to the further circuit diagram on appropriate adjustment encapsulating structure surface
Case.In the example that Figure 12 is provided, covered with same coating on the contact 22 of two top source electrodes 12 of chip 10
Lid, this part coating will be used as source lead 52.Similar, on the contact 21 of the top grid 11 of chip 10, then
Cover using another as the coating of gate lead 51；Also, in two contact portions 42 of the correspondence bottom drain 13 of chip 10
Top surface, be also respectively formed with the coating as drain lead 61.Wherein, the drain lead being electrically connected with contact portion 42
61 edges for extending respectively into the first side and the 3rd side.Because the bottom of framework 40 etches partially the breach 43 to be formed also by the second plastic packaging
Body 32 is filled, and drain lead 61 terminates in the position away from the second side and four side edge.In the example that Figure 12 is provided,
Drain lead 61 is continuously extended to fill and etches partially the plastic-sealed body edge of breach 43 to be formed along the first side and the 3rd side respectively.Separately
Outward, gate lead 51 extends to the edge of the second side of encapsulating structure but terminates in position away from the first side and the 3rd lateral edges
Put；Source lead 52 extends to the edge of the 4th side of encapsulating structure but terminates in position away from the first side and the 3rd lateral edges
Put, the convenient situation that grid and source electrode are detected in practical application.In the example that Figure 12 is provided, plastic-sealed body surrounds the four of chip
Side simultaneously extends to the edge of the second side and the 4th side, and gate lead 51 and source lead 52 are covered each by the part top of plastic-sealed body
Face simultaneously extends to the second side, the edge of the 4th side.In different embodiments, it is electrically connected with the bottom drain 13 with chip 10
The exposed surface of the bearing part 41 on framework 40（Fig. 2）, can further form heat dissipating layer or connection radiating piece；Or,
The coating that can also connect with other device electrics in the exposed bottom surface formation or similar conductive structure.
Embodiment 2
As Figure 13 ~ Figure 21 will introduce second manufacture method of encapsulating structure of the present invention, wherein comprising following step
Suddenly：
Step B1 shown in Figure 13 ~ Figure 15 ~ step B3, it is similar with step A1 ~ step A3 in previous embodiment respectively,
Multiple MOSFET chips are formed with a wafer, are formed respectively on the top grid 11 and top source electrode 12 of each chip 10
There is the conductive contact 21 and 22 for protruding from the top surface of chip 10, be also formed with the top surface that the first plastic-sealed body 31 is covered in chip 10
And wrap up each contact 21 and 22 wherein.
The top surface of wafer need not be ground in the present embodiment, but directly carry out step B4 shown in Figure 16,
The bottom surface of wafer is ground, until the thickness y of wafer meets ultra-thin substrate（substrateless）Magnitude.Compare Figure 15 ~ figure
16 is visible, and the thickness of the first plastic-sealed body 31 is all H, and the thickness of wafer then has from Y to y（Y>y）Change.The thickness of wafer after grinding
Degree y is preferably 1mil（Mill）Or it is thinner.Afterwards cutting crystal wafer forms each independent chip 10.
The conductive framework 40 arranged in step B5 shown in Figure 17, is connected to comprising a bearing part 41 and relatively
Two contact portions 42 on the outside of the side of bearing part 41 first and the 3rd side, and the plane height that two contact portions 42 are located
In the plane that bearing part 41 is located.In addition, the bottom in four corners along framework 40, also distinguishes shape by etching partially technique
Into jagged 43.
In step B6 as shown in figure 18, underrun conducting resinl 70 of chip 10 etc. is bonded in into the top of bearing part 41
On face, the bottom drain 13 of chip 10 externally can electrically be connected by the bearing part 41 of framework 40 and contact portion 42
Connect.
In step B7 as shown in figure 19, chip 10 and framework 40 are all wrapped in by the second plastic-sealed body to be formed by encapsulation
In 32, the top surface, side and bottom surface in whole encapsulating structure is all wrapped up, only by the side of two contact portions 42 of framework 40
Come out in face.
In step B8 as shown in figure 20, it is ground in the top surface of encapsulating structure, the top grid on chip 10
11 and the contact 21 and 22 of top source electrode 12, and the top surface of two contact portions 42 on framework 40 is all exposed to the second modeling
Beyond envelope body 32.The top surface of chip 10 is ground with the top surface of the second plastic-sealed body 32 due to together with, so both are grinding
It is generally aligned in the same plane after mill.
As shown in Fig. 2 being ground by masking tape before encapsulation or after packaging to bottom surface so that with the bottom of chip 10
The bottom surface exposure of portion 13 corresponding bearing parts 41 of drain electrode is arranged, and helps radiate.
In step B9 as shown in figure 21, the contact 21 and 22 of each electrode of correspondence at least on the top surface of encapsulating structure
Welding coating is formed with the top surface of contact portion 42, as the pin being electrically connected with external devices.And it is possible to
Reconstructing for encapsulating structure surface circuit pattern is realized by the distributing position of further adjustment coating（re-pattern）,
To meet actual application needs.A kind of circuit pattern similar with Figure 12 is provided in Figure 21, is repeated no more.
In sum, in the encapsulating structure for being formed by above two method, encapsulation one kind is preferably applied in wafer scale
Not Yan Mo after make thickness meet ultra-thin substrate（substrateless）The MOSFET chips of magnitude, effectively to reduce device encapsulation
Volume afterwards.The top source electrode 12 of the chip 10 is electrically connected with successively the contact 22 and source lead 52 of correspondence position, top
Grid 11 is then electrically connected with successively the contact 21 and gate lead 51 of correspondence position；And the bottom drain 13 of chip 10 is electric successively
Property is connected to bearing part 41 and the contact portion 42 of framework 40, and the drain lead 61 in contact portion 42.The grid
Pin 51, source lead 52, drain lead 61 are dielectrically separated from each other by the first plastic-sealed body 31, the second plastic-sealed body 32, these
The top surface of the encapsulating structure that pin is located is flushed, using in actual applications down as the back side of device（Fig. 3）, for other
External devices are electrically connected with.By changing the coating for forming pin distribution, encapsulating structure surface circuit can be realized
Pattern is reconstructed.In the front of device（Fig. 2）, then the supporting part of framework 40 being electrically connected with the bottom drain 13 with chip 10
The bottom surface exposure for dividing 41 is arranged, and is effectively improved device radiating effect.
Although present disclosure has been made to be discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
Various modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (24)
1. it is a kind of exposure device topmost surface and bottom surface encapsulating structure manufacture method, it is characterised in that comprise the steps of：
Step 1, is formed with a wafer multiple chips, and each chip includes the top first electrode for being arranged on wafer top surface
With top second electrode, an and bottom electrode for being arranged on wafer bottom surface；
Step 2, corresponds to each top electrodes on wafer top surface, is respectively formed with conductive contact；
Step 3, is packaged in wafer top surface, and formation covers the top surface of each chip and the first plastic-sealed body of contact；
Step 4, is ground to the bottom surface of wafer, until the wafer to be thinned to the thickness of setting；And by the wafer after grinding
It is cut into each chip of single；
Step 5, arranges a conductive framework, and the framework is provided with bearing part and around relative the of the bearing part
Side and the 3rd side, and the second relative side and the 4th side；The framework is respectively equipped with contact portion in the first side and the 3rd side
It is connected with bearing part, and the plane that the contact portion is located is higher than the plane that the bearing part is located；
Step 6, the bottom surface of any one of chip is fixed on the top surface of the bearing part of framework, and forms the bottom of chip
Electric connection between the bearing part and contact portion of portion's electrode and framework；
Step 7, the framework to being connected to chip is packaged so that on chip on the contact and framework of each top electrodes
Contact portion, is respectively kept with the surface being exposed to outside the second plastic-sealed body top surface that encapsulation is formed, to carry out with external devices
It is electrically connected with；Also, the bottom surface of the bearing part on framework is also caused, is left and is exposed to outside the second plastic-sealed body bottom surface
Surface, to be radiated；
Step 8, in top surface each contact of correspondence and the exposed surface of contact portion of whole encapsulating structure, is formed with coating work
For the pin of respective electrode, the electric connection with external devices is realized, wherein, first be electrically connected with the contact portion
Pin extends respectively into the edge of the first side and the 3rd side, and the second pin being electrically connected with top first electrode extends to the
The edge of two sides but edge away from the first side and the 3rd side is terminated in, the 3rd pin being electrically connected with top second electrode
Extend to the edge of the 4th side but terminate in edge away from the first side and the 3rd side.
2. manufacture method as claimed in claim 1, it is characterised in that：
Chip described in step 1 is a kind of MOSFET chips, is provided with top grid, top source electrode and bottom drain.
3. manufacture method as claimed in claim 1, it is characterised in that：
Contact described in step 2 is formed on correspondence top electrodes and protrudes from the plant ball or projection of chip top surface.
4. manufacture method as claimed in claim 1, it is characterised in that：
The thickness of the wafer is 1 Mill after grinding.
5. manufacture method as claimed in claim 1, it is characterised in that：
The thickness of the wafer is below 1 Mill after grinding.
6. manufacture method as claimed in claim 1, it is characterised in that：
In step 8, the first pin being electrically connected with the contact portion extends respectively into the edge of the first side and the 3rd side, but
Terminate in the edge away from the second side and the 4th side；Along the bottom in four corners of framework, also pass through to etch partially respectively to be formed with
Breach；The breach is filled in encapsulation by the second plastic-sealed body.
7. the manufacture method as described in claim 1 or 6, it is characterised in that：
The bearing part area of the framework more than chip area, the interstitial spaces between the chip and bearing part,
Filled by the second plastic-sealed body during encapsulation.
8. manufacture method as claimed in claim 1, it is characterised in that：
In step 7 the top surface of the chip and framework is all wrapped in the second plastic packaging body that encapsulation is formed；By from whole
The top surface of individual encapsulating structure grinds together, so as to the top surface of the contact and contact portion is exposed to into the first plastic-sealed body and
Outside the top surface of two plastic-sealed bodies, and cause the top surface of the contact, contact portion, the first plastic-sealed body and the second plastic-sealed body all
It is in same plane.
9. manufacture method as claimed in claim 1, it is characterised in that：
Before the bottom surface of step 4 grinding crystal wafer, be first ground in the top surface for encapsulating wafer so that after grinding each
The top surface of contact is exposed to outside the top surface of first plastic-sealed body on chip；
Then encapsulation is formed before the second plastic-sealed body in the step 7, first in the chip and the top surface masking tape of framework, from
And need exposed surface to protect contact and contact portion in encapsulation；Also, after packaging to whole encapsulation knot
The top surface of structure carries out cull or grinding so that the top surface of contact and the first plastic-sealed body on the chip, with the contact site
Divide and the top surface of the second plastic-sealed body is at same plane.
10. manufacture method as claimed in claim 1, it is characterised in that：
By adjusting the distributing position of the coating on chip and framework top surface, and the coating and corresponding contact body or connect
The annexation of contact portion point is realizing reconstructing for whole encapsulating structure surface circuit pattern.
A kind of 11. exposure device topmost surfaces and the encapsulating structure of bottom surface, it is characterised in that include in the encapsulating structure：
One chip, is provided with top first electrode, top second electrode and bottom electrode；The top first electrode and top
Conductive contact is respectively formed with two electrodes；It is formed with the chip and covers the chip top surface and contact each
First plastic-sealed body of the mutual dielectric separation of body phase；Also, the top surface of each contact be exposed to first plastic-sealed body top surface it
Outward；
One framework, is provided with bearing part and the first relative side and the 3rd side around the bearing part, and relative
Two sides and the 4th side；The framework is respectively equipped with contact portion and is connected with bearing part in the first side and the 3rd side, and described connects
The plane that contact portion point is located is higher than the plane that the bearing part is located；The bottom surface of the chip is fixed on the supporting part of the framework
On the top surface for dividing, and form the electric connection between the bottom electrode of the chip and the bearing part of framework and contact portion；
The second plastic-sealed body being packaged to the chip and framework, realizes between each contact on chip, and chip
On contact and framework on contact portion between mutual separation and insulation；Also, the contact and frame on the chip
Contact portion on frame, is respectively kept with the surface being exposed to outside the second plastic-sealed body top surface, to carry out electrically with external devices
Connection；The bottom surface of bearing part on the framework, also leaves the surface being exposed to outside the bottom surface of the second plastic-sealed body, to carry out
Radiating；Wherein, second plastic-sealed body is at least filled with the interstitial spaces between chip and framework, and each contact on chip
The top surface of the contact portion on the top surface and framework of body, is all exposed to outside the top surface of second plastic-sealed body；
In the top surface of whole encapsulating structure, the exposed surface of each contact and contact portion is corresponded to, be formed with coat of metal work
For the pin of respective electrode, the electric connection with external devices is realized, wherein, first be electrically connected with the contact portion
Pin extends respectively into the edge of the first side and the 3rd side, and the second pin being electrically connected with top first electrode extends to the
The edge of two sides but edge away from the first side and the 3rd side is terminated in, the 3rd pin being electrically connected with top second electrode
Extend to the edge of the 4th side but terminate in edge away from the first side and the 3rd side.
12. encapsulating structures as claimed in claim 11, it is characterised in that：
Second plastic-sealed body surrounds four sides of chip and extends to the edge of the second side and the 4th side, with top first electrode electricity
Property connection second pin cover the portion top surface of second plastic-sealed body and extend to the edge of the second side, with top second electrode
The 3rd pin being electrically connected with covers the edge that the portion top surface of second plastic-sealed body extends to the 4th side.
13. encapsulating structures as claimed in claim 12, it is characterised in that：
The respective exposed top surface of the contact and contact portion, with the top surface of second plastic-sealed body same plane is at.
14. encapsulating structures as claimed in claim 11, it is characterised in that：
The chip is a kind of MOSFET chips, and it is source electrode, institute that the top first electrode is grid, the top second electrode
It is drain electrode to state bottom electrode.
15. encapsulating structures as claimed in claim 11, it is characterised in that：
The contact is formed on correspondence top electrodes and protrudes from the plant ball or projection of chip top surface.
16. encapsulating structures as claimed in claim 11, it is characterised in that：
Before the chip is fixedly attached on framework, the substrate thickness of the chip is 1 Mill.
17. encapsulating structures as claimed in claim 11, it is characterised in that：
Before the chip is fixedly attached on framework, the substrate thickness of the chip is below 1 Mill.
A kind of 18. exposure device topmost surfaces and the encapsulating structure of bottom surface, it is characterised in that include in the encapsulating structure：
One chip, is provided with top first electrode, top second electrode and bottom electrode；The top first electrode and top
Conductive contact is respectively formed with two electrodes；
One framework, is provided with bearing part and the first relative side and the 3rd side around the bearing part, and relative
Two sides and the 4th side；The framework is respectively equipped with contact portion and is connected with bearing part in the first side and the 3rd side, and described connects
The plane that contact portion point is located is higher than the plane that the bearing part is located；The bottom surface of the chip is fixed on the supporting part of the framework
On the top surface for dividing, and form the electric connection between the bottom electrode of the chip and the bearing part of framework and contact portion；
The plastic-sealed body being packaged to the chip and framework, realizes between each contact on chip, and on chip
Mutual separation and insulation between contact portion on contact and framework；Also, on the contact and framework on the chip
Contact portion, the surface being exposed to outside plastic-sealed body top surface is respectively kept with, to be electrically connected with external devices；It is described
The bottom surface of bearing part on framework, also leaves the surface outside the bottom surface for being exposed to plastic-sealed body, to be radiated；
In the top surface of whole encapsulating structure, the exposed surface of each contact and contact portion is corresponded to, be formed with coat of metal work
For the pin of respective electrode, the electric connection with external devices is realized, wherein, first be electrically connected with the contact portion
Pin extends respectively into the edge of the first side and the 3rd side but terminates in edge away from the second side and the 4th side, with top first
The second pin that electrode is electrically connected with extends to the edge of the second side but terminates in edge away from the first side and the 3rd side, with top
The 3rd pin that portion second electrode is electrically connected with extends to the edge of the 4th side but terminates in side away from the first side and the 3rd side
Edge；
Wherein, along the bottom in four corners of the framework, also respectively by etching partially to form jagged；Also, the breach exists
Filled by plastic-sealed body during encapsulation.
19. encapsulating structures as claimed in claim 18, it is characterised in that：
The plastic-sealed body surrounds four sides of chip and extends to the edge of the second side and the 4th side, electrically connects with top first electrode
The second pin for connecing covers the edge that the portion top surface of the plastic-sealed body extends to the second side, is electrically connected with top second electrode
The 3rd pin cover the portion top surface of the plastic-sealed body and extend to the edge of the 4th side.
20. encapsulating structures as claimed in claim 19, it is characterised in that：
The respective exposed top surface of the contact and contact portion, with the top surface of the plastic-sealed body same plane is at.
21. encapsulating structures as claimed in claim 18, it is characterised in that：
The chip is a kind of MOSFET chips, and it is source electrode, institute that the top first electrode is grid, the top second electrode
It is drain electrode to state bottom electrode.
22. encapsulating structures as claimed in claim 18, it is characterised in that：
The contact is formed on correspondence top electrodes and protrudes from the plant ball or projection of chip top surface.
23. encapsulating structures as claimed in claim 18, it is characterised in that：
Before the chip is fixedly attached on framework, the substrate thickness of the chip is 1 Mill.
24. encapsulating structures as claimed in claim 18, it is characterised in that：
Before the chip is fixedly attached on framework, the substrate thickness of the chip is below 1 Mill.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310310373.4A CN104347431B (en) | 2013-07-23 | 2013-07-23 | Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310310373.4A CN104347431B (en) | 2013-07-23 | 2013-07-23 | Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure |
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| CN106328545A (en) * | 2015-07-02 | 2017-01-11 | 万国半导体(开曼)股份有限公司 | Ultrathin chip double-surface exposed package structure of and manufacturing method thereof |
| CN110310931A (en) * | 2019-07-15 | 2019-10-08 | 深圳市泛宜微电子技术有限公司 | A kind of chip and potted element |
| CN116544197A (en) * | 2023-07-05 | 2023-08-04 | 华羿微电子股份有限公司 | Power device packaging structure and packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6410363B1 (en) * | 1997-03-10 | 2002-06-25 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing same |
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| US7242076B2 (en) * | 2004-05-18 | 2007-07-10 | Fairchild Semiconductor Corporation | Packaged integrated circuit with MLP leadframe and method of making same |
| US7786558B2 (en) * | 2005-10-20 | 2010-08-31 | Infineon Technologies Ag | Semiconductor component and methods to produce a semiconductor component |
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| US6410363B1 (en) * | 1997-03-10 | 2002-06-25 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing same |
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Effective date of registration: 20200428 Address after: Ontario, Canada Patentee after: World semiconductor International Limited Partnership Address before: 475 oakmead Park Road, Sunnyvale, California 94085, USA Patentee before: Alpha and Omega Semiconductor Inc. |