CN110310931A - A kind of chip and potted element - Google Patents
A kind of chip and potted element Download PDFInfo
- Publication number
- CN110310931A CN110310931A CN201910636804.3A CN201910636804A CN110310931A CN 110310931 A CN110310931 A CN 110310931A CN 201910636804 A CN201910636804 A CN 201910636804A CN 110310931 A CN110310931 A CN 110310931A
- Authority
- CN
- China
- Prior art keywords
- electrode
- chip
- electrodes
- semiconductor material
- material layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The embodiment of the invention provides a kind of chips characterized by comprising semiconductor material layer；First electrode, the first electrode are arranged on the first surface of the semiconductor material layer；Second electrode, the second electrode are arranged on the semiconductor material layer second surface opposite with first surface；At least two third electrodes, the third electrode are arranged on the semiconductor conducting layer second surface opposite with first surface, and at least two thirds distribution of electrodes is around the second electrode；The distance that setting is spaced between the first electrode, second electrode and at least two third electrodes is either filled by insulating materials.Chip provided in an embodiment of the present invention can shorten the distance between two electrodes, reduce power consumption.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of chips and potted element.
Background technique
Semiconductor chip application is an invention of twentieth century, and the mankind is made to have subsequently entered electronics industry epoch and information
The change epoch.Comprehensively utilizing the microwave integrated circuit that a variety of semiconductor materials and device function are prepared is the various height of current development
The mainstay of scientific and technological weapon, be widely used in various advanced tactical missiles, electronic warfare, communication system, land-sea space base it is various
Advanced phased-array radar (especially airborne and spaceborne radar)；In the mobile phone of civilian business, wireless communication, personal satellite
Communication network, global positioning system, direct broadcast satellite reception and millimeter wave automatic collision avoidance system etc., which have been formed, to be developed rapidly
Great market.
With the development of electronic technology, the requirement of especially high-power semiconductor devices, the thermal diffusivity of semiconductor chip
It can be more and more important.On the one hand need to reduce the heat production of semiconductor chip, still further aspect, it is also desirable to increase semiconductor chip
Heat-sinking capability.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of chip and encapsulation components.
The embodiment of the invention provides a kind of chips characterized by comprising
Semiconductor material layer；
First electrode, the first electrode are arranged on the first surface of the semiconductor material layer；
The semiconductor material layer second surface opposite with first surface is arranged in second electrode, the second electrode
On；
Opposite with first surface of the semiconductor conducting layer is arranged at least two third electrodes, the third electrode
On two surfaces, and at least two thirds distribution of electrodes is around the second electrode；The first electrode, second electrode with
And at least two the distance of setting is spaced between third electrode or pass through insulating materials fill it is provided in an embodiment of the present invention
Electronic component is encapsulated, special three-decker is formed, the first conductive layer and third conductive layer form non-coplanar design, simplify envelope
Dress technique, heat radiation ability.
The embodiment of the invention also provides a kind of potted element, including said chip, the first conductive layer and the second conduction
Layer；
Wherein first conductive layer is arranged on the third surface of the chip；
Second conductive layer is arranged on the 4th surface of the chip, wherein the third surface and the 4th surface phase
It is right.
Chip and potted element provided in an embodiment of the present invention, can improve the hot property of chip, improve the fortune of chip
Row performance.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without any creative labor, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of chip provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another chip provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another chip provided in an embodiment of the present invention；
Fig. 4 is a kind of circuit theory schematic diagram for encapsulating electronic component provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of encapsulation electronic component provided in an embodiment of the present invention.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, to understand thoroughly the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention also may be implemented in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, in case unnecessary details interferes description of the invention.
The terms such as " first " of the embodiment of the present invention, " second ", only difference the relevant technologies feature, do not indicate successively suitable
Sequence.
In order to illustrate technical solution described in the embodiment of the present invention, the following is a description of specific embodiments.
Chip provided in an embodiment of the present invention is the chip applied in power device package element, for example apply big
Power transistor, thyristor, bidirectional thyristor, GTO (Gate-Turn-Off Thyristor, turn-off thyristor), MOSFET
(Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate
Bipolar Transistor) etc. in chip in electronic component.
As shown in Figure 1-3, being chip provided in an embodiment of the present invention.Specific chip includes semiconductor material layer 120,
A kind of illustrative embodiment, the semiconductor material layer are crystal silicon layer.As shown, the semiconductor material layer 120
For flat rectangular configuration, the semiconductor material layer includes first surface, and the second surface opposite with first surface.
As shown in Figs. 1-3, the lower surface of semiconductor material layer 120 is first surface, and the upper surface of semiconductor material layer 120 is second
Surface.
The chip includes first electrode 130.A kind of specific embodiment, the first electrode are D grades (drain).
A kind of specific embodiment, the first electrode are conductive layer, compare the preferably first electrode and lead for conduction
Thermosphere, such as layers of copper.By taking layers of copper as an example, the first electrode 130, which can be, fits to the first of the semiconductor material layer 120
On surface.The layers of copper can be through plating formation, is also possible to metal copper layer and presses to the semiconductor material layer 120
First surface on.
A kind of specific embodiment, the first electrode 130 cover in the first surface of the semiconductor material layer 120
Most region.As shown in Figure 1-3, the first electrode 130 covers the area that the semiconductor material layer 120 is more than 80%
Domain.Increase area coverage, the heat-sinking capability of subsequent chip can be enhanced and reduces the distance of electron-transport.
Chip provided in an embodiment of the present invention further includes having second electrode 140.A kind of specific embodiment, described second
Electrode is G grades (grid).A kind of specific embodiment, the second electrode 140 are conductive layer, compare preferably institute
Stating second electrode 140 is thermally conductive layer, such as layers of copper.By taking layers of copper as an example, the second electrode 140 can be fit to it is described
On the second surface of semiconductor material layer 120.The layers of copper can be through plating formation, be also possible to metal copper layer pressing
Onto the second surface of the semiconductor material layer 120.The second electrode at least one end extends to the side of the second surface
Boundary.As shown in Figure 1-3, one end of the second electrode 140 extends to the distance of the setting of a boundary apart from second surface, example
As at least 0.3mm is adapted to the demand of high pressure when the distance apart from boundary is more than or equal to 0.6mm；The other end extends
The distance set to another boundary of second surface, for example, at least 0.3mm, when the distance apart from boundary is more than or equal to
When 0.6mm, it is adapted to the demand of high pressure.
Chip provided in an embodiment of the present invention further includes having at least two third electrodes 110.A kind of specific embodiment,
The third electrode 110 is S grades (source electrode).A kind of specific embodiment, the third electrode 110 is conductive layer, more excellent
The mode of choosing is that the third electrode 110 is thermally conductive layer, such as layers of copper.By taking layers of copper as an example, the third electrode 110 can be with
It is to fit on the second surface of the semiconductor material layer 120.The layers of copper can be through plating formation, be also possible to
Metal copper layer presses on the second surface of the semiconductor material layer 120.
The second electrode 140 and at least two third electrodes 110 can cover the semiconductor material layer 120 second
Most of region on surface, such as the region more than 80%.In such a way that this large area covers, increase the area of heat dissipation,
Improve heat dissipation performance.
As shown in Figure 1, being a kind of specific chip structure schematic diagram provided in an embodiment of the present invention.Specifically, described
Two electrodes 140 are located on the perpendicular bisector on a boundary of the first surface.
The chip 100 includes that there are two third electrodes 110.A kind of specific embodiment, described two third electrodes
110 are symmetrically distributed in 140 two sides of second electrode.And interval setting between the second electrode 140 and third electrode 110
Distance, such as 0.2mm, to guarantee between second electrode 140 and third electrode 110 without short circuit.Another way, such as Fig. 3 institute
Show, can wrap between the second electrode 140 and third electrode 110 containing insulation filler.Guaranteed by insulation filler
Without short circuit between second electrode 140 and third electrode 110.
It as Figure 2-3, is 100 structural schematic diagram of another chip provided in an embodiment of the present invention.The chip 100 wraps
4 third electrodes 110 are included.Second electrode 140 is in " ten " word.Four ends of the second electrode 140 extend respectively into institute
Four boundaries of second surface are stated, and the second surface is divided into four regions by the second electrode 140.The third electricity
Pole 110 is respectively distributed in 4 regions.And the second electrode 140 is spaced at a distance from setting between third electrode 110
Or it is separated by insulating materials.A kind of preferred embodiment, 4 third electrodes 110 are symmetric.
The embodiment of the invention also provides a kind of potted elements, and as illustrated in figures 4-5, the potted element includes above-mentioned reality
Apply any middle chip of example.The chip includes third surface and fourth surface opposite with third surface.The encapsulation
Element further includes having the first conductive layer and the second conductive layer, wherein the third surface of the chip is arranged in the first conductive layer
On.Second conductive layer is arranged on the 4th surface of the chip.
A kind of specific embodiment, first conductive layer and the second conductive layer are respectively conductive heat conducting material, such as
Copper.By this two-sided setting, it is capable of increasing heat dissipation area, improves the performance of chip operation.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although referring to aforementioned reality
Applying example, invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution should all
It is included within protection scope of the present invention.
Claims (10)
1. a kind of chip characterized by comprising
Semiconductor material layer；
First electrode, the first electrode are arranged on the first surface of the semiconductor material layer；
Second electrode, the second electrode are arranged on the semiconductor material layer second surface opposite with first surface；
At least two third electrodes, at least two thirds electrode are arranged on second surface, and at least two third electricity
Pole is distributed in around the second electrode；It is spaced and sets between the first electrode, second electrode and at least two third electrodes
Fixed distance is either filled by insulating materials.
2. chip as described in claim 1, which is characterized in that the first electrode is thermally conductive layer, and described first is electric
Pole covers the region of 80% or more the semiconductor material layer first surface.
3. chip as described in claim 1, which is characterized in that the second electrode and at least two third electrodes are conduction
Heat-conducting layer, and the second electrode and at least two third electrodes integrally cover the semiconductor material layer second surface 80%
Above region.
4. chip as described in claim 1, which is characterized in that the chip includes two third electrodes, and described two the
Three distribution of electrodes are in the second electrode two sides.
5. chip as claimed in claim 4, which is characterized in that described two third electrodes are symmetricly set on the second electrode
Two sides.
6. chip as claimed in claim 5, which is characterized in that the second electrode is arranged in the semiconductor material layer frame
Central axes on, and at least two thirds electrode is made to be symmetricly set on the second electrode two sides.
7. chip as described in claim 1, which is characterized in that the chip includes 4 third electrodes, and 4 thirds
Electrode is separated by the second electrode.
8. chip as claimed in claim 7, which is characterized in that 4 third electrodes are symmetrical relative to second electrode.
9. chip as claimed in claim 8, which is characterized in that the second electrode is in " ten " word, and the second electrode includes
There are four end, four ends extend respectively into the boundary of the second surface, and the second electrode is relative to described the
The transverse and longitudinal axis on two surfaces is symmetrical, and 4 third electrodes are symmetrical relative to the second electrode.
10. a kind of potted element, which is characterized in that including any chip described in claim 1-9, the first conductive layer and
Two conductive layers；
Wherein first conductive layer is arranged on the third surface of the chip；
Second conductive layer is arranged on the 4th surface of the chip, wherein the third surface is opposite with the 4th surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910636804.3A CN110310931A (en) | 2019-07-15 | 2019-07-15 | A kind of chip and potted element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910636804.3A CN110310931A (en) | 2019-07-15 | 2019-07-15 | A kind of chip and potted element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110310931A true CN110310931A (en) | 2019-10-08 |
Family
ID=68081365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910636804.3A Pending CN110310931A (en) | 2019-07-15 | 2019-07-15 | A kind of chip and potted element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110310931A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508922A (en) * | 2020-04-26 | 2020-08-07 | 深圳市昭矽微电子科技有限公司 | MOSFET chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101080816A (en) * | 2004-12-31 | 2007-11-28 | 万国半导体股份有限公司 | Flip chip contact(PCC) power package |
| CN101904004A (en) * | 2008-01-31 | 2010-12-01 | 万国半导体有限公司 | Wafer level chip scale package and process of manufacture |
| CN102569099A (en) * | 2010-12-28 | 2012-07-11 | 万国半导体(开曼)股份有限公司 | Packaging method of flip chip |
| CN104347431A (en) * | 2013-07-23 | 2015-02-11 | 万国半导体股份有限公司 | Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure |
| CN105489571A (en) * | 2014-09-15 | 2016-04-13 | 万国半导体(开曼)股份有限公司 | Semiconductor package with cooling fin, and packaging method for semiconductor package |
| CN106711100A (en) * | 2016-08-22 | 2017-05-24 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure and processing method |
| CN107240571A (en) * | 2017-05-10 | 2017-10-10 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, includes the submodule group and compression joint type package module of the chip |
-
2019
- 2019-07-15 CN CN201910636804.3A patent/CN110310931A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101080816A (en) * | 2004-12-31 | 2007-11-28 | 万国半导体股份有限公司 | Flip chip contact(PCC) power package |
| CN101904004A (en) * | 2008-01-31 | 2010-12-01 | 万国半导体有限公司 | Wafer level chip scale package and process of manufacture |
| CN102569099A (en) * | 2010-12-28 | 2012-07-11 | 万国半导体(开曼)股份有限公司 | Packaging method of flip chip |
| CN104347431A (en) * | 2013-07-23 | 2015-02-11 | 万国半导体股份有限公司 | Packaging structure exposing top surface and bottom surface of device and method for manufacturing the packaging structure |
| CN105489571A (en) * | 2014-09-15 | 2016-04-13 | 万国半导体(开曼)股份有限公司 | Semiconductor package with cooling fin, and packaging method for semiconductor package |
| CN106711100A (en) * | 2016-08-22 | 2017-05-24 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure and processing method |
| CN107240571A (en) * | 2017-05-10 | 2017-10-10 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, includes the submodule group and compression joint type package module of the chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508922A (en) * | 2020-04-26 | 2020-08-07 | 深圳市昭矽微电子科技有限公司 | MOSFET chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10748878B2 (en) | Semiconductor device assembly with heat transfer structure formed from semiconductor material | |
| US7859846B2 (en) | Low thermal resistance power module assembly | |
| CN102315181B (en) | Semiconductor device | |
| US20150348956A1 (en) | Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods | |
| US9412679B1 (en) | Power semiconductor device | |
| US11387159B2 (en) | Chip package | |
| EP3157053B1 (en) | Power module | |
| US9000580B2 (en) | Power semiconductor module with pressed baseplate and method for producing a power semiconductor module with pressed baseplate | |
| EP2889902B1 (en) | Electric power semiconductor device | |
| TW201036121A (en) | Semiconductor device having a diamond substrate heat spreader | |
| CN105632947A (en) | Semiconductor device packaging structure and manufacturing method thereof | |
| CN109196637B (en) | Semiconductor device with a plurality of semiconductor chips | |
| JP4146888B2 (en) | Semiconductor module and method for manufacturing semiconductor module | |
| JP2004006603A (en) | Semiconductor power device | |
| CN110310931A (en) | A kind of chip and potted element | |
| CN106783753A (en) | Semiconductor devices | |
| US5038198A (en) | Modular semiconductor power device | |
| CN110676232B (en) | Semiconductor device packaging structure, manufacturing method thereof and electronic equipment | |
| US8026580B2 (en) | Semiconductor device package with integrated heat spreader | |
| CN112530915A (en) | Semiconductor device with a plurality of semiconductor chips | |
| EP3297022B1 (en) | Top side cooling for gan power device | |
| CN209708964U (en) | Power module and electronic equipment | |
| JP2012238737A (en) | Semiconductor module and manufacturing method therefor | |
| US3828229A (en) | Leadless semiconductor device for high power use | |
| CN204792767U (en) | Diode power module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20191008 |