CN105575301B - Signal line detection method of array substrate - Google Patents
Signal line detection method of array substrate Download PDFInfo
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- CN105575301B CN105575301B CN201510958046.9A CN201510958046A CN105575301B CN 105575301 B CN105575301 B CN 105575301B CN 201510958046 A CN201510958046 A CN 201510958046A CN 105575301 B CN105575301 B CN 105575301B
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000001514 detection method Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 claims description 12
- 230000000737 periodic effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 19
- 238000007689 inspection Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The application discloses an array substrate, a signal line detection method, a display panel and a display device. The array substrate comprises a plurality of signal lines and a detection circuit, wherein the detection circuit comprises a control circuit, a plurality of transistors, a plurality of test lines and a plurality of receiving lines; each test line is respectively connected with one end of at least one signal line; the first pole of each transistor is respectively connected with the other end of one signal wire, the grid electrode is respectively connected with one output end of the control circuit, and the second pole of each transistor is respectively connected with one receiving wire corresponding to the signal wire. Different test signals are applied to the signal wires in the array substrate, and the corresponding relation between the received signals and the test signals is tested, so that the detection of short circuit and open circuit of the wiring of the array substrate can be realized, the detection cost is reduced, and the detection precision of the array substrate is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a signal line detection method, a display panel and a display device.
Background
In the conventional display panel manufacturing process, the manufactured array substrate needs to be cut. When cutting, the electrodes on the array substrate may be scratched, which may cause short circuit or open circuit of the signal lines, and thus the display panel may not perform signal conversion and display normally. Therefore, the signal lines of the cut array substrate need to be detected to ensure that the display panel displays normally.
The current detection method mainly comprises the following steps: one is to provide a special detection area on the array substrate and detect whether the gate line or the data line is open-circuited by a detection circuit. The scheme occupies a part of typesetting space and increases the area of the array substrate. The second method is to perform the test by simultaneously inserting needles at both ends of the gate lines or the data lines by a probe card. This solution has high requirements on the size and quality of the probe and high costs. In another method, a sensor is used to detect whether a pulse signal is present on a gate line or a data line. However, this solution is suitable for a display panel with a large pixel unit size, and when the pixel unit size is small, this solution cannot detect a short circuit or an open circuit of the signal line.
Disclosure of Invention
In view of the above, it is desirable to provide a signal line detection method for an array substrate with low detection cost and high accuracy. Further, it is also desirable to provide a detection method that can save layout space. To address one or more of the problems set forth above. The application provides an array substrate, a signal line detection method, a display panel and a display device.
In a first aspect, the present application provides an array substrate, including a plurality of signal lines and a detection circuit, where the detection circuit includes a control circuit, a plurality of transistors, a plurality of test lines, and a plurality of receiving lines; each test line is respectively connected with one end of at least one signal line; the first pole of each transistor is respectively connected with the other end of one signal wire, the grid electrode is respectively connected with one output end of the control circuit, and the second pole of each transistor is respectively connected with one receiving wire corresponding to the signal wire.
In some optional implementations, the signal line includes: a first grid line group consisting of all the grid lines in the odd rows and a second grid line group consisting of all the grid lines in the even rows; and/or a first data line group consisting of data lines of all odd columns and a second data line group consisting of data lines of all even columns.
In some alternative implementations, the control circuit includes a plurality of cascaded shift registers.
In a second aspect, the present application provides a signal line inspection method for an array substrate, for inspecting the array substrate provided in the first aspect of the present application, the method including: applying a plurality of test signals to the plurality of signal lines through the test lines, respectively; applying an enable signal to a control circuit; gradually conducting the transistor corresponding to each signal line; a signal is received over the receive line.
In some alternative implementations, the enable signal is a high level signal.
In some optional implementations, the signal line includes: a first grid line group consisting of all the grid lines in the odd rows and a second grid line group consisting of all the grid lines in the even rows; and/or a first data line group consisting of data lines of all odd columns and a second data line group consisting of data lines of all even columns.
In a further implementation, a periodic first gate line test signal is applied to the first gate line group, and a second gate line test signal delayed by a quarter of a period from the first gate line test signal is applied to the second gate line group; and/or applying a periodic first data line test signal to the first data line group and applying a second data line test signal having a delay of one-quarter period with the first data line test signal to the second data line group.
In a further implementation, each transistor is turned on for a time that is one-quarter of the period of the test signal.
In some optional implementations, the signal received by the receiving line is inconsistent with the test signal applied to the signal line connected to the receiving line, and it is determined that the signal line is shorted or open.
In a further implementation, the first gate line test signal and/or the first data line test signal is a square wave signal.
In a further implementation manner, the signal received by the receiving line is not turned over in a certain time sequence position in accordance with the corresponding test signal, and the signal line corresponding to the time sequence position is determined to be broken; the amplitude of the signal received by the receiving line at a certain time sequence position is half of the amplitude of the test signal, and the signal line corresponding to the time sequence position is determined to be in short circuit with the next signal line.
In a third aspect, the present application provides a display panel including the array substrate provided above.
In a fourth aspect, the present application provides a display device comprising the display panel provided above.
According to the array substrate, the signal line detection method, the display panel and the display device, different test signals are applied to the signal lines in the array substrate, the relative relation of the received signals is tested, the detection of short circuit and open circuit of the array substrate wiring is achieved, the detection cost is reduced, and the detection precision is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an array substrate according to another embodiment of the present application;
fig. 3 is a schematic view illustrating a signal line inspection method of an array substrate according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an array substrate in which odd-numbered gate lines and even-numbered gate lines are connected to different test lines according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a signal detected by a gate line of the array substrate of the embodiment shown in fig. 4;
fig. 6 is a schematic signal diagram illustrating disconnection of the first and sixth gate lines during detection of the gate lines of the array substrate shown in fig. 4;
fig. 7 is a schematic signal diagram illustrating a first gate line and a second gate line being shorted during the gate line detection of the array substrate shown in fig. 4;
FIG. 8 is a schematic structural diagram of an array substrate with odd and even column data lines connected to different test lines according to an embodiment of the present disclosure;
fig. 9 is a schematic structural view of still another array substrate according to an embodiment of the present application;
fig. 10 is a schematic diagram of a signal detected by a gate line of the array substrate of the embodiment shown in fig. 9.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
Referring to fig. 1, a schematic structural diagram of an array substrate according to an embodiment of the present application is shown. As shown in fig. 1, in the present embodiment, the array substrate may include a plurality of signal lines and a detection circuit, and the detection circuit may include a control circuit 13, a plurality of transistors 14, a plurality of test lines 11, and a plurality of receiving lines 12. Wherein the signal lines may include gate lines G1, G2, G3, … Gn, and data lines S1, S2, S3, … Sm, where n and m are positive integers. As shown in fig. 1, each of the test lines 11 is connected to one end of at least one gate line Gi (where i ═ 1,2,3, … n) as a signal line, and the other end of the gate line Gi is connected to the first electrode of one transistor 14. The gate of transistor 14 is connected to an output of the control circuit and the second pole of transistor 14 is connected to a receive line 12 corresponding to Gi.
The array substrate shown in fig. 1 includes two test lines 111 and 112 and two receiving lines 121 and 122 corresponding to the test lines. One end of a part of the gate lines is connected to the test line 111, and the other end is connected to the receiving line 121 through a transistor. One end of the other part of the gate line is connected to the test line 112, and the other end is connected to the receiving line 122 through the transistor. The transistor 14 is controlled to be turned on or off by the control circuit 13. The control circuit 13 may include a plurality of cascaded shift registers, each of which is connected to a gate of one of the transistors, and each of the transistors is sequentially controlled to be turned on by the output shift signal.
Referring to fig. 2, a schematic structural diagram of an array substrate according to another embodiment of the present application is shown. As shown in fig. 2, in the present embodiment, the array substrate may include a plurality of signal lines and a detection circuit, and the detection circuit may include a control circuit 23, a plurality of transistors 24, a plurality of test lines 21, and a plurality of receiving lines 22. Wherein the signal lines may include gate lines G1, G2, G3, … Gn, and data lines S1, S2, S3, … Sm, where n and m are positive integers. As shown in fig. 2, each of the test lines 21 is connected to one end of at least one data line Si (where i ═ 1,2,3, … n) as a signal line, and the other end of the data line Si is connected to the first pole of one of the transistors 24. A gate of the transistor 24 is connected to an output terminal of the control circuit, and a second pole of the transistor 24 is connected to one of the receiving lines 22 corresponding to the data line Si.
The array substrate shown in fig. 2 includes two test lines 211 and 212 and two receiving lines 221 and 222 corresponding to the test lines. One end of the partial data line is connected to the test line 211, and the other end is connected to the receiving line 221 through a transistor. One end of the other part of the data line is connected to the test line 212, and the other end is connected to the receiving line 222 via a transistor. The transistor 24 is controlled to be turned on or off by the control circuit 23. The control circuit 23 may include a plurality of cascaded shift registers, each of which is connected to a gate of a transistor, and sequentially scans each data line by controlling on or off of the transistor.
As can be seen from fig. 2, unlike the embodiment shown in fig. 1, the data lines in fig. 2 are signal lines, and the data lines can be scanned by applying an enable signal to the control circuit.
Further referring to fig. 3, a schematic diagram of a signal line detection method of an array substrate according to an embodiment of the present application is shown.
As shown in fig. 3, in step 301, a plurality of test signals are applied to a plurality of signal lines through test lines, respectively.
In this embodiment, each test line may be connected to a plurality of signal lines, and different test signals may be applied to different test lines, for example, different types of signals such as a sinusoidal signal, a square wave signal, and a pulse signal may be applied to different test lines, different types of signals with different periods may be applied to different test lines, and opposite-phase signals with the same type and the same period may be applied to different test lines.
In step 302, an enable signal is applied to the control circuit.
In this embodiment, scanning of the signal lines can be realized by the control circuit. In the embodiment as shown in fig. 1, the first stage shift register may be controlled to input a high level signal by applying an enable signal to the control circuit, and the transistor connected to the first gate line G1 is turned on, thereby transferring the test signal input to the first gate line G1 to the corresponding output line. In the embodiment shown in fig. 2, similarly to the embodiment shown in fig. 1, the first stage shift register may be controlled to output a high level signal by applying an enable signal to the control circuit, and the transistor 24 connected to the first data line S1 is turned on, so that the test signal input to the first data line S1 is transferred to the corresponding receiving line. Alternatively, the enable signal may be a high level signal.
In step 303, the transistors corresponding to each signal line are turned on step by step.
The first stage shift register in the control circuit can apply a starting signal to the second stage shift register after a preset time, and a transistor connected with the second grid line is conducted; meanwhile, the second-stage shift register can return a stop signal to the first-stage shift register, so that the first-stage shift register outputs a low-level signal and switches off the transistor connected with the first grid line. The control circuit gradually turns on the transistor corresponding to each grid line or data line according to the signal transmission rule, turns off the transistor corresponding to the previous grid line or data line, and then gradually turns on each grid line or data line according to the signal transmission rule, and turns off the previous grid line or data line. The last grid line or data line can be controlled to be disconnected by a stop signal applied to the control circuit, so that the row-by-row or column-by-column scanning of the array substrate is completed.
In step 304, a signal is received over a receive line.
In this embodiment, a signal transmitted through the gate line or the data line may be received through the receiving line. Then, whether the signal line is short-circuited or open-circuited can be determined based on a relationship between the received signal and the test signal applied to the signal line.
It should be noted that, although the steps of the signal line detection method of the array substrate are described in a specific order in fig. 3, in practical applications, the above steps may be performed in a different order according to actual situations, or multiple steps in fig. 3 may be performed simultaneously, for example, steps 301 and 302 may be performed simultaneously.
In some embodiments, the signal lines may include a first gate line group consisting of all the gate lines of the odd-numbered rows and a second gate line group consisting of all the gate lines of the even-numbered rows. Further referring to fig. 4, a schematic structural diagram of the array substrate in which odd-numbered rows of gate lines and even-numbered rows of gate lines are connected to different test lines according to an embodiment of the present application is shown.
As shown in fig. 4, in the present embodiment, one end of the first gate line group composed of all the odd-numbered gate lines is connected to the test line 411, and the other end is connected to the first electrode of the transistor 14. The second pole of transistor 14 is connected to receive line 421 corresponding to test line 411. A first gate line group consisting of all even-numbered rows of gate lines has one end connected to the test line 412 and the other end connected to the first electrode of the transistor 14. The second pole of each transistor 14 is connected to a receive line 422 corresponding to the test line 412, and the gate is connected to the control circuit 13. The control circuit 13 may control the transistors connected to the gate lines to be turned on in sequence. Thus, a test signal applied to the signal line through the test line is transmitted to the receive line terminal through the gate line, the receive line 421 can receive the test signal input through the test line 411, and the receive line 422 can receive the test signal input through the test line 412.
For the array substrate in the embodiment shown in fig. 4, the signal lines thereof can be detected by the method shown in fig. 3. And applying a start signal Stv to the control circuit 13, turning on the transistor corresponding to each gate line step by step to scan the gate lines, and after the last gate line is scanned, applying a stop signal Rst to the control circuit 13 to complete the line scanning of the array substrate. When the signal received by the receiving line 421 is inconsistent with the test signal input through the test line 411, it can be determined that the gate lines in the first gate line group are short-circuited or open-circuited. Further, if the test signal is a periodic signal, the position of the gate line where the short circuit or the open circuit occurs may be determined according to the timing position where the inconsistency occurs. Accordingly, when the signal received by the receiving line 422 is not identical to the test signal input through the test line 412, it may be determined that the gate lines in the second gate line group are short-circuited or open-circuited. Further, if the test signal is a periodic signal, the position of the gate line where the short circuit or the open circuit occurs may be determined according to the timing position where the inconsistency occurs.
Fig. 5 is a schematic diagram illustrating a signal detected by the gate line of the array substrate of the embodiment shown in fig. 4. As shown in fig. 5, a first test signal TG1 and a second test signal TG2 are applied to a first gate line group consisting of all odd-numbered row gate lines and a second gate line group consisting of all even-numbered row gate lines through test lines 411 and 412, respectively. The first test signal TG1 and the second test signal TG2 are both square wave signals, and the TG2 has a quarter-cycle delay with respect to the TG 1. In fig. 5, the time when the timing signal G1, G2, G3, G4, and G … of each gate line is at a high level indicates the turn-on time of the corresponding transistor. Fig. 5 is a schematic diagram showing the received signal and the input signal when all the gate lines are not short-circuited or open-circuited. As can be seen from fig. 5, when the gate line is not short-circuited or open-circuited, the received signal RG1 of the first signal line group and the test signal TG1 have the same polarity and the same amplitude at the same timing position; the received signal RG2 of the second signal line group has the same polarity and the same amplitude as the test signal TG2 at the same timing position.
When the test signals TG1 and TG2 shown in fig. 5 are applied to the array substrate shown in fig. 4 and the control circuit is controlled to turn on the transistors in sequence by the timing signals shown in fig. 5, if the received signals are identical to the test signals, it can be determined that the gate lines in the array substrate shown in fig. 4 are not short-circuited or open-circuited.
Fig. 6 shows a signal diagram of the first and sixth gate lines being broken during the gate line detection of the array substrate of the embodiment shown in fig. 4. As shown in fig. 6, the test signals input to the two groups of gate lines are periodic square wave signals, and there is a quarter period of delay between the two test signals TG1 and TG 2. The turn-on time of the corresponding transistor is represented by the time when the timing signals G1, G2, G3, G4, … of each gate line are at a high level. The time for which the transistor corresponding to each grid line is conducted is one fourth of the period of the square wave signal. If the first gate line G1 is open, the first receiving line cannot receive a high signal applied to G1 when the transistor corresponding to G1 is turned on, and thus outputs a low signal. If the sixth gate line G6 is open, the second receiving line cannot receive the high signal applied to G6 when the transistor corresponding to G6 is turned on, and thus outputs a low signal. In fig. 6, the RG1 does not flip at the timing position corresponding to G1 in accordance with the TG1, and the RG2 does not flip at the timing position corresponding to G6 in accordance with the TG 2. If the G3 were to break, the RG1 received signal at G3 would maintain the polarity of the previous row, i.e., a high signal (not shown in fig. 6). Comparing the signal received by the receiving line under the normal condition of the gate line (fig. 5), it can be seen that if the gate line is open, the receiving line cannot be turned over in the corresponding time sequence position of the gate line in accordance with the test signal. Whether the gate line is open can be determined according to the following method: and if the signal received by the receiving line is not inverted in a certain time sequence position and is consistent with the corresponding test signal, determining that the grid line corresponding to the time sequence position is disconnected.
Referring further to fig. 7, a signal diagram illustrating a first gate line and a second gate line being shorted when detecting the gate lines of the array substrate shown in fig. 4 is shown. As shown in fig. 7, when the first gate line G1 and the second gate line G2 are shorted, the receiving line 421 receives the test signal TG1 and the test signal TG2 at the same time at the timing position where G1 is turned on, where TG1 is a high-level signal and TG2 is a low-level signal. Therefore, the signal RG1 received by the reception line 421 is at the middle level at the timing position corresponding to G1, i.e., the amplitude of the signal received at the timing position of RG1 is half of the amplitude of the test signal TG 1. When the transistor corresponding to G2 is turned on, both TG1 and TG2 are high level signals, and therefore, the signal RG2 received by the reception line 422 is high level at the timing position corresponding to G2. Therefore, if the amplitude of the signal received by the receiving line at a certain time sequence position is half of the amplitude of the test signal, it can be determined that the grid line corresponding to the time sequence position is short-circuited with the next grid line.
While the method for detecting the short circuit and the open circuit of the gate line is described above with reference to the array substrate shown in fig. 4, it can be understood that the data lines in the array substrate can also be detected by using the corresponding relationship of the signals shown in fig. 5 to 7.
Referring to fig. 8, a schematic structural diagram of an array substrate with odd and even column data lines connected to different test lines according to an embodiment of the present disclosure is shown. The array substrate shown in fig. 8 may be used to detect whether the data lines are short-circuited or open-circuited. As shown in fig. 8, the array substrate includes a first test line 811, a second test line 812, a first receiving line 821, a second receiving line 822, a control circuit 23, a transistor 24, and a signal line. Here, the signal lines include, in addition to the gate lines G, a first data line group S1, S3, S5, …, S (2M-1) (M is a positive integer, and 2M-1 ═ M or 2M ═ M) composed of data lines of all odd columns. And a second data line group S2, S4, S6, …, S (2M) (M is a positive integer, and 2M-1 ═ M or 2M ═ M) composed of data lines of all even columns.
As shown in fig. 8, one end of each of the first data line groups is connected to a first test line 811, the other end is connected to a first pole of a transistor, the gate of the transistor is connected to the control circuit 23, and the second pole is connected to a receiving line 821 corresponding to the data line group and the test line 811. One end of the second data line group is connected to the second test line 812, the other end is connected to the first electrode of a transistor, the gate of the transistor is connected to the control circuit 23, and the second electrode is connected to the receiving line 822 corresponding to the data line group and the test line 812.
When data line detection is performed, a first data line test signal TS1 and a second data line test signal TS2 may be input through the test lines 811 and 812, respectively, a start signal is applied to the control circuit, the control circuit turns on the transistor corresponding to each data line step by step, and whether the data line is short-circuited or open-circuited is determined by signals RS1 and RS2 received through the receiving lines 821 and 822.
For the array substrate shown in fig. 8, signals similar to those in fig. 5 can also be used for detection. If the signal received by the receiving line 821 or 822 does not flip over in a certain timing position in accordance with the corresponding test signal 811 or 812, it can be determined that the data line corresponding to the timing position is open; if the amplitude of the signal received by the receiving line 821 or 822 at a certain timing position is half of the amplitude of the test signal 811, it can be determined that the data line corresponding to the timing position is short-circuited with the next data line.
In the embodiments described above with reference to fig. 4 and 8, whether the gate line or the data line is short-circuited or disconnected can be determined by the signal received by the receiving line, and the position of the short-circuited or disconnected gate line or data line can be determined based on the timing correspondence between the received signal and the test signal, so that the detection of the signal line of the array substrate is realized without occupying an additional layout space. Compared with the prior art, the array substrate and the detection method thereof provided by the embodiment of the application have the advantages of low detection cost, high speed and high precision, can detect the signal line of the array substrate with the smaller pixel unit size, can detect the signal line after unit test (cell visual test), avoid scratching a panel during cutting, and reduce the omission factor.
It should be noted that the signal lines in the array substrate provided by the present application are not limited to the above grouping by odd-even rows/columns, and the signal lines may be grouped by various methods, and only the corresponding test signal needs to be applied to the signal lines, so that the detection of the signal lines may also be realized. Another grouping embodiment of the signal lines in the array substrate is described below with reference to fig. 9 and 10.
Referring to fig. 9, a schematic structural diagram of another array substrate according to an embodiment of the present application is shown. As shown in fig. 9, the array substrate signal line and the detection circuit include a first test line 911, a second test line 912, a third test line 913, a first receiving line 921, a second receiving line 922, a third receiving line 923, a control circuit 13, and a transistor 14. Wherein, in addition to the data line S, the signal line includes a first gate line group composed of all Gi (i ═ 1,4,7, …, 3i +1, i is a non-negative integer, and 3i +1 ≦ n), a second gate line group composed of all Gj (j ═ 2,5,8, …, 3j +2, j is a non-negative integer, and 3j +2 ≦ n), and a third gate line group composed of all Gk (k ═ 3,6,9, …, 3k +3, k is a non-negative integer, and 3j +3 ≦ n).
As shown in fig. 9, one end of each of the first gate line groups is connected to a first test line 911, the other end is connected to a first pole of each of the transistors, the gates of the transistors are connected to the control circuit 23, and the second pole is connected to a receiving line 921 corresponding to the gate line group and the test line 911. One end of each of the second gate line groups is connected to the second test line 912, the other end of each of the second gate line groups is connected to a first electrode of one of the transistors, the gate electrodes of the transistors are connected to the control circuit 23, and the second electrodes of the transistors are connected to the receiving lines 922 corresponding to the gate line groups and the test line 912. One end of each of the third gate line groups is connected to the third test line 913, the other end is connected to a first electrode of a transistor, a gate electrode of the transistor is connected to the control circuit 23, and a second electrode is connected to the receiving line 923 corresponding to the gate line group and the test line 913.
When data line detection is performed, a first gate line test signal TG1, a second gate line test signal TG2 and a third gate line test signal TG3 can be respectively input through test lines 911, 912 and 913, a start signal is applied to a control circuit, a transistor corresponding to each gate line is turned on step by step through the control circuit, and whether the gate lines are short-circuited or open-circuited is judged through signals RG1, RG2 and RG3 received through receiving lines 921, 922 and 923.
Referring further to fig. 10, a schematic diagram of a signal detected by the gate line of the array substrate of the embodiment shown in fig. 9 is shown. Wherein G1, G2, G3, G4, G5, G6 … respectively represent signals applied to each gate line, RG1, RG2, RG3 respectively receive signals received by lines 921, 922, 923 when the first gate line G1 and the eighth gate line G8 are open, RG1 ' receives a signal received by line 921 when the first gate line G1 and the second gate line G2 are short, RG2 ' receives a signal received by line 922 when the second gate line G2 and the third gate line G3 are short, and RG3 ' receives a signal received by line 923 when the third gate line G3 and the fourth gate line G4 are short. As shown in fig. 10, square wave signals TG1, TG2 and TG3 are used as input signals, TG2 and TG1 have a one-sixth period delay, and TG3 and TG1 have a one-third period delay. When a certain grid line is broken, the signal received by the corresponding receiving line at the time sequence position corresponding to the grid line is not turned over in accordance with the test signal; when two adjacent grid lines are short-circuited, the amplitude of the signal received by the corresponding receiving line at the time sequence position corresponding to the grid line is one half of the amplitude of the test signal. Therefore, whether the grid line is short-circuited or broken can be judged according to whether the received signal is overturned or not and whether the amplitude is changed or not, and the position of the grid line with the short circuit or the broken circuit is determined according to the time sequence position of the received signal inconsistent with the test signal.
The method for inspecting the array substrate in the embodiment of fig. 9 is described above with reference to fig. 10. Similarly, the data lines may also be grouped in a similar manner to the gate lines in fig. 9, and the detection of a short or open of the data lines may be performed using a test signal similar or identical to that of fig. 10.
In the above embodiments, the test signal is taken as a square wave signal as an example, and the detection method of the array substrate is described. It will be appreciated that in practice, many different forms of signal may be used as the test signal, such as a sinusoidal signal, a periodic pulsed signal, etc. During detection, if the signal received by the receiving line is inconsistent with the corresponding test signal, the detected signal line can be determined to be short-circuited or open-circuited. Furthermore, the time of applying high level to the transistor by each level of the shift register can be controlled by the control circuit, and the control circuit is matched with the test signal to determine the position of the signal line with short circuit or open circuit, so that the accurate detection of the wiring of the array substrate is realized.
The present application further provides a display panel including the array substrate described in the above embodiments.
The present application also provides a display including the display panel described in the above embodiments.
It should be noted that the first pole of the transistor described in the above embodiments may be one of a source and a drain of the transistor, and the second pole of the transistor may be the other of the source and the drain of the transistor. If the source electrode of the transistor is the first electrode, the drain electrode of the transistor is the second electrode; if the drain of the transistor is said first pole, the source of the transistor is said second pole. This is not a limitation of the present application.
According to the array substrate, the signal line detection method, the display panel and the display device provided by the embodiment of the application, the test lines and the receiving lines are arranged in the array substrate, different test signals are applied to the signal lines in the array substrate, and the relative relation of the received signals is tested, so that the detection of short circuit and open circuit of the array substrate wiring is realized, the detection cost is reduced, and the detection precision is improved.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (2)
1. A signal line detection method of an array substrate comprises a plurality of signal lines and a detection circuit, wherein the detection circuit comprises a control circuit, a plurality of transistors, a plurality of test lines and a plurality of receiving lines; the control circuit comprises a plurality of cascaded shift registers; each test line is respectively connected with one end of at least one signal line; the first pole of each transistor is respectively connected with the other end of one signal wire, the grid electrode of each transistor is respectively connected with one output end of the control circuit, and the second pole of each transistor is respectively connected with one receiving wire corresponding to the signal wire;
the signal line includes:
a first grid line group consisting of all the grid lines in the odd rows and a second grid line group consisting of all the grid lines in the even rows; and/or
A first data line group consisting of data lines of all odd columns and a second data line group consisting of data lines of all even columns; wherein,
one end of the first gate line group or the first data line group is electrically connected with one test line, and a second pole of each transistor electrically connected with the other end of the first gate line group or the other end of the first data line group is connected with one receiving line corresponding to the one test line; one end of the second gate line group or the second data line group is electrically connected to another test line, and a second pole of each transistor electrically connected to the other end of the second gate line group or the second data line group is connected to another receiving line corresponding to the another test line;
the method comprises the following steps:
applying a plurality of test signals to the plurality of signal lines through the test lines, respectively;
applying an enable signal to a control circuit;
gradually conducting the transistor corresponding to each signal line;
receiving a signal through the receive line;
applying a periodic first gate line test signal to the first gate line group, and applying a second gate line test signal having a delay of one-quarter period with the first gate line test signal to the second gate line group; and/or
Applying a periodic first data line test signal to the first data line group and applying a second data line test signal having a delay of one-quarter period from the first data line test signal to the second data line group;
the first grid line test signal and/or the first data line test signal are square wave signals;
each transistor is turned on for a time of one quarter of a period of the test signal;
the signal received by the receiving line is not turned over in a certain time sequence position consistent with the corresponding test signal, and the signal line corresponding to the time sequence position is determined to be broken;
the amplitude of the signal received by the receiving line at a certain time sequence position is half of the amplitude of the test signal, and the signal line corresponding to the time sequence position is determined to be in short circuit with the next signal line.
2. The method of claim 1, wherein the start signal is a high signal.
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| CN201510958046.9A CN105575301B (en) | 2015-12-18 | 2015-12-18 | Signal line detection method of array substrate |
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