CN105575301A - Array substrate, signal line detection method, display panel and display device - Google Patents
Array substrate, signal line detection method, display panel and display device Download PDFInfo
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- CN105575301A CN105575301A CN201510958046.9A CN201510958046A CN105575301A CN 105575301 A CN105575301 A CN 105575301A CN 201510958046 A CN201510958046 A CN 201510958046A CN 105575301 A CN105575301 A CN 105575301A
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- 239000000758 substrate Substances 0.000 title abstract 6
- 238000012360 testing method Methods 0.000 claims abstract description 96
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The application discloses an array substrate, a signal line detection method, a display panel and a display device. The array substrate comprises a plurality of signal lines and a detection circuit, wherein the detection circuit comprises a control circuit, a plurality of transistors, a plurality of test lines and a plurality of receiving lines; each test line is respectively connected with one end of at least one signal line; the first pole of each transistor is respectively connected with the other end of one signal wire, the grid electrode is respectively connected with one output end of the control circuit, and the second pole of each transistor is respectively connected with one receiving wire corresponding to the signal wire. Different test signals are applied to the signal wires in the array substrate, and the corresponding relation between the received signals and the test signals is tested, so that the detection of short circuit and open circuit of the wiring of the array substrate can be realized, the detection cost is reduced, and the detection precision of the array substrate is improved.
Description
Technical field
The application relates to display technique field, is specifically related to a kind of array base palte, signal wire detection method, display panel and display device.
Background technology
In traditional display panel manufacturing process, the array base palte to making is needed to cut.The electrode on array base palte may be caused during cutting to scratch, cause signal wire short circuit or open circuit, make display panel normally cannot carry out signal conversion and display.Therefore, the array base palte after to cutting is needed to carry out the detection of signal wire, to ensure that display panel normally shows.
Current detection method mainly comprises following several: a kind of is on array base palte, arrange special surveyed area, detects the whether open circuit of grid line or data line by testing circuit.This scheme occupies a part of typesetting space, adds the area of array base palte.Simultaneously second method adopts probe card to have an acupuncture treatment at the two ends of grid line or data line to detect.This scheme to the size of probe and quality requirements higher, cost is larger.In another approach, inductor is adopted to detect on grid line or data line whether have pulse signal.But this scheme is applicable to the larger display panel of pixel cell size, when the size of pixel cell is less, this scheme cannot realize the detection of signal wire short circuit or open circuit.
Summary of the invention
In view of this, the signal wire detection method of a kind of testing cost is low, precision is high array base palte is provided to provide.Further, also expect that the detection method provided can save typesetting space.In order to solve above-mentioned one or more problem.This application provides array base palte, signal wire detection method, display panel and display device.
First aspect, this application provides a kind of array base palte, comprises many signal line and testing circuit, and described testing circuit comprises control circuit, multiple transistor many p-wires and many reception lines; Each p-wire is connected with one end of at least one signal wire respectively; First pole of each transistor is connected with the other end of a signal line respectively, and grid is connected with an output terminal of control circuit respectively, and the second pole receives line with one that corresponds to signal wire respectively and is connected.
In some optional implementations, above-mentioned signal wire comprises: the first grid line group be made up of the grid line of all odd-numbered lines and the second grid line group be made up of the grid line of all even number lines; And/or the first data line group to be made up of the data line of all odd columns and the second data line group be made up of the data line of all even columns.
In some optional implementations, control circuit comprises the shift register of multiple cascade.
Second aspect, this application provides a kind of signal wire detection method of array base palte, for detect as the application's first aspect the array base palte that provides, method comprises: apply multiple test signal by p-wire respectively to multiple signal wire; Enabling signal is applied to control circuit; The transistor that each signal line of conducting is corresponding step by step; By described reception line Received signal strength.
In some optional implementations, enabling signal is high level signal.
In some optional implementations, above-mentioned signal wire comprises: the first grid line group be made up of the grid line of all odd-numbered lines and the second grid line group be made up of the grid line of all even number lines; And/or the first data line group to be made up of the data line of all odd columns and the second data line group be made up of the data line of all even columns.
In further implementation, apply periodic first grid line test signal to the first grid line group, apply the second grid line test signal with the first grid line test signal with the time delay in 1/4th cycles to the second grid line group; And/or apply periodic first data line test signal to the first data line group, apply the second data line test signal with the first data line test signal with the time delay in 1/4th cycles to the second data line group.
In further implementation, the time of each transistor turns is 1/4th of the cycle of test signal.
In some optional implementations, receiving the signal that receives of line inconsistent with the test signal be applied to receiving on signal wire that line is connected, determining that signal wire is short-circuited or open circuit.
In further implementation, the first grid line test signal and/or described first data line test signal are square-wave signal.
In further implementation, there is not the upset consistent with corresponding test signal at a certain timing position in the signal that reception line receives, determines the signal wire generation open circuit that this timing position is corresponding; The signal that reception line receives is 1/2nd of test signal amplitude in the amplitude of a certain timing position, determines that the signal wire that this timing position is corresponding and next signal line are short-circuited.
The third aspect, this application provides a kind of display panel, comprises above-mentioned provided array base palte.
Fourth aspect, this application provides a kind of display device, comprises above-mentioned provided display panel.
The array base palte that the application provides, signal wire detection method, display panel and display device, by applying different test signals to the signal wire in array base palte, the relativeness of test Received signal strength, achieve the detection of the short circuit of array base palte cabling, open circuit, reduce testing cost, improve accuracy of detection.
Accompanying drawing explanation
That is done with reference to the following drawings by reading is described in detail non-limiting example, and the other features, objects and advantages of the application will become more obvious:
Fig. 1 is the structural representation of the array base palte according to the application's embodiment;
Fig. 2 is the structural representation of the array base palte according to another embodiment of the application;
Fig. 3 is the schematic diagram of the signal wire detection method of array base palte according to the application's embodiment;
Fig. 4 is the structural representation of the array base palte being connected different p-wire according to the odd-numbered line grid line of the embodiment of the present application with even number line grid line;
Fig. 5 is the schematic diagram of a kind of signal of the grid line detection of array base palte embodiment illustrated in fig. 4;
Fig. 6 is a kind of signal schematic representation of the grid line of array base palte embodiment illustrated in fig. 4 Article 1 and open circuit of Article 6 grid line when detecting;
Fig. 7 is a kind of signal schematic representation of the grid line of array base palte embodiment illustrated in fig. 4 Article 1 grid line and short circuit of Article 2 grid line when detecting;
Fig. 8 is the structural representation of the array base palte being connected different p-wire according to the odd column data line of the embodiment of the present application with even column data line;
Fig. 9 is the structural representation of another array base palte according to the embodiment of the present application;
Figure 10 is the schematic diagram of a kind of signal of the grid line detection of array base palte embodiment illustrated in fig. 9.
Embodiment
Below in conjunction with drawings and Examples, the application is described in further detail.Be understandable that, specific embodiment described herein is only for explaining related invention, but not the restriction to this invention.It also should be noted that, for convenience of description, in accompanying drawing, illustrate only the part relevant to Invention.
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
Please refer to Fig. 1, it illustrates the structural representation of the array base palte according to the application's embodiment.As shown in Figure 1, in the present embodiment, array base palte can comprise many signal line and testing circuit, and testing circuit can comprise control circuit 13, multiple transistor 14, many p-wires 11 and many reception lines 12.Wherein signal wire can comprise grid line G1, G2, G3 ... Gn and data line S1, S2, S3 ... Sm, wherein n, m are positive integer.As shown in Figure 1, each p-wire 11 respectively with at least one as one end of the grid line Gi of signal wire be connected (wherein i=1,2,3 ... n), the other end of grid line Gi is connected with the first pole of a transistor 14.The grid of transistor 14 is connected with control circuit output terminal, and the second pole of transistor 14 receives line 12 be connected with one that corresponds to Gi.
Array base palte shown in Fig. 1 comprises two p-wires 111,112 and two reception line 121,122 corresponding with p-wire.One end of part grid line is connected with p-wire 111, and the other end receives line 121 by transistor AND gate and connects.One end of another part grid line is connected with p-wire 112, and the other end receives line 122 by transistor AND gate and connects.Transistor 14 is controlled to be turned on or off by control circuit 13.Control circuit 13 can comprise the shift register of multiple cascade, and every one-level shift register is connected with the grid of a transistor, controls each transistor turns successively by the shift signal exported.
Please refer to Fig. 2, it illustrates the structural representation of the array base palte according to another embodiment of the application.As shown in Figure 2, in the present embodiment, array base palte can comprise many signal line and testing circuit, and testing circuit can comprise control circuit 23, multiple transistor 24, many p-wires 21 and many reception lines 22.Wherein signal wire can comprise grid line G1, G2, G3 ... Gn and data line S1, S2, S3 ... Sm, wherein n, m are positive integer.As shown in Figure 2, each p-wire 21 respectively with at least one as one end of the data line Si of signal wire be connected (wherein i=1,2,3 ... n), the other end of data line Si is connected with the first pole of a transistor 24.The grid of transistor 24 is connected with control circuit output terminal, and the second pole of transistor 24 receives line 22 be connected with one that corresponds to data line Si.
Array base palte shown in Fig. 2 comprises two p-wires 211,212 and two reception line 221,222 corresponding with p-wire.One end of segment data line is connected with p-wire 211, and the other end receives line 221 by transistor AND gate and connects.One end of another part data line is connected with p-wire 212, and the other end receives line 222 by transistor AND gate and connects.Transistor 24 is controlled to be turned on or off by control circuit 23.Control circuit 23 can comprise the shift register of multiple cascade, and every one-level shift register is connected with the grid of a transistor, scans each data line successively by controlling being turned on or off of transistor.
As can be seen from Figure 2, with embodiment illustrated in fig. 1 unlike, in Fig. 2, data line is as signal wire, can by control circuit apply enabling signal scan data line.
With further reference to Fig. 3, it illustrates the schematic diagram of the signal wire detection method of the array base palte according to the application's embodiment.
As shown in Figure 3, in step 301, multiple test signal is applied by p-wire respectively to multiple signal wire.
In the present embodiment, each p-wire can be connected with multiple signal wire, different test signals can be applied to different p-wire, such as can apply the dissimilar signal such as sinusoidal signal, square-wave signal, pulse signal respectively to different p-wire, also can apply same type cycle different signal respectively to different p-wire, the anti-phase signal of same type same period can also be applied to different p-wire respectively.
In step 302, enabling signal is applied to control circuit.
In the present embodiment, the scanning of signal wire can be realized by control circuit.In the embodiment shown in fig. 1, first order shift register input high level signal can be controlled by applying enabling signal to control circuit, the transistor that conducting is connected with Article 1 grid line G1, thus the test signal of input Article 1 grid line G1 is passed to corresponding output line.In the embodiment shown in Figure 2, similar with the embodiment shown in Fig. 1, first order shift register output high level signal can be controlled by applying enabling signal to control circuit, the transistor 24 that conducting is connected with Article 1 data line S1, thus the test signal of input Article 1 data line S1 is passed to corresponding reception line.Alternatively, enabling signal can be high level signal.
In step 303, the transistor that each signal line of conducting is corresponding step by step.
First order shift register in control circuit can apply enabling signal to second level shift register, the transistor that conducting is connected with Article 2 grid line after the schedule time; Meanwhile, second level shift register can return stop signal to first order shift register, makes first order shift register output low level signal, disconnects the transistor be connected with Article 1 grid line.Control circuit according to above-mentioned signal transmission rule step by step each grid line of conducting or transistor corresponding to data line, disconnect a upper grid line or transistor corresponding to data line, namely can according to above-mentioned signal transmission rule each grid line of conducting or data line, the upper grid line of disconnection or data line step by step.The last item grid line or data line can be controlled by the stop signal being applied to control circuit to disconnect, thus complete array base palte line by line or scan by column.
In step 304, by receiving line Received signal strength.
In the present embodiment, signal through grid line or data line transfer can be received by receiving line.Afterwards, can judge whether signal wire is short-circuited or open circuit according to the relation between the signal received and the test signal applied to signal wire.
It should be noted that, although describe the step of the signal wire detection method of array base palte in Fig. 3 with specific order, but in actual applications, above-mentioned steps can be performed with different orders according to actual conditions, such as, or the multiple steps performed in Fig. 3, step 301 and 302 can perform simultaneously simultaneously.
In certain embodiments, signal wire can comprise the first grid line group be made up of the grid line of all odd-numbered lines and the second grid line group be made up of the grid line of all even number lines.With further reference to Fig. 4, it illustrates the structural representation of the array base palte being connected different p-wire according to the odd-numbered line grid line of the embodiment of the present application with even number line grid line.
As shown in Figure 4, in the present embodiment, the one end of the first grid line group be made up of all odd-numbered line grid lines is connected with p-wire 411, and the other end is connected with the first pole of transistor 14.Second pole of transistor 14 is connected with the reception line 421 corresponding to p-wire 411.The one end of the first grid line group be made up of all even number line grid lines is connected with p-wire 412, and the other end is connected with the first pole of transistor 14.Second pole of each transistor 14 is connected with the reception line 422 corresponding to p-wire 412, and grid is connected with control circuit 13.Control circuit 13 can control the transistor conducting be successively connected with grid line.Like this, the test signal be applied on signal wire by p-wire is transferred to reception line end through grid line, receives line 421 and can receive the test signal inputted by p-wire 411, receives line 422 and can receive the test signal inputted by p-wire 412.
For the array base palte in embodiment illustrated in fig. 4, its signal wire can be detected by method as shown in Figure 3.Apply enabling signal Stv to control circuit 13, the transistor that each grid line of conducting is corresponding step by step, realizes the scanning of grid line, after the last item grid line has scanned, can apply stop signal Rst, complete the line scanning of array base palte to control circuit 13.When receiving line 421 signal received and the test signal inputted by p-wire 411 and being inconsistent, can determine that the grid line in the first grid line group there occurs short circuit or open circuit.Further, if test signal is periodic signal, can also determine to be short-circuited according to occurring inconsistent timing position or the position of grid line of open circuit.Correspondingly, when receiving line 422 signal received and the test signal inputted by p-wire 412 and being inconsistent, can determine that the grid line in the second grid line group there occurs short circuit or open circuit.Further, if test signal is periodic signal, can also determine to be short-circuited according to occurring inconsistent timing position or the position of grid line of open circuit.
The schematic diagram of a kind of signal that the grid line that Fig. 5 shows array base palte embodiment illustrated in fig. 4 detects.As shown in Figure 5, the first test signal TG1 and the second test signal TG2 is applied by p-wire 411 and 412 respectively to the first grid line group be made up of all odd-numbered line grid lines and the second grid line group of being made up of all even number line grid lines.Wherein, the first test signal TG1 and the second test signal TG2 is square-wave signal, and TG2 has the time delay in 1/4th cycles relative to TG1.The time of each transistor turns is 1/4th of the test signal cycle, in Figure 5, clock signal G1, the G2 of each grid line, G3, G4 ... for the ON time of transistor corresponding to the time representation of high level.Fig. 5 shows the schematic diagram that all grid lines are not short-circuited with Received signal strength during open circuit and input signal.As can be seen from Figure 5, when grid line be not short-circuited or open circuit time, the Received signal strength RG1 of the first signal line group is identical in same timing position polarity with test signal TG1, and the amplitude of signal is also identical; The Received signal strength RG2 of secondary signal line group is identical in same timing position polarity with test signal TG2, and the amplitude of signal is also identical.
To array base palte applying test signal TG1, TG2 as shown in Figure 5 shown in Fig. 4, and when controlling control circuit with the clock signal shown in Fig. 5 successively turn-on transistor, if Received signal strength is consistent with test signal, then can determine that the grid line in the array base palte shown in Fig. 4 is not short-circuited or open circuit.
Article 1 and a kind of signal schematic representation of Article 6 grid line open circuit when the grid line that Fig. 6 shows array base palte embodiment illustrated in fig. 4 detects.As shown in Figure 6, the test signal inputting two groups of grid lines is periodic square-wave signal, and the time delay in two 1/4th cycles of existence between test signal TG1 and TG2.With clock signal G1, the G2 of each grid line, G3, G4 ... for the ON time of transistor corresponding to the time representation of high level.The time that the transistor that each grid line is corresponding is switched on is 1/4th of the square-wave signal cycle.If Article 1 grid line G1 open circuit, Article 1 receives line cannot receive when the transistor turns that G1 is corresponding the high level signal be applied on G1, therefore output low level signal.If Article 6 grid line G6 open circuit, Article 2 receives line cannot receive when the transistor turns that G6 is corresponding the high level signal be applied on G6, therefore output low level signal.In Fig. 6 there is not the upset consistent with TG1 at the timing position place that G1 is corresponding in RG1, and RG2, at the timing position place that G6 is corresponding, the upset consistent with TG2 does not occur.If open circuit occurs G3, then the signal that RG1 receives at G3 place can keep the polarity of lastrow, namely keeps high level signal (Fig. 6 is not shown).Contrast grid line receives the signal (Fig. 5) that line receives under normal circumstances and can find out, if grid line open circuit, receives line, at the timing position that this grid line is corresponding, the upset consistent with test signal can not occur.Then can judge grid line whether open circuit according to following methods: if receive the signal that line receives, at a certain timing position, the upset consistent with corresponding test signal does not occur, determine the grid line generation open circuit that this timing position is corresponding.
With further reference to Fig. 7, Article 1 grid line and a kind of signal schematic representation of Article 2 grid line short circuit when the grid line that it illustrates array base palte embodiment illustrated in fig. 4 detects.As shown in Figure 7, when Article 1 grid line G1 and Article 2 grid line G2 is short-circuited, receive line 421 and receive test signal TG1 and test signal TG2 at the timing position place of G1 conducting simultaneously, at this moment, TG1 is high level signal, and TG2 is low level signal.Therefore, receiving signal RG1 received by line 421 is intermediate level at the timing position that G1 is corresponding, and the amplitude of the signal namely received at this timing position place at RG1 is 1/2nd of test signal TG1 amplitude.When the transistor turns that G2 is corresponding, TG1 and TG2 is high level signal, and therefore, the signal RG2 received received by line 422 is high level at the timing position that G2 is corresponding.It can thus be appreciated that, if the signal that reception line receives is 1/2nd of test signal amplitude in the amplitude of a certain timing position, can determine that the grid line that this timing position is corresponding and next grid line are short-circuited.
Array base palte shown in above composition graphs 4 describes the short circuit of grid line and the detection method of open circuit, is appreciated that for the data line in array base palte, also can adopt the corresponding relation of signal as illustrated in figs. 5-7 to detect.
Please refer to Fig. 8, it illustrates the structural representation of the array base palte being connected different p-wire according to the odd column data line of the embodiment of the present application with even column data line.Array base palte shown in Fig. 8 may be used for detecting data line whether short circuit and open circuit.As shown in Figure 8, array base palte comprises the first reception of p-wire 811, second p-wire 812, first reception line 821, second line 822, control circuit 23, transistor 24 and signal wire.Wherein, except grid line G, signal wire also comprise be made up of the data line of all odd columns the first data line group S1, S3, S5 ..., S (2M-1) (M is positive integer, and 2M-1=m or 2M=m).And the second data line group S2, the S4 to be made up of the data line of all even columns, S6 ..., S (2M) (M is positive integer, and 2M-1=m or 2M=m).
As shown in Figure 8, one end of first data line group is all connected with the first p-wire 811, the other end connects the first pole of a transistor respectively, and the grid of transistor is connected with control circuit 23, and the second pole is connected with the reception line 821 corresponding to this data line group and p-wire 811.One end of second data line group is all connected with the second p-wire 812, and the other end connects the first pole of a transistor respectively, and the grid of this transistor is connected with control circuit 23, and the second pole is connected with the reception line 822 corresponding to this data line group and p-wire 812.
When carrying out data line and detecting, the first data line test signal TS1 and the second data line test signal TS2 can be inputted respectively by p-wire 811 and 812, enabling signal is applied to control circuit, by the control circuit transistor that each data line of conducting is corresponding step by step, signal RS1 and RS2 received by receiving line 821 and 822 judges whether data line is short-circuited, open circuit.
For the array base palte shown in Fig. 8, also can adopt the signal similar with Fig. 5 to detect.If the signal that reception line 821 or 822 receives, at a certain timing position, the upset consistent with corresponding test signal 811 or 812 does not occur, the data line generation open circuit that this timing position is corresponding can be determined; If the signal that reception line 821 or 822 receives is 1/2nd of test signal 811 amplitude in the amplitude of a certain timing position, can determine that the data line that this timing position is corresponding and next data line are short-circuited.
In above composition graphs 4 and the embodiment described by Fig. 8, the signal that can receive by receiving line judges whether grid line or data line are short-circuited or open circuit, and can determine to be short-circuited based on the sequential corresponding relation of the signal received and test signal or the grid line of open circuit or the position of data line, when typesetting space outside not occupying volume, achieve the detection of array base palte signal wire.Compared to prior art, the array base palte that the embodiment of the present application provides and detection method testing cost is low, speed is fast, precision is high, the signal wire of the less array base palte of pixel cell size can be detected, and can detect after unit testing (cellvisualtest), avoid scratching panel during cutting, reduce loss.
It should be noted that, signal wire in the array base palte that the application provides is not limited to the above-mentioned situation by parity rows/column split, multiple method can be adopted to divide into groups to signal wire, only need apply corresponding test signal to signal wire, also can realize the detection of signal wire.The embodiment of the another kind grouping of signal wire in array base palte is described below in conjunction with Fig. 9 and Figure 10.
Please refer to Fig. 9, it illustrates the structural representation of another array base palte according to the embodiment of the present application.As shown in Figure 9, array base palte signal wire and testing circuit, testing circuit comprises the first p-wire 911, second p-wire 912, the 3rd p-wire 913, first receives line 921, second and receives line 922, the 3rd reception line 923, control circuit 13 and transistor 14.Wherein, except data line S, signal wire also comprises by all Gi (i=1,4,7 ..., 3i+1, i are nonnegative integer, and 3i+1≤n) form the first grid line group, by all Gj (j=2,5,8 ... 3j+2, j are nonnegative integer, and 3j+2≤n) the second grid line group of forming and by all Gk (k=3,6,9 ... 3k+3, k are nonnegative integer, and 3j+3≤n) the 3rd grid line group that forms.
As shown in Figure 9, one end of first grid line group is all connected with the first p-wire 911, the other end connects the first pole of a transistor respectively, and the grid of transistor is connected with control circuit 23, and the second pole is connected with the reception line 921 corresponding to this grid line group and p-wire 911.One end of second grid line group is all connected with the second p-wire 912, and the other end connects the first pole of a transistor respectively, and the grid of transistor is connected with control circuit 23, and the second pole is connected with the reception line 922 corresponding to this grid line group and p-wire 912.One end of 3rd grid line group is all connected with the 3rd p-wire 913, and the other end connects the first pole of a transistor respectively, and the grid of transistor is connected with control circuit 23, and the second pole is connected with the reception line 923 corresponding to this grid line group and p-wire 913.
When carrying out data line and detecting, the first grid line test signal TG1, the second grid line test signal TG2 and the 3rd grid line test signal TG3 can be inputted respectively by p-wire 911,912 and 913, enabling signal is applied to control circuit, by the control circuit transistor that each grid line of conducting is corresponding step by step, signal RG1, RG2, RG3 of receiving by receiving line 921,922,923 judge whether grid line is short-circuited, open circuit.
With further reference to Figure 10, the schematic diagram of a kind of signal that the grid line that it illustrates array base palte embodiment illustrated in fig. 9 detects.Wherein, G1, G2, G3, G4, G5, G6 ... represent the signal being applied to each grid line respectively, RG1, RG2, RG3 receive the signal that line 921,922,923 receives when being respectively Article 1 grid line G1 and the G8 open circuit of Article 8 grid line, the signal that RG1 ' receives for receiving line 921 when Article 1 grid line G1 and the G2 short circuit of Article 2 grid line, the signal that RG2 ' receives for receiving line 922 when Article 2 grid line G2 and the G3 short circuit of Article 3 grid line, the signal that RG3 ' receives for receiving line 923 when Article 3 grid line G3 and the G4 short circuit of Article 4 grid line.As shown in Figure 10, using square-wave signal TG1, TG2 and TG3 as input signal, and TG2 and TG1 has the time delay in 1/6th cycles, and TG3 and TG1 has the time delay in 1/3rd cycles.When a certain bar grid line generation open circuit, there is not the upset consistent with test signal in the signal that corresponding reception line receives at the timing position place that this grid line is corresponding; When two adjacent grid lines are short-circuited, corresponding reception line is 1/2nd of test signal amplitude at the signal amplitude that the timing position place that this grid line is corresponding receives.Therefore whether can overturn according to the signal received, whether amplitude changes judges grid line whether short circuit or open circuit, and determine to be short-circuited according to the signal received and the inconsistent timing position of test signal or the grid line position of open circuit.
The detection method of middle array base palte embodiment illustrated in fig. 9 is more than described in conjunction with Figure 10.Similarly, data line also can be divided into groups according to the method similar with grid line in Fig. 9, and adopt the test signal similar or identical with Figure 10 to carry out the detection of data line short circuit or open circuit.
Be square-wave signal with test signal in above-described embodiment be example, describe the detection method of array base palte.Be appreciated that when practical application, multiple multi-form signal can be adopted as test signal, such as sinusoidal signal, periodically pulse signal etc.When detecting, if the signal that reception line receives is inconsistent with corresponding test signal, then can determine that the signal wire be detected there occurs short circuit or open circuit.Further, every one-level shift register can be controlled by control circuit and apply time of high level to transistor, match with test signal, determine and be short-circuited or the signal wire position of open circuit, realize the accurate detection of array base palte cabling.
Present invention also provides a kind of display panel, comprise the array base palte described by above-described embodiment.
Present invention also provides a kind of display, comprise the display panel described by above-described embodiment.
It should be noted that, first of the transistor described in above-described embodiment can be extremely the source electrode of transistor and the pole in draining, and second of transistor can be extremely the source electrode of transistor and another pole in draining.If the source electrode of transistor is the first described pole, then the drain electrode of transistor is the second described pole; If the drain electrode of transistor is the first described pole, then the source electrode of transistor is the second described pole.The application does not limit this.
The array base palte that the above embodiments of the present application provide, signal wire detection method, display panel and display device, by arranging p-wire and receive line in array base palte, different test signals is applied to the signal wire in array base palte, the relativeness of test Received signal strength, achieve the detection of the short circuit of array base palte cabling, open circuit, reduce testing cost, improve accuracy of detection.
More than describe and be only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art are to be understood that, invention scope involved in the application, be not limited to the technical scheme of the particular combination of above-mentioned technical characteristic, also should be encompassed in when not departing from described inventive concept, other technical scheme of being carried out combination in any by above-mentioned technical characteristic or its equivalent feature and being formed simultaneously.The technical characteristic that such as, disclosed in above-mentioned feature and the application (but being not limited to) has similar functions is replaced mutually and the technical scheme formed.
Claims (13)
1. an array base palte, comprises many signal line and testing circuit, it is characterized in that, described testing circuit comprises control circuit, multiple transistor, many p-wires and many reception lines; Each p-wire is connected with one end of at least one signal wire respectively; First pole of each transistor is connected with the other end of a signal line respectively, and grid is connected with an output terminal of described control circuit respectively, and the second pole receives line with one that corresponds to described signal wire respectively and is connected.
2. array base palte according to claim 1, is characterized in that, described signal wire comprises:
The the first grid line group be made up of the grid line of all odd-numbered lines and the second grid line group be made up of the grid line of all even number lines; And/or
The first data line group be made up of the data line of all odd columns and the second data line group be made up of the data line of all even columns.
3. array base palte according to claim 1, is characterized in that, described control circuit comprises the shift register of multiple cascade.
4. a signal wire detection method for array base palte, for detecting the array base palte as described in any one of claim 1-3, described method comprises:
Multiple test signal is applied respectively to multiple signal wire by p-wire;
Enabling signal is applied to control circuit;
The transistor that each signal line of conducting is corresponding step by step;
By described reception line Received signal strength.
5. method according to claim 4, is characterized in that, described enabling signal is high level signal.
6. method according to claim 4, is characterized in that, described signal wire comprises:
The the first grid line group be made up of the grid line of all odd-numbered lines and the second grid line group be made up of the grid line of all even number lines; And/or
The first data line group be made up of the data line of all odd columns and the second data line group be made up of the data line of all even columns.
7. method according to claim 6, is characterized in that, applies periodic first grid line test signal to the first grid line group, applies the second grid line test signal with the first grid line test signal with the time delay in 1/4th cycles to the second grid line group; And/or
Apply periodic first data line test signal to the first data line group, apply the second data line test signal with the first data line test signal with the time delay in 1/4th cycles to the second data line group.
8. method according to claim 6, is characterized in that, the time of each transistor turns is 1/4th of the cycle of described test signal.
9. method according to claim 4, is characterized in that, the signal that described reception line receives is inconsistent with the test signal be applied on the signal wire that is connected with described reception line, determines that described signal wire is short-circuited or open circuit.
10. method according to claim 7, is characterized in that, described first grid line test signal and/or described first data line test signal are square-wave signal.
11. methods according to claim 10, is characterized in that, the signal that described reception line receives, at a certain timing position, the upset consistent with corresponding test signal does not occur, and determine the signal wire generation open circuit that this timing position is corresponding;
The signal that described reception line receives is 1/2nd of test signal amplitude in the amplitude of a certain timing position, determines that the signal wire that this timing position is corresponding and next signal line are short-circuited.
12. 1 kinds of display panels, is characterized in that, comprise as arbitrary in claim 1-3 as described in array base palte.
13. 1 kinds of display device, is characterized in that, comprise display panel according to claim 12.
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