CN111276494B - Array substrate, manufacturing method thereof, display panel and display device - Google Patents
Array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
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- CN111276494B CN111276494B CN202010086997.2A CN202010086997A CN111276494B CN 111276494 B CN111276494 B CN 111276494B CN 202010086997 A CN202010086997 A CN 202010086997A CN 111276494 B CN111276494 B CN 111276494B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 230000003287 optical effect Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 62
- 230000005611 electricity Effects 0.000 claims description 32
- 230000003068 static effect Effects 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 17
- 238000012360 testing method Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 6
- 230000006698 induction Effects 0.000 claims description 2
- 230000005284 excitation Effects 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000002708 enhancing effect Effects 0.000 abstract description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 230000005012 migration Effects 0.000 description 5
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- 230000007547 defect Effects 0.000 description 3
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- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract
The invention discloses an array substrate, a manufacturing method thereof, a display panel and a display device.A first signal is loaded on each grid line of a grid metal layer, and a second signal with the polarity opposite to that of the first signal is loaded on each signal line of a source drain metal layer, so that the second signal is output on a normal signal line, and the first signal is output on a short-circuit signal line, thereby enhancing the signal difference between the normal signal line and the short-circuit signal line and being beneficial to detecting the short-circuit signal line; in addition, the first signals are loaded on the grid lines, and the second signals with the polarity opposite to that of the first signals are loaded on the short-circuit signal lines, so that the excitation deterioration of the short-circuit position is realized, and the optical detector and the thermal infrared imager are convenient to determine the short-circuit position. Therefore, the invention can effectively detect the bad short circuit between the gate metal layer and the source drain metal layer, thereby improving the product yield and the display quality.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
In the substrate manufacturing (Array) stage of a double copper (Cu) display product, a phenomenon that a Gate metal layer (Gate) and a source drain metal layer (SD) are raised due to buffer layer particles (buffer PT) often occurs, so that a short circuit (short) occurs between the Gate metal layer (Gate) and the source drain metal layer (SD); in addition, the Migration (Migration) of copper in the gate metal layer may occur due to an electrostatic discharge (ESD) phenomenon during the manufacturing process, and the migrated copper may contact the source/drain metal layer through the insulating film during the subsequent manufacturing process, thereby causing a short circuit between the gate metal layer and the source/drain metal layer. However, the short-circuit defect is not easily detected in the process of normally detecting the source-drain metal layer, and when such a defect is found at the rear end, it is difficult to perform maintenance, which affects the yield and display quality of the product.
Disclosure of Invention
In view of the above, embodiments of the present invention provide an array substrate, a manufacturing method thereof, a display panel, and a display device, so as to improve the yield and display quality of display products.
Therefore, the method for manufacturing an array substrate provided by the embodiment of the invention comprises the following steps:
providing a substrate base plate;
forming a gate drive circuit comprising a plurality of cascaded shift register units on the substrate, a plurality of gate lines extending in a first direction on a gate metal layer and electrically connected with the shift register units in a one-to-one correspondence manner, a plurality of signal lines extending in a second direction on a source drain metal layer, a first electrostatic discharge wire extending in the first direction and electrically connected with one end of each signal line through a first switch element in a one-to-one correspondence manner, and an electrostatic discharge terminal electrically connected with the first electrostatic discharge wire and multiplexed as a substrate test terminal; the first switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the first electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor;
controlling each shift register unit to independently load a first signal to each grid line, and loading a second signal to each signal line through an open-short circuit test device in sequence via the electrostatic discharge terminal, the first electrostatic discharge wire and the first switch element to determine the signal line with a short circuit, wherein the polarities of the first signal and the second signal are opposite;
controlling each shift register unit to independently load the first signal on each grid line, and determining a short-circuit position on the signal line with the short circuit by using an optical detector and a thermal infrared imager after the second signal is loaded on the signal line with the short circuit through the electrostatic discharge terminal, the first electrostatic discharge wire and the first switch element in sequence through the open-short circuit testing equipment;
and maintaining the short circuit position.
In a possible implementation manner, in the manufacturing method provided by the embodiment of the present invention, while forming the first electrostatic discharge trace extending in the first direction and electrically connected to one end of each of the signal lines through the switch elements in one-to-one correspondence, the method further includes:
forming a second electrostatic discharge wire extending in the first direction and electrically connected to the other end of each of the signal lines through a one-to-one corresponding second switching element, and two third electrostatic discharge wires extending in the second direction and electrically connected to both ends of each of the gate lines through a one-to-one corresponding third switching element, respectively;
the second switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the second electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor;
the third switching element comprises two capacitors and a transistor, wherein a first electrode of the transistor is electrically connected with the third electrostatic discharge wire, a second electrode of the transistor is electrically connected with the grid line, one capacitor is electrically connected between the first electrode of the transistor and the grid electrode, and the other capacitor is electrically connected between the second electrode of the transistor and the grid electrode.
In a possible implementation manner, in the manufacturing method provided in an embodiment of the present invention, after the repairing the short-circuit position, the method further includes:
binding the signal wire, the two third electrostatic discharge wires and the first chip on film, and binding the electrostatic discharge terminal and the gate drive circuit and the second chip on film; or, the signal line, the two third electrostatic discharge wires and the electrostatic discharge terminal are all bound with the first chip on film, and the gate driving circuit is bound with the second chip on film.
In a possible implementation manner, in the manufacturing method provided in an embodiment of the present invention, after the repairing the short circuit position, the method further includes:
removing the electrostatic discharge terminal;
binding the signal wire, the two third electrostatic discharge wires and the first chip on film, and binding the first electrostatic discharge wire and the gate drive circuit and the second chip on film; or, the signal line, the first electrostatic discharge wire and the two third electrostatic discharge wires are all bound with the first chip on film, and the gate driving circuit is bound with the second chip on film.
In a possible implementation manner, in the manufacturing method provided in an embodiment of the present invention, while the signal line and the two third esd traces are all bound to the first chip on film, the method further includes:
and binding the signal lines, the second electrostatic discharge wires and the two third electrostatic discharge wires with a third chip on film, wherein the first chip on film and the third chip on film are separated at two ends of each signal line.
In a possible implementation manner, in the manufacturing method provided in the embodiment of the present invention, the bonding the gate driving circuit and the second chip on film specifically includes:
and binding the grid drive circuit with the second chip on film through wiring or a connecting terminal.
In a possible implementation manner, in the manufacturing method provided in an embodiment of the present invention, forming a plurality of signal lines extending in a second direction on the source drain metal layer specifically includes:
and forming a plurality of data lines, a plurality of high-level signal lines and a plurality of induction lines which extend in the second direction on the source drain metal layer by a one-time composition process.
Based on the same inventive concept, the embodiment of the invention provides an array substrate, and the array substrate is prepared by adopting the manufacturing method.
In a possible implementation manner, the array substrate provided in an embodiment of the present invention includes: the static electricity discharge circuit comprises a grid drive circuit, a plurality of grid lines, a plurality of signal lines and first static electricity discharge wires, wherein the grid drive circuit is provided with a plurality of cascaded shift register units, the grid lines extend in a grid metal layer along a first direction and are electrically connected with the shift register units in a one-to-one correspondence mode, the signal lines extend in a source drain metal layer along a second direction, and the first static electricity discharge wires extend in the first direction and are electrically connected with one end of each signal line through a first switch element in a one-to-one correspondence mode; the first switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the first electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor.
In a possible implementation manner, in the array substrate provided in the embodiment of the present invention, an electrostatic discharge terminal electrically connected to the first electrostatic discharge trace is further included; the electrostatic discharge terminal is multiplexed as a substrate test terminal.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: the second electrostatic discharge wire and the two third electrostatic discharge wires are arranged on the same layer as the first electrostatic discharge wire; wherein,
the second electrostatic discharge routing extends in the first direction and is electrically connected with the other end of each signal line through a one-to-one corresponding second switch element;
the two third electrostatic discharge wires extend in the second direction and are electrically connected with two ends of each grid line through the corresponding third switch elements;
the second switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the second electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor;
the third switching element comprises two capacitors and a transistor, wherein a first electrode of the transistor is electrically connected with the third electrostatic discharge wire, a second electrode of the transistor is electrically connected with the grid line, one capacitor is electrically connected between the first electrode of the transistor and the grid electrode, and the other capacitor is electrically connected between the second electrode of the transistor and the grid electrode.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a first chip on film and a second chip on film;
the first chip on film is respectively bound and connected with the signal wire and the two third electrostatic discharge wires; the second chip on film is respectively bound and connected with the electrostatic discharge terminal and the gate drive circuit, or respectively bound and connected with the first electrostatic discharge wire and the gate drive circuit;
or,
the first chip on film is respectively bound and connected with the signal wire, the two third electrostatic discharge wires and the electrostatic discharge terminal, or respectively bound and connected with the signal wire, the first electrostatic discharge wire and the two third electrostatic discharge wires; the second chip on film is connected with the grid drive circuit in a binding mode.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a third chip on film;
the third chip on film is respectively bound and connected with the signal lines, the second electrostatic discharge wires and the two third electrostatic discharge wires, and the third chip on film and the first chip on film are respectively separated from two ends of each signal line.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the array substrate further includes: a trace or connection terminal;
the grid driving circuit is connected with the second chip on film in a binding mode through the wiring or the connecting terminal.
In a possible implementation manner, in the array substrate provided in an embodiment of the present invention, the signal line includes: a plurality of data lines, a plurality of high level signal lines and a plurality of sensing lines.
Based on the same inventive concept, an embodiment of the present invention provides a display panel, including the array substrate.
Based on the same inventive concept, the embodiment of the invention provides a display device, which comprises the display panel.
The invention has the following beneficial effects:
the array substrate, the manufacturing method thereof, the display panel and the display device provided by the embodiment of the invention comprise the following steps: providing a substrate base plate; forming a gate drive circuit comprising a plurality of cascaded shift register units on a substrate, a plurality of gate lines extending along a first direction on a gate metal layer and electrically connected with the shift register units in a one-to-one correspondence manner, a plurality of signal lines extending along a second direction on a source drain metal layer, first electrostatic discharge wires extending along the first direction and electrically connected with one end of each signal line through a first switch element in a one-to-one correspondence manner, and electrostatic discharge terminals electrically connected with the first electrostatic discharge wires and multiplexed as substrate test terminals; controlling each shift register unit to independently load a first signal to each grid line, and loading a second signal to each signal line through an electrostatic discharge terminal, a first electrostatic discharge wire and a first switch element in sequence by open-short circuit test equipment to determine the signal line with a short circuit, wherein the polarities of the first signal and the second signal are opposite; controlling each shift register unit to independently load a first signal on each grid line, loading a second signal on a signal line which is short-circuited through an electrostatic discharge terminal, a first electrostatic discharge wire and a first switch element in sequence by using open-short circuit testing equipment, and determining a short-circuit position on the signal line which is short-circuited by using an optical detector and a thermal infrared imager; and maintaining the short-circuit position. Loading a first signal on each grid line of the grid metal layer and loading a second signal with the polarity opposite to that of the first signal on each signal line of the source drain metal layer, so that the second signal is output on the normal signal line and the first signal is output on the short-circuit signal line, thereby enhancing the signal difference between the normal signal line and the short-circuit signal line and being beneficial to detecting the short-circuit signal line; in addition, the first signals are loaded on the grid lines, and the second signals with the polarity opposite to that of the first signals are loaded on the short-circuit signal lines, so that the excitation deterioration of the short-circuit position is realized, and the optical detector and the thermal infrared imager are convenient to determine the short-circuit position. Therefore, the invention can effectively detect the bad short circuit between the gate metal layer and the source drain metal layer, thereby improving the product yield and the display quality.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 3 is a waveform diagram of a first signal and a second signal provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a short-circuit signal line according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of detecting a short circuit location according to an embodiment of the present invention;
fig. 6 is a second schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 7 is a third schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 8 is a fourth schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 9 is a fifth schematic structural view of an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. "inner", "outer", "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
For the purpose of explaining the process of detecting a defect, hereinafter, a short circuit occurring between the gate metal layer and the source-drain metal layer due to the buffer layer particles is referred to as a defective type 1, and a short circuit between the gate metal layer and the source-drain metal layer due to copper migration of the gate metal layer is referred to as a defective type 2. In addition, since each of the first switching element, the second switching element, and the third switching element according to the present invention includes two capacitors and one transistor, and only the first pole and the second pole of the transistor are electrically connected to different members on the array substrate, the first switching element, the second switching element, and the third switching element will be collectively referred to as a switching element hereinafter.
As shown in fig. 1, the method for manufacturing an array substrate according to an embodiment of the present invention may specifically include the following steps:
s001, providing a substrate.
S002, forming a gate driving circuit 101 including a plurality of cascaded shift register units on the substrate, a plurality of gate lines 102 extending in the gate metal layer along the first direction X and electrically connected to each shift register unit in a one-to-one correspondence, a plurality of signal lines 103 extending in the source-drain metal layer along the second direction Y, a first electrostatic discharge trace 105 extending in the first direction X and electrically connected to one end of each signal line 103 through a one-to-one correspondence switch element 104, and an electrostatic discharge terminal 106 electrically connected to the first electrostatic discharge trace 105 and multiplexed as a substrate test terminal (AT PAD); the switch element 104 includes two capacitors and a transistor, a first electrode of the transistor is electrically connected to the first esd trace 105, a second electrode of the transistor is electrically connected to the signal line 103, one of the capacitors is electrically connected between the first electrode and the gate of the transistor, and the other capacitor is electrically connected between the second electrode and the gate of the transistor, as shown in fig. 2;
it should be noted that, the specific fabrication of the gate driving circuit 101, the gate line 102, the signal line 103, the first electrostatic discharge trace 105 and the electrostatic discharge terminal 106 can be realized by referring to the prior art. In contrast, in the present invention, the electrostatic discharge terminal 106 is multiplexed as a substrate test terminal to facilitate loading of a test signal to each signal line 103.
And S003, controlling each shift register unit to independently load a first signal S1 to each gate line 102, and loading a second signal S2 to each signal line 103 through the electrostatic discharge terminal 106, the first electrostatic discharge routing 105 and the switching element 104 in sequence by using an open-short test device to determine the signal line 103 with a short circuit, wherein the polarities of the first signal S1 and the second signal S2 are opposite.
Specifically, the signal loading condition of each shift register unit needs to be controlled according to the actual structure of the gate driving circuit 101 in the product, so as to destroy the cascade output relationship between each shift register unit, so that each shift register unit independently loads the first signal S1 to each gate line 102, and the influence caused by the cascade output of each shift register unit is eliminated.
The first signal S1 and the second signal S2 may be Direct Current (DC) signals with opposite polarities, or Alternating Current (AC) signals with opposite polarities, and may be selected according to actual products. The switching element 104 is composed of two capacitors and one transistor. Since the capacitor has the characteristics of alternating current and direct current, the first signal S1 and the second signal S2 loaded in the present invention are alternating current signals, as shown in fig. 3. Due to the principle of capacitive coupling, the voltage at the end of the capacitor electrically connected with the source and drain of the transistor is lower than the voltage at the end of the capacitor electrically connected with the gate of the transistor. Therefore, when the first signal S1 and the second signal S2 are at a high level, one end of the capacitor electrically connected to the source and drain of the transistor is at a first high level, and the other end of the capacitor electrically connected to the gate of the transistor is coupled at a second high level, where the first high level is the same as the high levels of the first signal S1 and the second signal S2, and the second high level is higher than the first high level. The transistor is turned on by the first high level and the second high level, and then a high level of the first signal S1 is input to the gate line 102, or a high level of the second signal S2 is input to the signal line 103. Based on the same principle, a low level of the first signal S1 may be input to the gate line 102, and a low level of the second signal S2 may be input to the signal line 103. The presence of the two capacitors makes it necessary to apply the second signal S2 with a large pulse to the first esd trace 105 for a long time (generally, the duration of the application is 1 hour to 2 hours), so as to couple the gate of the transistor to a high level, thereby turning on the transistor, and further applying the second signal S2 to each signal line 103 through the turned-on transistor. In addition, in the actual display process, in the prior art, the driving signal applied to each signal line 103 and gate line 102 is much smaller than the second signal S2, and the duration is in microseconds, so that the switching element 104 is in the non-operating state, and thus mutual interference between the driving signals applied to different signal lines 103 or gate lines 102 can be effectively avoided.
And S004, controlling each shift register unit to independently load a first signal S1 to each gate line 102, and determining a short-circuit position on the short-circuited signal line 103 by using an optical detector and a thermal infrared imager after loading a second signal S2 to the short-circuited signal line 103 through the electrostatic discharge terminal 106, the first electrostatic discharge trace 105 and the switch element 104 in sequence through an open-short circuit test device.
And S005, maintaining the short circuit position.
In the manufacturing method of the array substrate provided by the embodiment of the invention, the first signal S1 is loaded on each gate line 102 of the gate metal layer, and the second signal S2 with the polarity opposite to that of the first signal S1 is loaded on each signal line 103 of the source-drain metal layer, so that the second signal S2 is output on the normal signal line 103, and the first signal S1 is output on the short-circuit signal line 103, thereby enhancing the signal difference between the normal signal line 103 and the short-circuit signal line 103, and facilitating the detection of the short-circuit signal line 103, as shown in fig. 4; in addition, the first signal S1 is loaded on each grid line 102, and the second signal S2 with the polarity opposite to that of the first signal S1 is loaded on the short-circuit signal line 103, so that the excitation deterioration of the short-circuit position is realized, and the short-circuit position can be conveniently determined by adopting an optical detector and a thermal infrared imager; specifically, as shown in fig. 5, after the pressure excitation, the protrusion phenomenon of the gate metal layer and the source drain metal layer is more obvious, and the optical detector (e.g., an optical microscope) is used to search along the abnormal short-circuit signal line 103, so that the bad type 1 can be found; the defective type 2 caused by the copper migration of the gate metal layer generates heat after the pressure excitation, and thus can be detected by a thermal infrared imager. As described above, the short circuit occurring between the gate metal layer and the source-drain metal layer due to the buffer layer particles is of the defective type 1, and the short circuit between the gate metal layer and the source-drain metal layer due to the copper migration of the gate metal layer is of the defective type 2. Therefore, the invention can effectively detect the bad short circuit between the gate metal layer and the source drain metal layer, thereby improving the product yield and the display quality.
Optionally, in the manufacturing method provided in the embodiment of the present invention, in order to facilitate electrostatic discharge in a product, while the step of forming the first electrostatic discharge trace 105 extending in the first direction X and electrically connected to one end of each signal line 103 is performed, the following steps may be further performed:
forming a second electrostatic discharge trace 107 extending in the first direction X and electrically connected to the other end of each signal line 103 through a one-to-one corresponding switch element 104, where the switch element 104 includes two capacitors and a transistor, a first electrode of the transistor is electrically connected to the second electrostatic discharge trace 107, a second electrode is electrically connected to the signal line 103, one of the capacitors is electrically connected between the first electrode and the gate of the transistor, and the other capacitor is electrically connected between the second electrode and the gate of the transistor; and two third esd traces 108 extending in the second direction Y and electrically connected to two ends of each gate line 102 through the switch elements 104 corresponding to each other one by one, where the switch elements 104 include two capacitors and a transistor, a first electrode of the transistor is electrically connected to the third esd traces 108, a second electrode of the transistor is electrically connected to the gate lines 102, one of the capacitors is electrically connected between the first electrode of the transistor and the gate, and the other capacitor is electrically connected between the second electrode of the transistor and the gate, as shown in fig. 2.
Optionally, in the manufacturing method provided in the embodiment of the present invention, after the step S005 is performed to repair the short-circuit position, the following steps may be further performed:
the signal line 103, the two third esd traces 108 are all bonded to the first flip chip film 109, and the esd terminal 106 and the gate driver circuit 101 are all bonded to the second flip chip film 110, as shown in fig. 6; or, the signal line 103, the two third esd traces 108 and the esd terminals 106 are all bonded to the first chip on film 109, and the gate driving circuit 101 is bonded to the second chip on film 110. Alternatively, as shown in fig. 6, the gate driving circuit 101 is bonded to the second chip on film 110 through the connection terminal 111.
In the situation shown in fig. 6, the static electricity on the first static electricity releasing wires 105 is released through the second flip chip film 110, the static electricity on the second static electricity releasing wires 107 is released to the whole display panel, and the two third static electricity releasing wires 108 are released through the first flip chip film 109, so as to avoid the influence of the high voltage caused by the concentration of the static electricity inside the display panel on the display quality.
Further, in the manufacturing method provided in the embodiment of the present invention, while the signal line 103 and the two third esd traces 108 are all bonded to the first flip chip film 109, the following steps may also be performed:
the signal lines 103, the second esd traces 107 and the two third esd traces 108 are all bonded to the third flip-chip film 112, and the first flip-chip film 109 and the third flip-chip film 112 are separated from each other at two ends of each signal line 103, as shown in fig. 7.
In the case shown in fig. 7, the static electricity on the first static electricity discharging wires 105 is discharged through the second flip-chip film 110, the static electricity on the second static electricity discharging wires 107 is discharged through the third flip-chip film 112, and the two third static electricity discharging wires 108 are discharged through the first flip-chip film 109 and the third flip-chip film 112, so as to prevent the display quality from being affected by the static electricity on the display panel.
Optionally, in the manufacturing method provided in the embodiment of the present invention, after the step S005 is performed to repair the short-circuit position, the following steps may be further performed:
removing the electrostatic discharge terminal 106;
the signal line 103, the two third static electricity releasing lines 108 are all bound with the first chip on film 109, and the first static electricity releasing line 105 and the gate driving circuit 101 are all bound with the second chip on film 110, as shown in fig. 8; or, the signal line 103, the first esd trace 105 and the two third esd traces 108 are all bonded to the first chip on film 109, and the gate driving circuit 101 is bonded to the second chip on film 110. Optionally, as shown in fig. 8, the gate driving circuit 101 is bound to the second chip on film 110 by a trace.
In the situation shown in fig. 8, the static electricity on the first static electricity discharging wires 105 is discharged through the second flip chip film 110, the static electricity on the second static electricity discharging wires 107 is discharged to the whole display panel, and the two third static electricity discharging wires 108 are discharged through the first flip chip film 109, so as to avoid the influence of the high voltage caused by the static electricity concentration inside the display panel on the display quality.
Further, in the manufacturing method provided in the embodiment of the present invention, while the signal line 103 and the two third esd traces 108 are all bonded to the first flip chip film 109, the following steps may be further performed:
the signal lines 103, the second esd traces 107 and the two third esd traces 108 are all bonded to the third flip-chip film 112, and the first flip-chip film 109 and the third flip-chip film 112 are separated from each other at two ends of each signal line 103, as shown in fig. 9.
In the case shown in fig. 9, the static electricity on the first static electricity discharging wires 105 is discharged through the second flip-chip film 110, the static electricity on the second static electricity discharging wires 107 is discharged through the third flip-chip film 112, and the two third static electricity discharging wires 108 are discharged through the first flip-chip film 109 and the third flip-chip film 112, so as to prevent the display quality from being affected by the static electricity on the display panel.
It should be noted that the first chip on film 109 and the third chip on film 112 only provide signals for the signal lines 103, and the second chip on film provides signals for the signal lines 103 and the gate driving circuit 101.
Optionally, in the manufacturing method provided in the embodiment of the present invention, the forming of the plurality of signal lines 103 extending along the second direction Y on the source drain metal layer may be specifically implemented by the following steps:
and forming a plurality of data lines, a plurality of high-level signal lines and a plurality of sensing lines which extend in the second direction Y on the source drain metal layer through a one-time composition process.
That is, the signal line 103 may include a Data line (Data), a high-level signal line (VDD), and a sensing line (Sense) in the present invention, but the signal line 103 is not limited to the Data line, the high-level signal line, and the sensing line in specific implementation.
Based on the same inventive concept, the embodiment of the invention also provides an array substrate, and the array substrate is prepared by adopting the manufacturing method. Because the principle of solving the problems of the array substrate is similar to that of solving the problems of the manufacturing method, the implementation of the array substrate provided by the embodiment of the invention can refer to the implementation of the manufacturing method provided by the embodiment of the invention, and repeated details are not repeated.
Optionally, as shown in fig. 8, the array substrate provided in the embodiment of the present invention includes: a gate driving circuit 101 having a plurality of cascaded shift register units, a plurality of gate lines 102 extending in a first direction X on a gate metal layer and electrically connected to the shift register units in a one-to-one correspondence, a plurality of signal lines 103 extending in a second direction Y on a source-drain metal layer, and first electrostatic discharge traces 105 extending in the first direction X and electrically connected to one end of each signal line 103 through a one-to-one correspondence switching element 104; the switch element 104 includes two capacitors and a transistor, a first electrode of the transistor is electrically connected to the first esd trace 105, a second electrode of the transistor is electrically connected to the signal line 103, one of the capacitors is electrically connected between the first electrode and the gate of the transistor, and the other capacitor is electrically connected between the second electrode and the gate of the transistor.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 6, the array substrate further includes: and an electrostatic discharge terminal 106 electrically connected to the first electrostatic discharge trace 105 and multiplexed as a substrate test terminal.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 6 and 8, the array substrate further includes: a second esd trace 107 and two third esd traces 108 disposed on the same layer as the first esd trace 105; wherein,
the second esd traces 107 extend in the first direction X and are electrically connected to the other end of each signal line 103 through a one-to-one corresponding switch element 104, where the switch element 104 includes two capacitors and a transistor, a first electrode of the transistor is electrically connected to the second esd traces 107, a second electrode of the transistor is electrically connected to the signal line 103, one of the capacitors is electrically connected between the first electrode and the gate of the transistor, and the other capacitor is electrically connected between the second electrode and the gate of the transistor;
the two third esd traces 108 extend in the second direction Y and are electrically connected to two ends of each gate line 102 through the switch elements 104 corresponding to each other one by one, each switch element 104 includes two capacitors and a transistor, a first electrode of the transistor is electrically connected to the third esd traces 108, a second electrode of the transistor is electrically connected to the gate line 102, one of the capacitors is electrically connected between the first electrode of the transistor and the gate, and the other capacitor is electrically connected between the second electrode of the transistor and the gate.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 6 and 8, the array substrate further includes: a first chip on film 109 and a second chip on film 110;
the first flip chip film 109 is respectively bound and connected with the signal line 103 and the two third electrostatic discharge wires 108; the second chip on film 110 is respectively bound and connected with the electrostatic discharge terminal 106 and the gate driving circuit 101, or the second chip on film 110 is respectively bound and connected with the first electrostatic discharge wire 105 and the gate driving circuit 101;
or,
the first chip on film 109 is respectively bound and connected with the signal line 103, the two third electrostatic discharge wires 108 and the electrostatic discharge terminal 106, or the first chip on film 109 is respectively bound and connected with the signal line 103, the first electrostatic discharge wire 105 and the two third electrostatic discharge wires 108; the second chip on film 110 is connected to the gate driving circuit 101 in a bonding manner.
Optionally, in the array substrate provided in the embodiment of the present invention, as shown in fig. 6 to 9, the array substrate further includes: wiring or connection terminals 111;
the gate driving circuit 101 is bound and connected to the second chip on film 110 through a trace or a connection terminal 111.
Optionally, in the array substrate provided in the embodiment of the present invention, the signal line 103 includes: a plurality of data lines, a plurality of high level signal lines and a plurality of sensing lines.
Based on the same inventive concept, the embodiment of the invention further provides a display panel, which comprises the array substrate provided by the embodiment of the invention. The display panel may be an organic electroluminescent display panel (OLED) or a liquid crystal display panel (LCD). As the principle of solving the problem of the display panel is similar to that of solving the problem of the array substrate, the implementation of the display panel provided by the embodiment of the present invention can refer to the implementation of the array substrate provided by the embodiment of the present invention, and repeated details are not repeated.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the display panel provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, an intelligent watch, a fitness wrist strap, and a personal digital assistant. As the principle of the display device to solve the problem is similar to that of the display panel, the display device provided by the embodiment of the present invention can be implemented by the display panel provided by the embodiment of the present invention, and repeated descriptions are omitted.
According to the array substrate, the manufacturing method thereof, the display panel and the display device provided by the embodiment of the invention, the first signal is loaded on each grid line of the grid metal layer, and the second signal with the polarity opposite to that of the first signal is loaded on each signal line of the source drain metal layer, so that the second signal is output on the normal signal line, and the first signal is output on the short-circuit signal line, and therefore, the signal difference between the normal signal line and the short-circuit signal line is enhanced, and the detection of the short-circuit signal line is facilitated; in addition, the first signals are loaded on the grid lines, and the second signals with the polarity opposite to that of the first signals are loaded on the short-circuit signal lines, so that the excitation deterioration of the short-circuit position is realized, and the optical detector and the thermal infrared imager are convenient to determine the short-circuit position. Therefore, the invention can effectively detect the bad short circuit between the gate metal layer and the source drain metal layer, thereby improving the product yield and the display quality.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (17)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate base plate;
forming a gate drive circuit comprising a plurality of cascaded shift register units on the substrate, a plurality of gate lines extending in a first direction on a gate metal layer and electrically connected with the shift register units in a one-to-one correspondence manner, a plurality of signal lines extending in a second direction on a source drain metal layer, a first electrostatic discharge wire extending in the first direction and electrically connected with one end of each signal line through a first switch element in a one-to-one correspondence manner, and an electrostatic discharge terminal electrically connected with the first electrostatic discharge wire and multiplexed as a substrate test terminal; the first switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the first electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor;
controlling each shift register unit to independently load a first signal to each grid line, and loading a second signal to each signal line through an open-short circuit test device in sequence via the electrostatic discharge terminal, the first electrostatic discharge wire and the first switch element to determine the signal line with a short circuit, wherein the polarities of the first signal and the second signal are opposite;
controlling each shift register unit to independently load the first signal on each grid line, and determining a short-circuit position on the signal line with the short circuit by using an optical detector and a thermal infrared imager after the second signal is loaded on the signal line with the short circuit through the electrostatic discharge terminal, the first electrostatic discharge wire and the first switch element in sequence through the open-short circuit testing equipment;
and maintaining the short circuit position.
2. The method according to claim 1, wherein while forming a first esd trace extending in the first direction and electrically connected to one end of each of the signal lines through a one-to-one corresponding first switching element, the method further comprises:
forming a second electrostatic discharge wire extending in the first direction and electrically connected to the other end of each of the signal lines through a one-to-one corresponding second switching element, and two third electrostatic discharge wires extending in the second direction and electrically connected to both ends of each of the gate lines through a one-to-one corresponding third switching element, respectively;
the second switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the second electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor;
the third switching element comprises two capacitors and a transistor, wherein a first electrode of the transistor is electrically connected with the third electrostatic discharge wire, a second electrode of the transistor is electrically connected with the grid line, one capacitor is electrically connected between the first electrode of the transistor and the grid electrode, and the other capacitor is electrically connected between the second electrode of the transistor and the grid electrode.
3. The method of manufacturing of claim 2, further comprising, after repairing the short circuit location:
binding the signal wire, the two third electrostatic discharge wires and the first chip on film, and binding the electrostatic discharge terminal and the gate drive circuit and the second chip on film; or, the signal line, the two third electrostatic discharge wires and the electrostatic discharge terminal are all bound with the first chip on film, and the gate driving circuit is bound with the second chip on film.
4. The method of manufacturing of claim 2, further comprising, after repairing the short circuit location:
removing the electrostatic discharge terminal;
binding the signal wire, the two third electrostatic discharge wires and the first chip on film, and binding the first electrostatic discharge wire and the gate drive circuit and the second chip on film; or, the signal line, the first electrostatic discharge wire and the two third electrostatic discharge wires are all bound with the first chip on film, and the gate driving circuit is bound with the second chip on film.
5. The method according to claim 3 or 4, wherein the signal line, the two third ESD traces and the first COF are all bonded together, and further comprising:
and binding the signal lines, the second electrostatic discharge wires and the two third electrostatic discharge wires with a third chip on film, wherein the first chip on film and the third chip on film are separated at two ends of each signal line.
6. The manufacturing method according to claim 3 or 4, wherein the step of bonding the gate driving circuit and the second chip on film specifically comprises:
and binding the grid drive circuit with the second chip on film through wiring or a connecting terminal.
7. The manufacturing method of any one of claims 1 to 4, wherein a plurality of signal lines extending in the second direction are formed on the source-drain metal layer, and specifically includes:
and forming a plurality of data lines, a plurality of high-level signal lines and a plurality of induction lines which extend in the second direction on the source drain metal layer through a one-time composition process.
8. An array substrate, wherein the array substrate is prepared by the method of any one of claims 1 to 7.
9. The array substrate of claim 8, comprising: the static electricity discharge circuit comprises a grid drive circuit, a plurality of grid lines, a plurality of signal lines and first static electricity discharge wires, wherein the grid drive circuit is provided with a plurality of cascaded shift register units, the grid lines extend in a grid metal layer along a first direction and are electrically connected with the shift register units in a one-to-one correspondence mode, the signal lines extend in a source drain metal layer along a second direction, and the first static electricity discharge wires extend in the first direction and are electrically connected with one end of each signal line through a first switch element in a one-to-one correspondence mode; the first switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the first electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor.
10. The array substrate of claim 9, further comprising: and the electrostatic discharge terminal is electrically connected with the first electrostatic discharge wire and is multiplexed as a substrate test terminal.
11. The array substrate of claim 9 or 10, further comprising: a second electrostatic discharge wire and two third electrostatic discharge wires arranged in the same layer as the first electrostatic discharge wire; wherein,
the second electrostatic discharge wires extend in the first direction and are electrically connected with the other end of each signal wire through a one-to-one corresponding second switch element;
the two third electrostatic discharge wires extend in the second direction and are electrically connected with two ends of each grid line through the corresponding third switch elements;
the second switch element comprises two capacitors and a transistor, wherein a first pole of the transistor is electrically connected with the second electrostatic discharge wire, a second pole of the transistor is electrically connected with the signal line, one capacitor is electrically connected between the first pole and the grid of the transistor, and the other capacitor is electrically connected between the second pole and the grid of the transistor;
the third switching element comprises two capacitors and a transistor, wherein a first electrode of the transistor is electrically connected with the third electrostatic discharge wire, a second electrode of the transistor is electrically connected with the grid line, one capacitor is electrically connected between the first electrode of the transistor and the grid electrode, and the other capacitor is electrically connected between the second electrode of the transistor and the grid electrode.
12. The array substrate of claim 11, further comprising: a first chip on film and a second chip on film;
the first chip on film is respectively bound and connected with the signal wire and the two third electrostatic discharge wires; the second chip on film is respectively bound and connected with the electrostatic discharge terminal and the gate drive circuit, or respectively bound and connected with the first electrostatic discharge wire and the gate drive circuit;
or,
the first chip on film is respectively bound and connected with the signal wire, the two third electrostatic discharge wires and the electrostatic discharge terminal, or respectively bound and connected with the signal wire, the first electrostatic discharge wire and the two third electrostatic discharge wires; the second chip on film is connected with the grid drive circuit in a binding mode.
13. The array substrate of claim 12, further comprising: a third chip on film;
the third chip on film is respectively bound and connected with the signal lines, the second electrostatic discharge wires and the two third electrostatic discharge wires, and the third chip on film and the first chip on film are respectively distributed at two ends of each signal line.
14. The array substrate of claim 12, further comprising: a trace or connection terminal;
the grid driving circuit is connected with the second chip on film in a binding mode through the wiring or the connecting terminal.
15. The array substrate of claim 9 or 10, wherein the signal line comprises: a plurality of data lines, a plurality of high level signal lines and a plurality of sensing lines.
16. A display panel comprising the array substrate according to any one of claims 8 to 15.
17. A display device characterized by comprising the display panel according to claim 16.
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| CN105575301A (en) * | 2015-12-18 | 2016-05-11 | 上海天马微电子有限公司 | Array substrate, signal line detection method, display panel and display device |
| CN107728395A (en) * | 2017-10-31 | 2018-02-23 | 京东方科技集团股份有限公司 | Array base palte, display device, data wire bad detection means and detection method |
| CN109935571A (en) * | 2019-04-02 | 2019-06-25 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, crack detecting method, display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105575301A (en) * | 2015-12-18 | 2016-05-11 | 上海天马微电子有限公司 | Array substrate, signal line detection method, display panel and display device |
| CN107728395A (en) * | 2017-10-31 | 2018-02-23 | 京东方科技集团股份有限公司 | Array base palte, display device, data wire bad detection means and detection method |
| CN109935571A (en) * | 2019-04-02 | 2019-06-25 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, crack detecting method, display device |
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